Wolfgang Grandegger | 2a367c3 | 2011-11-30 23:41:18 +0000 | [diff] [blame] | 1 | #ifndef _CAN_PLATFORM_CC770_H_ |
| 2 | #define _CAN_PLATFORM_CC770_H_ |
| 3 | |
| 4 | /* CPU Interface Register (0x02) */ |
| 5 | #define CPUIF_CEN 0x01 /* Clock Out Enable */ |
| 6 | #define CPUIF_MUX 0x04 /* Multiplex */ |
| 7 | #define CPUIF_SLP 0x08 /* Sleep */ |
| 8 | #define CPUIF_PWD 0x10 /* Power Down Mode */ |
| 9 | #define CPUIF_DMC 0x20 /* Divide Memory Clock */ |
| 10 | #define CPUIF_DSC 0x40 /* Divide System Clock */ |
| 11 | #define CPUIF_RST 0x80 /* Hardware Reset Status */ |
| 12 | |
| 13 | /* Clock Out Register (0x1f) */ |
| 14 | #define CLKOUT_CD_MASK 0x0f /* Clock Divider mask */ |
| 15 | #define CLKOUT_SL_MASK 0x30 /* Slew Rate mask */ |
| 16 | #define CLKOUT_SL_SHIFT 4 |
| 17 | |
| 18 | /* Bus Configuration Register (0x2f) */ |
| 19 | #define BUSCFG_DR0 0x01 /* Disconnect RX0 Input / Select RX input */ |
| 20 | #define BUSCFG_DR1 0x02 /* Disconnect RX1 Input / Silent mode */ |
| 21 | #define BUSCFG_DT1 0x08 /* Disconnect TX1 Output */ |
| 22 | #define BUSCFG_POL 0x20 /* Polarity dominant or recessive */ |
| 23 | #define BUSCFG_CBY 0x40 /* Input Comparator Bypass */ |
| 24 | |
| 25 | struct cc770_platform_data { |
| 26 | u32 osc_freq; /* CAN bus oscillator frequency in Hz */ |
| 27 | |
| 28 | u8 cir; /* CPU Interface Register */ |
| 29 | u8 cor; /* Clock Out Register */ |
| 30 | u8 bcr; /* Bus Configuration Register */ |
| 31 | }; |
| 32 | |
| 33 | #endif /* !_CAN_PLATFORM_CC770_H_ */ |