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LeafOS / LeafOS-Devices / android_kernel_samsung_universal7904 / 9439caafa33e59bf166eefaf39d9d241576dc119 / . / arch / arm64 / boot / dts / exynos / exynos7872.dtsi
blob: 66bf3ca26ee7c549b8b6c68b5549ebc6763edfd3 [file] [log] [blame]
/*
* SAMSUNG EXYNOS7872 SoC device tree source
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SAMSUNG EXYNOS7872 SoC device nodes are listed in this file.
* EXYNOS7872 based board files can include this file and provide
* values for board specfic bindings.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/memreserve/ 0xE0000000 0xD00000;
#include <dt-bindings/soc/samsung/exynos7872.h>
#include <dt-bindings/clock/exynos7872.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/sysmmu/sysmmu.h>
#include <dt-bindings/thermal/thermal.h>
#include "exynos7872-pinctrl.dtsi"
#include "exynos7872-pm-domains.dtsi"
#include "exynos7872-ess.dtsi"
/ {
compatible = "samsung,armv8", "samsung,exynos7872";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <1>;
aliases {
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
pinctrl3 = &pinctrl_3;
uart0 = &serial_0;
uart1 = &serial_1;
uart2 = &serial_2;
uart3 = &serial_3;
uart4 = &serial_4;
uart5 = &serial_5;
hsi2c0 = &hsi2c_0;
hsi2c1 = &hsi2c_1;
hsi2c2 = &hsi2c_2;
hsi2c3 = &hsi2c_3;
hsi2c4 = &hsi2c_4;
hsi2c5 = &hsi2c_5;
hsi2c6 = &hsi2c_6;
hsi2c7 = &hsi2c_7;
hsi2c8 = &hsi2c_8;
hsi2c9 = &hsi2c_9;
spi0 = &spi_0;
spi1 = &spi_1;
spi2 = &spi_2;
spi3 = &spi_3;
spi4 = &spi_4;
mshc0 = &dwmmc_0;
mshc1 = &dwmmc_1;
mshc2 = &dwmmc_2;
dpp0 = &idma_g0;
dpp1 = &idma_g1;
dpp2 = &idma_vg0;
dpp3 = &idma_gf;
dsim0 = &dsim_0;
decon0 = &decon_f;
scaler0 = &scaler_0;
mfc0 = &mfc_0;
};
chipid@10000000 {
compatible = "samsung,exynos7872-chipid";
reg = <0x0 0x10000000 0x100>;
};
reboot {
compatible = "exynos,reboot";
pmu_base = <0x11C80000>;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
hmp {
up_threshold = <524>;
down_threshold = <214>;
semiboost_up_threshold = <254>;
semiboost_down_threshold = <163>;
bootboost-duration-us = <40000000>;
little-id = <1>;
};
cpu0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
};
cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
};
cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
};
cpu4: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a73", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a73", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
};
idle-states {
entry-method = "arm,psci";
BOOTCL_CPU_SLEEP: bootcl-cpu-sleep {
idle-state-name = "c2";
compatible = "exynos,idle-state";
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <35>;
exit-latency-us = <90>;
min-residency-us = <750>;
status = "okay";
};
NONBOOTCL_CPU_SLEEP: nobootcl-cpu-sleep {
idle-state-name = "c2";
compatible = "exynos,idle-state";
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <30>;
exit-latency-us = <75>;
min-residency-us = <2000>;
status = "okay";
};
};
};
psci {
compatible = "arm,psci";
method = "smc";
cpu_suspend = <0xC4000001>;
cpu_off = <0x84000002>;
cpu_on = <0xC4000003>;
};
acpm {
compatible = "samsung,exynos-acpm";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x0 0x11C88000 0x1000>; /* PMU_ALIVE */
acpm-ipc-channel = <4>;
};
acpm_ipc {
compatible = "samsung,exynos-acpm-ipc";
#address-cells = <2>;
#size-cells = <1>;
interrupts = <0 39 0>;
reg = <0x0 0x11C40000 0x1000>, /* AP2APM MAILBOX */
<0x0 0x02052000 0x1B000>; /* APM SRAM */
initdata-base = <0x4B80>;
num-timestamps = <32>;
debug-log-level = <0>;
logging-period = <500>;
dump-base = <0x02052000>;
dump-size = <0x1B000>;
};
acpm_dvfs {
compatible = "samsung,exynos-acpm-dvfs";
acpm-ipc-channel = <5>;
cpu_cold_temp_list = <ACPM_DVFS_MIF>, <ACPM_DVFS_INT>,
<ACPM_DVFS_CPUCL0>, <ACPM_DVFS_CPUCL1>,
<ACPM_DVFS_CAM>, <ACPM_DVFS_DISP>;
gpu_cold_temp_list = <ACPM_DVFS_G3D>;
};
exynos_dm: exynos-dm@17000000 {
compatible = "samsung,exynos-dvfs-manager";
reg = <0x0 0x17000000 0x0>;
acpm-ipc-channel = <1>;
cpufreq_cl0 {
dm-index = <DM_CPU_CL0>;
available = "true";
cal_id = <ACPM_DVFS_CPUCL0>;
};
cpufreq_cl1 {
dm-index = <DM_CPU_CL1>;
available = "true";
cal_id = <ACPM_DVFS_CPUCL1>;
};
devfreq_mif {
dm-index = <DM_MIF>;
available = "true";
policy_use = "true";
cal_id = <ACPM_DVFS_MIF>;
};
devfreq_int {
dm-index = <DM_INT>;
available = "true";
policy_use = "true";
cal_id = <ACPM_DVFS_INT>;
};
devfreq_intcam {
dm-index = <DM_INTCAM>;
available = "false";
cal_id = <0>;
};
devfreq_disp {
dm-index = <DM_DISP>;
available = "true";
cal_id = <ACPM_DVFS_DISP>;
};
devfreq_cam {
dm-index = <DM_CAM>;
available = "true";
cal_id = <ACPM_DVFS_CAM>;
};
dvfs_gpu {
dm-index = <DM_GPU>;
available = "false";
cal_id = <ACPM_DVFS_G3D>;
};
};
devfreq_0: devfreq_mif@17000010 {
compatible = "samsung,exynos-devfreq";
reg = <0x0 0x17000010 0x0>;
devfreq_type = "mif";
devfreq_domain_name = "dvfs_mif";
/* Delay time */
use_delay_time = "true";
delay_time_list = "20";
freq_info = <676000 451000 451000 451000 933000 451000>;
/* initial_freq, default_qos, suspend_freq, min_freq, max_freq reboot_freq */
/* Booting value */
boot_info = <40 933000>;
/* boot_qos_timeout, boot_freq */
use_get_dev = "false";
polling_ms = <0>;
/* governor data */
gov_name = "interactive";
use_reg = "false";
use_tmu = "true";
use_cl_dvfs = "false";
use_sw_clk = "false";
dfs_id = <ACPM_DVFS_MIF>;
acpm-ipc-channel = <1>;
use_acpm = "true";
};
devfreq_1: devfreq_int@17000020 {
compatible = "samsung,exynos-devfreq";
reg = <0x0 0x17000020 0x0>;
devfreq_type = "int";
devfreq_domain_name = "dvfs_int";
/* Delay time */
use_delay_time = "false";
freq_info = <533000 178000 178000 107000 533000 533000>;
/* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
/* Booting value */
boot_info = <40 533000>;
/* boot_qos_timeout, boot_freq */
/* default_dev_profile */
use_get_dev = "false";
polling_ms = <0>;
/* governor data */
gov_name = "interactive";
use_reg = "false";
use_tmu = "true";
use_cl_dvfs = "false";
use_sw_clk = "false";
dfs_id = <ACPM_DVFS_INT>;
acpm-ipc-channel = <1>;
use_acpm = "true";
};
devfreq_2: devfreq_disp@17000040 {
compatible = "samsung,exynos-devfreq";
reg = <0x0 0x17000040 0x0>;
devfreq_type = "disp";
devfreq_domain_name = "dvfs_disp";
/* Delay time */
use_delay_time = "false";
freq_info = <267000 160000 160000 100000 267000 267000>;
/* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
/* Booting value */
boot_info = <40 267000>;
/* boot_qos_timeout, boot_freq */
/* default dev profile */
use_get_dev = "false";
polling_ms = <0>;
/* governor data */
gov_name = "interactive";
use_reg = "false";
use_tmu = "true";
use_cl_dvfs = "false";
use_sw_clk = "false";
dfs_id = <ACPM_DVFS_DISP>;
};
devfreq_3: devfreq_cam@17000050 {
compatible = "samsung,exynos-devfreq";
reg = <0x0 0x17000050 0x0>;
devfreq_type = "cam";
devfreq_domain_name = "dvfs_cam";
/* Delay time */
use_delay_time = "false";
freq_info = <533000 100000 267000 100000 533000 533000>;
/* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
/* Booting value */
boot_info = <40 533000>;
/* boot_qos_timeout, boot_freq */
/* default dev profile */
use_get_dev = "false";
polling_ms = <0>;
/* governor data */
gov_name = "interactive";
use_reg = "false";
use_tmu = "true";
use_cl_dvfs = "false";
use_sw_clk = "false";
dfs_id = <ACPM_DVFS_CAM>;
};
cpufreq {
domain@0 {
device_type = "cpufreq-domain";
sibling-cpus = "0-3";
cal-id = <ACPM_DVFS_CPUCL1>;
dm-type = <DM_CPU_CL0>;
min-freq = <449000>;
/* PM QoS Class ID*/
pm_qos-min-class = <3>;
pm_qos-max-class = <4>;
user-default-qos = <757000>;
dm-constraints {
mif-perf {
const-type = <CONSTRAINT_MIN>;
dm-type = <DM_MIF>;
/* cpu mif */
table = < 1586000 933000
1482000 933000
1352000 933000
1248000 933000
1144000 902000
1014000 902000
902000 835000
839000 728000
757000 676000
676000 546000
546000 451000
449000 0 >;
};
};
};
domain@1 {
device_type = "cpufreq-domain";
sibling-cpus = "4-5";
cal-id = <ACPM_DVFS_CPUCL0>;
dm-type = <DM_CPU_CL1>;
min-freq = <728000>;
/* PM QoS Class ID*/
pm_qos-min-class = <5>;
pm_qos-max-class = <6>;
dm-constraints {
mif-perf {
const-type = <CONSTRAINT_MIN>;
dm-type = <DM_MIF>;
/* cpu mif */
table = < 2184000 933000
2080000 933000
1976000 933000
1872000 933000
1768000 933000
1664000 933000
1560000 933000
1456000 835000
1352000 835000
1248000 676000
1144000 546000
1040000 546000
936000 451000
832000 451000
728000 451000 >;
};
};
};
};
gic:interrupt-controller@10601000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x10601000 0x1000>,
<0x0 0x10602000 0x1000>,
<0x0 0x10604000 0x2000>,
<0x0 0x10606000 0x2000>;
interrupts = <1 9 0xf04>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xff01>,
<1 14 0xff01>,
<1 11 0xff01>,
<1 10 0xff01>;
clock-frequency = <26000000>;
use-clocksource-only;
};
clock: clock-controller@0x10560000 {
compatible = "samsung,exynos7872-clock";
reg = <0x0 0x10560000 0x1000>;
#clock-cells = <1>;
acpm-ipc-channel = <0>;
};
mct@10040000 {
compatible = "samsung,exynos4210-mct";
reg = <0x0 0x10040000 0x800>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&mct_map>;
interrupts = <0>, <1>, <2>, <3>,
<4>, <5>, <6>, <7>,
<8>, <9>, <10>, <11>;
clocks = <&clock OSCCLK>, <&clock GATE_MCT>;
clock-names = "fin_pll", "mct";
use-clockevent-only;
mct_map: mct-map {
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = <0 &gic 0 234 0>,
<1 &gic 0 235 0>,
<2 &gic 0 236 0>,
<3 &gic 0 237 0>,
<4 &gic 0 238 0>,
<5 &gic 0 239 0>,
<6 &gic 0 240 0>,
<7 &gic 0 241 0>,
<8 &gic 0 242 0>,
<9 &gic 0 243 0>,
<10 &gic 0 244 0>,
<11 &gic 0 245 0>;
};
};
/* DMA */
amba {
#address-cells = <2>;
#size-cells = <1>;
compatible = "arm,amba-bus";
interrupt-parent = <&gic>;
ranges;
pdma0: pdma0@10520000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0x10520000 0x1000>;
interrupts = <0 69 0>;
clocks = <&clock GATE_PDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
dma-arwrapper = <0x10524400>,
<0x10524420>,
<0x10524440>,
<0x10524460>,
<0x10524480>,
<0x105244A0>,
<0x105244C0>,
<0x105244E0>;
dma-awwrapper = <0x10524404>,
<0x10524424>,
<0x10524444>,
<0x10524464>,
<0x10524484>,
<0x105244A4>,
<0x105244C4>,
<0x105244E4>;
dma-instwrapper = <0x10524500>;
dma-mask-bit = <36>;
coherent-mask-bit = <36>;
};
};
ITMON@0 {
compatible = "samsung,exynos-itmon";
interrupts = <0 57 0>, /* DATA_BUS */
<0 59 0>; /* PERI_BUS */
};
/* ALIVE */
pinctrl_0: pinctrl@11CB0000 {
compatible = "samsung,exynos7872-pinctrl";
reg = <0x0 0x11CB0000 0x1000>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
wakeup-interrupt-controller {
compatible = "samsung,exynos7-wakeup-eint";
interrupt-parent = <&gic>;
interrupts = <0 16 0>;
samsung,eint-flt-conf;
};
};
/* DISPAUD */
pinctrl_1: pinctrl@148F0000 {
compatible = "samsung,exynos7872-pinctrl";
reg = <0x0 0x148F0000 0x1000>;
interrupts = <0 130 0>;
};
/* FSYS */
pinctrl_2: pinctrl@13430000 {
compatible = "samsung,exynos7872-pinctrl";
reg = <0x0 0x13430000 0x1000>;
interrupts = <0 150 0>;
};
/* TOP */
pinctrl_3: pinctrl@139B0000 {
compatible = "samsung,exynos7872-pinctrl";
reg = <0x0 0x139B0000 0x1000>;
interrupts = <0 266 0>;
};
/* USI_0 */
usi_0: usi@10032000 {
compatible = "samsung,exynos-usi";
reg = <0x0 0x10032000 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_1 */
usi_1: usi@10032004 {
compatible = "samsung,exynos-usi";
reg = <0x0 0x10032004 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_2 */
usi_2: usi@10032008 {
compatible = "samsung,exynos-usi";
reg = <0x0 0x10032008 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
speedy@11CE0000 {
compatible = "samsung,exynos-speedy";
reg = <0x0 0x11CE0000 0x2000>;
interrupts = <0 34 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&speedy_bus>;
clocks = <&clock GATE_SPEEDY_APM>;
clock-names = "gate_speedy";
status = "disabled";
};
/* UART_HEALTH */
serial_0: uart@13800000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x13800000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 246 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_bus>;
clocks = <&clock GATE_UART0>, <&clock UART_0>;
clock-names = "gate_pclk0", "gate_uart0";
status = "disabled";
};
/* UART_BTWIFIFM */
serial_1: uart@13810000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x13810000 0x100>;
samsung,fifo-size = <256>;
interrupts = <0 247 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart1_bus>;
clocks = <&clock GATE_UART1>, <&clock UART_1>;
clock-names = "gate_pclk1", "gate_uart1";
status = "disabled";
samsung,uart-logging;
};
/* UART_DEBUG */
serial_2: uart@13820000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x13820000 0x100>;
samsung,fifo-size = <256>;
interrupts = <0 279 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_bus>;
clocks = <&clock GATE_UART2>, <&clock UART_2>;
clock-names = "gate_pclk2", "gate_uart2";
status = "disabled";
};
/* USI0 */
serial_3: uart@13920000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x13920000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 270 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_bus_single>; /* or <&uart3_bus_dual> */
clocks = <&clock GATE_USI0>, <&clock USI0>;
clock-names = "gate_pclk3", "gate_uart3";
status = "disabled";
};
/* USI1 */
serial_4: uart@13940000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x13940000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 274 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart4_bus_single>; /* or <&uart4_bus_dual> */
clocks = <&clock GATE_USI1>, <&clock USI1>;
clock-names = "gate_pclk4", "gate_uart4";
status = "disabled";
};
/* USI2 */
serial_5: uart@13980000 {
compatible = "samsung,exynos-uart";
samsung,separate-uart-clk;
reg = <0x0 0x13980000 0x100>;
samsung,fifo-size = <64>;
interrupts = <0 278 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart5_bus_single>; /* or <&uart5_bus_dual> */
clocks = <&clock GATE_USI2>, <&clock USI2>;
clock-names = "gate_pclk5", "gate_uart5";
status = "disabled";
};
/* HSI2C_REARSENSOR */
hsi2c_0: hsi2c@138A0000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x138A0000 0x1000>;
interrupts = <0 257 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c0_bus>;
clocks = <&clock GATE_HSI2C0>, <&clock GATE_HSI2C0>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpc1 0 0x1>;
gpio_scl= <&gpc1 1 0x1>;
status = "disabled";
};
/* HSI2C_REARAF */
hsi2c_1: hsi2c@138B0000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x138B0000 0x1000>;
interrupts = <0 258 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c1_bus>;
clocks = <&clock GATE_HSI2C1>, <&clock GATE_HSI2C1>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpc1 2 0x1>;
gpio_scl= <&gpc1 3 0x1>;
status = "disabled";
};
/* HSI2C_FRONTSENSOR */
hsi2c_2: hsi2c@138C0000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x138C0000 0x1000>;
interrupts = <0 259 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c2_bus>;
clocks = <&clock GATE_HSI2C2>, <&clock GATE_HSI2C2>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpc1 4 0x1>;
gpio_scl= <&gpc1 5 0x1>;
status = "disabled";
};
/* HSI2C_DEPTHSENSOR */
hsi2c_3: hsi2c@138D0000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x138D0000 0x1000>;
interrupts = <0 260 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c3_bus>;
clocks = <&clock GATE_HSI2C3>, <&clock GATE_HSI2C3>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpc1 6 0x1>;
gpio_scl= <&gpc1 7 0x1>;
status = "disabled";
};
/* USI0_CH0 */
hsi2c_4: hsi2c@13920000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x13920000 0x1000>;
interrupts = <0 267 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c4_bus>;
clocks = <&clock GATE_USI0>, <&clock GATE_USI0>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpc2 0 0x1>;
gpio_scl= <&gpc2 1 0x1>;
status = "disabled";
};
/* USI0_CH1 */
hsi2c_5: hsi2c@13930000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x13930000 0x1000>;
interrupts = <0 268 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c5_bus>;
clocks = <&clock GATE_USI0>, <&clock GATE_USI0>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpc2 2 0x1>;
gpio_scl= <&gpc2 3 0x1>;
status = "disabled";
};
/* USI1_CH0 */
hsi2c_6: hsi2c@13940000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x13940000 0x1000>;
interrupts = <0 271 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c6_bus>;
clocks = <&clock GATE_USI1>, <&clock GATE_USI1>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpc2 4 0x1>;
gpio_scl= <&gpc2 5 0x1>;
status = "disabled";
};
/* USI1_CH1 */
hsi2c_7: hsi2c@13950000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x13950000 0x1000>;
interrupts = <0 272 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c7_bus>;
clocks = <&clock GATE_USI1>, <&clock GATE_USI1>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpc2 6 0x1>;
gpio_scl= <&gpc2 7 0x1>;
status = "disabled";
};
/* USI2_CH0 */
hsi2c_8: hsi2c@13980000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x13980000 0x1000>;
interrupts = <0 275 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c8_bus>;
clocks = <&clock GATE_USI2>, <&clock GATE_USI2>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpp7 0 0x1>;
gpio_scl= <&gpp7 1 0x1>;
status = "disabled";
};
/* USI2_CH1 */
hsi2c_9: hsi2c@13990000 {
compatible = "samsung,exynos5-hsi2c";
samsung,check-transdone-int;
reg = <0x0 0x13990000 0x1000>;
interrupts = <0 276 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c9_bus>;
clocks = <&clock GATE_USI2>, <&clock GATE_USI2>;
clock-names = "rate_hsi2c", "gate_hsi2c";
samsung,scl-clk-stretching;
gpio_sda= <&gpp8 0 0x1>;
gpio_scl= <&gpp8 1 0x1>;
status = "disabled";
};
/* I2C_FUELGAUGE */
i2c_0: i2c@13830000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x0 0x13830000 0x100>;
interrupts = <0 248 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_bus>;
clocks = <&clock GATE_I2C0>, <&clock GATE_I2C0>;
clock-names = "rate_i2c", "gate_i2c";
status = "disabled";
};
/* I2C_TSP */
i2c_1: i2c@13840000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x0 0x13840000 0x100>;
interrupts = <0 249 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_bus>;
clocks = <&clock GATE_I2C1>, <&clock GATE_I2C1>;
clock-names = "rate_i2c", "gate_i2c";
status = "disabled";
};
/* I2C_TOUCHKEY */
i2c_2: i2c@13850000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x0 0x13850000 0x100>;
interrupts = <0 250 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_bus>;
clocks = <&clock GATE_I2C2>, <&clock GATE_I2C2>;
clock-names = "rate_i2c", "gate_i2c";
status = "disabled";
};
/* I2C_SPKAMP */
i2c_3: i2c@13860000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x0 0x13860000 0x100>;
interrupts = <0 251 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_bus>;
clocks = <&clock GATE_I2C3>, <&clock GATE_I2C3>;
clock-names = "rate_i2c", "gate_i2c";
status = "disabled";
};
/* I2C_IFPMIC */
i2c_4: i2c@13870000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x0 0x13870000 0x100>;
interrupts = <0 252 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_bus>;
clocks = <&clock GATE_I2C4>, <&clock GATE_I2C4>;
clock-names = "rate_i2c", "gate_i2c";
status = "disabled";
};
/* I2C_MUIC */
i2c_5: i2c@13880000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x0 0x13880000 0x100>;
interrupts = <0 253 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5_bus>;
clocks = <&clock GATE_I2C5>, <&clock GATE_I2C5>;
clock-names = "rate_i2c", "gate_i2c";
status = "disabled";
};
/* I2C_NFC */
i2c_6: i2c@13890000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x0 0x13890000 0x100>;
interrupts = <0 254 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6_bus>;
clocks = <&clock GATE_I2C6>, <&clock GATE_I2C6>;
clock-names = "rate_i2c", "gate_i2c";
status = "disabled";
};
/* I2C_APM */
i2c_7: i2c@11CD0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x0 0x11CD0000 0x100>;
interrupts = <0 255 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_bus>;
clocks = <&clock GATE_I2C_APM>, <&clock GATE_I2C_APM>;
clock-names = "rate_i2c", "gate_i2c";
status = "disabled";
};
/* SPI_REARFROM */
spi_0: spi@13900000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x13900000 0x100>;
samsung,spi-fifosize = <256>;
interrupts = <0 255 0>;
/*
dma-mode;
dmas = <&pdma0 19
&pdma0 18>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_SPI0>, <&clock SPI_0>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi0_bus>;
status = "disabled";
};
/* SPI_FRONTFROM */
spi_1: spi@13910000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x13910000 0x100>;
samsung,spi-fifosize = <256>;
interrupts = <0 256 0>;
/*
dma-mode;
dmas = <&pdma0 21
&pdma0 20>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_SPI1>, <&clock SPI_1>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
status = "disabled";
};
/* SPI USI0 */
spi_2: spi@13920000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x13920000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 269 0>;
/*
dma-mode;
dmas = <&pdma0 23
&pdma0 22>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI0>, <&clock USI0>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi2_bus>;
status = "disabled";
};
/* SPI USI1 */
spi_3: spi@13940000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x13940000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 273 0>;
/*
dma-mode;
dmas = <&pdma0 25
&pdma0 24>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI1>, <&clock USI1>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi3_bus>;
status = "disabled";
};
/* SPI USI2 */
spi_4: spi@13980000 {
compatible = "samsung,exynos-spi";
reg = <0x0 0x13980000 0x100>;
samsung,spi-fifosize = <64>;
interrupts = <0 277 0>;
/*
dma-mode;
dmas = <&pdma0 27
&pdma0 26>;
*/
dma-names = "tx", "rx";
swap-mode;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock GATE_USI2>, <&clock USI2>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi4_bus>;
status = "disabled";
};
fmp_0: fmp {
compatible = "samsung,exynos-fmp";
exynos,host-type = "mmc";
exynos-host = <&dwmmc_0>;
exynos,block-type = "mmcblk0p";
exynos,fips-block_offset = <5>;
};
smu_0: smu {
compatible = "samsung,exynos-smu";
};
dwmmc_0: dwmmc0@13500000 {
compatible = "samsung,exynos-dw-mshc";
reg = <0x0 0x13500000 0x2000>,
<0x0 0x13508000 0x200>;
reg-names = "dw_mmc",
"cmdq_mem";
interrupts = <0 146 0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock MMC_EMBD>, <&clock GATE_MMC_EMBD>;
clock-names = "ciu", "ciu_gate";
status = "disabled";
/* smu */
mmc-exynos-smu = <&smu_0>;
};
dwmmc_1: dwmmc1@13510000 {
compatible = "samsung,exynos-dw-mshc";
reg = <0x0 0x13510000 0x2000>;
reg-names = "dw_mmc";
interrupts = <0 145 0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock MMC_SDIO>, <&clock GATE_MMC_SDIO>;
clock-names = "ciu", "ciu_gate";
status = "disabled";
};
dwmmc_2: dwmmc2@13550000 {
compatible = "samsung,exynos-dw-mshc";
reg = <0x0 0x13550000 0x2000>;
reg-names = "dw_mmc";
interrupts = <0 147 0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock MMC_CARD>, <&clock GATE_MMC_CARD>;
clock-names = "ciu", "ciu_gate";
status = "disabled";
};
mali: mali@11500000 {
compatible = "arm,mali";
reg = <0x0 0x11500000 0x5000>;
interrupts = <0 159 0>, <0 160 0>, <0 158 0>;
interrupt-names = "JOB", "MMU", "GPU";
g3d_cmu_cal_id = <ACPM_DVFS_G3D>;
samsung,power-domain = <&pd_g3d>;
#cooling-cells = <2>; /* min followed by max */
};
iommu-domain_mfcmscl {
compatible = "samsung,exynos-iommu-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges;
domain-clients = <&smfc>, <&scaler_0>, <&mfc_0>, <&fimg2d_0>;
};
sysmmu_mfcmscl: sysmmu@12C50000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x12C50000 0x9000>;
interrupts = <0 198 0>, <0 199 0>;
clock-names = "aclk";
clocks = <&clock GATE_SMMU_MFCMSCL>;
sysmmu,secure-irq;
sysmmu,secure_base = <0x12C60000>;
sysmmu,tlb_property =
/* G2D AFBC header */
<(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_NOID>,
/* JPEG */
<(SYSMMU_PORT_NO_PREFETCH_READWRITE(0x1) | SYSMMU_BL2) SYSMMU_ID(0x0)>,
/* MSCALER */
<(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL4) SYSMMU_ID(0x1)>,
<(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID(0x5)>,
<(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID(0x9)>,
<(SYSMMU_PORT_NO_PREFETCH_WRITE(0x1) | SYSMMU_BL4) SYSMMU_ID(0x21)>,
<(SYSMMU_PORT_NO_PREFETCH_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x25)>,
<(SYSMMU_PORT_NO_PREFETCH_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x29)>,
/* G2D : Do not assign */
<SYSMMU_NOID SYSMMU_NOID>,
<SYSMMU_NOID SYSMMU_NOID>,
<SYSMMU_NOID SYSMMU_NOID>,
<SYSMMU_NOID SYSMMU_NOID>,
<SYSMMU_NOID SYSMMU_NOID>,
<SYSMMU_NOID SYSMMU_NOID>,
<SYSMMU_NOID SYSMMU_NOID>,
<SYSMMU_NOID SYSMMU_NOID>,
<SYSMMU_NOID SYSMMU_NOID>,
/* MFC */
<(SYSMMU_PORT_NO_PREFETCH_READWRITE(0x1) | SYSMMU_BL8) SYSMMU_ID_MASK(0x3, 0x3)>;
#iommu-cells = <0>;
};
smfc: smfc@12C00000 {
compatible = "samsung,exynos8890-jpeg";
reg = <0x0 0x12C00000 0x1000>;
interrupts = <0 194 0>;
clocks = <&clock GATE_JPEG>;
clock-names = "gate";
iommus = <&sysmmu_mfcmscl>;
samsung,power-domain = <&pd_mfcmscl>;
};
scaler_0: scaler@12C10000 {
compatible = "samsung,exynos5-scaler";
reg = <0x0 0x12C10000 0x1000>;
interrupts = <0 195 0>;
clocks = <&clock GATE_MSCL>;
clock-names = "gate";
iommus = <&sysmmu_mfcmscl>;
samsung,power-domain = <&pd_mfcmscl>;
};
mfc_0: mfc0@12C30000 {
compatible = "samsung,mfc-v6";
reg = <0x0 0x12C30000 0x10000>;
interrupts = <0 197 0>;
clock-names = "aclk_mfc";
clocks = <&clock GATE_MFC>;
iommus = <&sysmmu_mfcmscl>;
samsung,power-domain = <&pd_mfcmscl>;
status = "ok";
ip_ver = <16>;
clock_rate = <400000000>;
min_rate = <100000>;
num_qos_steps = <3>;
max_mb = <1518592>;
mfc_qos_table {
mfc_qos_variant_0 {
thrd_mb = <0>;
freq_mfc = <267000>;
freq_int = <267000>;
freq_mif = <451000>;
freq_cpu = <0>;
freq_kfc = <0>;
mo_value = <0>;
time_fw = <193>;
};
mfc_qos_variant_1 {
thrd_mb = <253886>;
freq_mfc = <333000>;
freq_int = <333000>;
freq_mif = <676000>;
freq_cpu = <0>;
freq_kfc = <0>;
mo_value = <0>;
time_fw = <150>;
};
mfc_qos_variant_2 {
thrd_mb = <525852>;
freq_mfc = <533000>;
freq_int = <533000>;
freq_mif = <903000>;
freq_cpu = <0>;
freq_kfc = <0>;
mo_value = <0>;
time_fw = <103>;
};
};
};
fimg2d_0: fimg2d@12C20000 {
compatible = "samsung,s5p-fimg2d";
reg = <0x0 0x12C20000 0x1000>;
interrupts = <0 196 0>;
clocks = <&clock GATE_G2D>;
clock-names="gate";
iommus = <&sysmmu_mfcmscl>;
samsung,power-domain = <&pd_mfcmscl>;
hw_ppc = <1400>, <1200>, <1900>;
skia_qos_table = <0 0 1014000
0 0 1014000
0 0 845000
0 0 845000
0 0 676000
0 0 0
>;
};
iommu-domain_is {
compatible = "samsung,exynos-iommu-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges;
domain-clients = <&fimc_is>, <&fimc_is_sensor0>,
<&fimc_is_sensor1>,
<&camerapp_gdc>;
};
sysmmu_is: sysmmu@14480000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x14480000 0x9000>;
interrupts = <0 183 0>;
clock-names = "aclk";
clocks = <&clock GATE_SMMU_IS>;
sysmmu,tlb_property =
/* 3AA, ISP */
<(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL1) SYSMMU_NOID>,
/* CSIS */
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x7F)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x8, 0x7F)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x10, 0x7F)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x18, 0x7F)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x40, 0x7F)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x48, 0x7F)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x50, 0x7F)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x58, 0x7F)>,
/* 3AA */
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0x1)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0x9)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0x11)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0x19)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0x21)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0x29)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0x31)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0x39)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0x41)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0x49)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x3) | SYSMMU_BL1) SYSMMU_ID(0x1)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x3) | SYSMMU_BL1) SYSMMU_ID(0x9)>,
/* MC-SCALER */
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0x2)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0xA)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0x12)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0x1A)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0x22)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0x32)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x3) | SYSMMU_BL1) SYSMMU_ID(0x2)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x3) | SYSMMU_BL1) SYSMMU_ID(0xA)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x3) | SYSMMU_BL1) SYSMMU_ID(0x1A)>,
/* TPU */
<(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x2) | SYSMMU_BL1) SYSMMU_ID(0x4)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x2) | SYSMMU_BL1) SYSMMU_ID(0x4)>,
/* VRA */
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0x3)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x3) | SYSMMU_BL1) SYSMMU_ID(0x3)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x3) | SYSMMU_BL1) SYSMMU_ID(0xB)>;
sysmmu,slot_property = <0xFF 0xFF00>;
#iommu-cells = <0>;
};
iommu-domain_disp {
compatible = "samsung,exynos-iommu-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges;
domain-clients = <&idma_g0>, <&idma_g1>, <&idma_vg0>, <&idma_gf>;
};
sysmmu_dpu: sysmmu@148C00000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x148C0000 0x9000>;
interrupts = <0 128 0>;
clock-names = "aclk";
clocks = <&clock GATE_SMMU_DPU>;
sysmmu,tlb_property =
<(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0) | SYSMMU_BL1) SYSMMU_NOID>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID(0x1)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID(0x0)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID(0x2)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID(0x6)>,
<(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID(0x8)>;
#iommu-cells = <0>;
};
tmuctrl_0: BIG@10070000 {
compatible = "samsung,exynos7872-tmu";
reg = <0x0 0x10070000 0x400>;
interrupts = <0 231 0>;
tmu_name = "BIG";
id = <0>;
sensors = <1>;
sensing_mode = "max";
hotplug_enable = <1>;
hotplug_in_threshold = <91>;
hotplug_out_threshold = <96>;
#include "exynos7872-tmu-sensor-conf.dtsi"
};
tmuctrl_1: LITTLE@10070000 {
compatible = "samsung,exynos7872-tmu";
reg = <0x0 0x10070000 0x400>;
interrupts = <0 231 0>;
tmu_name = "LITTLE";
id = <1>;
sensors = <1>;
sensing_mode = "max";
#include "exynos7872-tmu-sensor-conf.dtsi"
};
tmuctrl_2: GPU@10070000 {
compatible = "samsung,exynos7872-tmu";
reg = <0x0 0x10070000 0x400>;
interrupts = <0 231 0>;
tmu_name = "GPU";
id = <2>;
sensors = <1>;
sensing_mode = "max";
/* gpu cooling related table */
/* flags, driver_data(index), frequency */
gpu_idx_num = <6>;
gpu_cooling_table = < 0 0 1220000
0 1 1146000
0 2 845000
0 3 545000
0 4 343000
0 5 TABLE_END>;
#include "exynos7872-tmu-sensor-conf.dtsi"
};
thermal-zones {
big_thermal: BIG {
zone_name = "BIG_THERMAL";
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tmuctrl_0>;
trips {
big_alert0: big-alert0 {
temperature = <20000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
big_alert1: big-alert1 {
temperature = <76000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
big_alert2: big-alert2 {
temperature = <81000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
big_alert3: big-alert3 {
temperature = <86000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
big_alert4: big-alert4 {
temperature = <91000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
big_alert5: big-alert5 {
temperature = <96000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
big_alert6: big-alert6 {
temperature = <101000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
big_hot: big-hot {
temperature = <115000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "hot";
};
};
cooling-maps {
map0 {
trip = <&big_alert0>;
/* Corresponds to 2184MHz at freq_table */
cooling-device = <&cpu4 0 0>;
};
map1 {
trip = <&big_alert1>;
/* Corresponds to 1872Hz at freq_table */
cooling-device = <&cpu4 0 3>;
};
map2 {
trip = <&big_alert2>;
/* Corresponds to 1872MHz at freq_table */
cooling-device = <&cpu4 0 3>;
};
map3 {
trip = <&big_alert3>;
/* Corresponds to 1560MHz at freq_table */
cooling-device = <&cpu4 0 6>;
};
map4 {
trip = <&big_alert4>;
/* Corresponds to 1144MHz at freq_table */
cooling-device = <&cpu4 0 8>;
};
map5 {
trip = <&big_alert5>;
/* Corresponds to 728MHz at freq_table */
cooling-device = <&cpu4 0 10>;
};
map6 {
trip = <&big_alert6>;
/* Corresponds to 728MHz at freq_table */
cooling-device = <&cpu4 0 10>;
};
map7 {
trip = <&big_hot>;
/* Corresponds to 728MHz at freq_table */
cooling-device = <&cpu4 0 10>;
};
};
};
little_thermal: LITTLE {
zone_name = "LITTLE_THERMAL";
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tmuctrl_1>;
trips {
little_alert0: little-alert0 {
temperature = <20000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
little_alert1: little-alert1 {
temperature = <76000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
little_alert2: little-alert2 {
temperature = <81000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
little_alert3: little-alert3 {
temperature = <86000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
little_alert4: little-alert4 {
temperature = <91000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
little_alert5: little-alert5 {
temperature = <96000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
little_alert6: little-alert6 {
temperature = <101000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
little_hot: little-hot {
temperature = <115000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "hot";
};
};
cooling-maps {
map0 {
trip = <&little_alert0>;
/* Corresponds to 1586MHz at freq_table */
cooling-device = <&cpu0 0 0>;
};
map1 {
trip = <&little_alert1>;
/* Corresponds to 1586MHz at freq_table */
cooling-device = <&cpu0 0 0>;
};
map2 {
trip = <&little_alert2>;
/* Corresponds to 1586MHz at freq_table */
cooling-device = <&cpu0 0 0>;
};
map3 {
trip = <&little_alert3>;
/* Corresponds to 1482MHz at freq_table */
cooling-device = <&cpu0 0 1>;
};
map4 {
trip = <&little_alert4>;
/* Corresponds to 1248MHz at freq_table */
cooling-device = <&cpu0 0 3>;
};
map5 {
trip = <&little_alert5>;
/* Corresponds to 1144MHz at freq_table */
cooling-device = <&cpu0 0 4>;
};
map6 {
trip = <&little_alert6>;
/* Corresponds to 449MHz at freq_table */
cooling-device = <&cpu0 0 11>;
};
map7 {
trip = <&little_hot>;
/* Corresponds to 449MHz at freq_table */
cooling-device = <&cpu0 0 11>;
};
};
};
gpu_thermal: GPU {
zone_name = "GPU_THERMAL";
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tmuctrl_2>;
trips {
gpu_alert0: gpu-alert0 {
temperature = <20000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
gpu_alert1: gpu-alert1 {
temperature = <76000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
gpu_alert2: gpu-alert2 {
temperature = <81000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
gpu_alert3: gpu-alert3 {
temperature = <86000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
gpu_alert4: gpu-alert4 {
temperature = <91000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
gpu_alert5: gpu-alert5 {
temperature = <96000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
gpu_alert6: gpu-alert6 {
temperature = <101000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
gpu_hot: gpu-hot {
temperature = <115000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "hot";
};
};
cooling-maps {
map0 {
trip = <&gpu_alert0>;
/* Corresponds to 1220MHz at freq_table */
cooling-device = <&mali 0 0>;
};
map1 {
trip = <&gpu_alert1>;
/* Corresponds to 1220Hz at freq_table */
cooling-device = <&mali 0 0>;
};
map2 {
trip = <&gpu_alert2>;
/* Corresponds to 1220Mz at freq_table */
cooling-device = <&mali 0 0>;
};
map3 {
trip = <&gpu_alert3>;
/* Corresponds to 1146MHz at freq_table */
cooling-device = <&mali 0 1>;
};
map4 {
trip = <&gpu_alert4>;
/* Corresponds to 845MHz at freq_table */
cooling-device = <&mali 0 2>;
};
map5 {
trip = <&gpu_alert5>;
/* Corresponds to 545MHz at freq_table */
cooling-device = <&mali 0 3>;
};
map6 {
trip = <&gpu_alert6>;
/* Corresponds to 343MHz at freq_table */
cooling-device = <&mali 0 4>;
};
map7 {
trip = <&gpu_hot>;
/* Corresponds to 343MHz at freq_table */
cooling-device = <&mali 0 4>;
};
};
};
};
idma_g0: dpp@0x148B1000{
compatible = "samsung,exynos7872-dpp";
#pb-id-cells = <3>;
reg = <0x0 0x14851000 0x1000>, <0x0 0x148B1000 0x1000>, <0x0 0x148B0000 0x100>;
interrupts = <0 121 0>;
iommus = <&sysmmu_dpu>;
/* power domain */
samsung,power-domain = <&pd_dispaud>;
memory-region = <&fb_handover>;
};
idma_g1: dpp@0x148B2000{
compatible = "samsung,exynos7872-dpp";
#pb-id-cells = <3>;
reg = <0x0 0x14852000 0x1000>, <0x0 0x148B2000 0x1000>;
interrupts = <0 122 0>;
iommus = <&sysmmu_dpu>;
/* power domain */
samsung,power-domain = <&pd_dispaud>;
};
idma_gf: dpp@0x148B3000{
compatible = "samsung,exynos7872-dpp";
#pb-id-cells = <3>;
reg = <0x0 0x14853000 0x1000>, <0x0 0x148B3000 0x1000>;
interrupts = <0 123 0>;
iommus = <&sysmmu_dpu>;
/* power domain */
samsung,power-domain = <&pd_dispaud>;
};
idma_vg0: dpp@0x148B4000{
compatible = "samsung,exynos7872-dpp";
#pb-id-cells = <3>;
reg = <0x0 0x14854000 0x1000>, <0x0 0x148B4000 0x1000>;
interrupts = <0 124 0>, <0 120 0>;
iommus = <&sysmmu_dpu>;
/* power domain */
samsung,power-domain = <&pd_dispaud>;
};
disp_ss: disp_ss@0x14820000 {
compatible = "samsung,exynos7872-disp_ss";
reg = <0x0 0x14820000 0x10>;
};
pmu_system_controller: system-controller@11c80000 {
compatible = "samsung,exynos7872-pmu", "syscon";
reg = <0x0 0x11c80000 0x10000>;
};
exynos-pmu {
compatible = "samsung,exynos-pmu";
samsung,syscon-phandle = <&pmu_system_controller>;
};
mipi_phy_dsim: phy_m4s4_dsi@0x12821008 {
compatible = "samsung,mipi-phy-dsim";
samsung,pmu-syscon = <&pmu_system_controller>;
isolation = <0x674>;
/* PHY reset be controlled from DSIM */
/* reg = <0x0 0x12821008 0x4>; */
/* reset = <0 1>; */
/* init = <4 5>; */ /* PHY reset control path bit of SYSREG */
#phy-cells = <1>;
};
dsim_0: dsim@0x14870000 {
compatible = "samsung,exynos7872-dsim";
reg = <0x0 0x14870000 0x100>;
interrupts = <0 125 0>;
phys = <&mipi_phy_dsim 1>;
phy-names = "dsim_dphy";
/* power domain */
samsung,power-domain = <&pd_dispaud>;
};
decon_f: decon_f@0x14860000 {
compatible = "samsung,exynos7872-decon";
#pb-id-cells = <4>;
reg = <0x0 0x14860000 0x10000>;
/* under-run, frame start, frame done, extra */
interrupts = <0 115 0>, <0 114 0>, <0 113 0>, <0 112 0>;
/* clock */
clock-names = "aclk";
clocks = <&clock GATE_DPU_DECON0>;
/* pinctrl */
pinctrl-names = "hw_te_on", "hw_te_off";
pinctrl-0 = <&decon_f_te_on>;
pinctrl-1 = <&decon_f_te_off>;
/* power domain */
samsung,power-domain = <&pd_dispaud>;
max_win = <4>; /* chagne to 6 ->4 */
default_win = <3>;
default_idma = <0>;
psr_mode = <2>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */
trig_mode = <0>; /* 0: hw trigger, 1: sw trigger */
dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */
/* 0: DSI, 1: eDP, 2:HDMI, 3: WB */
out_type = <0>;
/* 0: DSI0, 1: DSI1, 2: DSI2 */
out_idx = <0>;
#address-cells = <2>;
#size-cells = <1>;
ranges;
/* EINT for TE */
/* TE is located in TOP */
gpios = <&gpc0 3 0xf>;
/* sw te pending register */
te_eint {
/* NWEINT_GPC0_PEND (GPC0_3:TE) */
reg = <0x0 0x139B0A38 0x4>;
};
cam-stat {
reg = <0x0 0x11c84064 0x4>;
};
};
udc: usb@13600000 {
compatible = "samsung,exynos-dwusb";
clocks = <&clock GATE_USB20DRD_HSDRD>, <&clock GATE_USB20DRD_USB>;
clock-names = "hsdrd", "usb";
reg = <0x0 0x13600000 0x10000>;
#address-cells = <2>;
#size-cells = <1>;
ranges;
status = "disabled";
usbdrd_dwc3: dwc3 {
compatible = "synopsys,dwc3";
reg = <0x0 0x13600000 0x10000>;
interrupts = <0 135 0>;
//suspend_clk_freq = <66000000>;
tx-fifo-resize = <0>;
adj-sof-accuracy = <0>;
is_not_vbus_pad = <1>;
enable_sprs_transfer = <1>;
phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
phy-names = "usb2-phy", "usb3-phy";
};
};
usbdrd_phy: phy@135F0000 {
compatible = "samsung,exynos-usbdrd-phy";
reg = <0x0 0x135F0000 0x100>;
clocks = <&clock GATE_USB20DRD_HSDRD>, <&clock GATE_USB20DRD_USB>, <&clock WIFI2AP_USBPLL>;
clock-names = "hsdrd", "usb", "usbpll";
samsung,pmu-syscon = <&pmu_system_controller>;
pmu_mask = <0x0>;
pmu_offset = <0x66c>;
phy_version = <0x212>;
/* if it doesn't need phy user mux,
you should write "none"
but refclk shouldn't be omitted */
phyclk_mux = "none";
phy_refclk = "usbpll";
/* if it has the other phy, it must be set to 1 */
has_other_phy = <0>;
/* ip type */
/* USB3DRD = 0
USB3HOST = 1
USB2DRD = 2
USB2HOST = 3 */
ip_type = <0x2>;
/* for PHY CAL */
/* choice only one item */
phy_refsel_clockcore = <1>;
phy_refsel_ext_osc = <0>;
phy_refsel_xtal = <0>;
phy_refsel_diff_pad = <0>;
phy_refsel_diff_internal = <0>;
phy_refsel_diff_single = <0>;
/* true : 1 , false : 0 */
use_io_for_ovc = <0>;
common_block_disable = <1>;
is_not_vbus_pad = <1>;
request_extrefclk = <1>;
status = "disabled";
#phy-cells = <1>;
ranges;
};
rtc@11CA0000 {
compatible = "samsung,exynos8-rtc";
reg = <0x0 0x11CA0000 0x100>;
interrupts = <0 29 0>, <0 30 0>;
};
sec_pwm: pwm@13970000 {
compatible = "samsung,s3c6400-pwm";
reg = <0x0 0x13970000 0x1000>;
samsung,pwm-outputs = <0>, <1>, <2>, <3>, <4>;
#pwm-cells = <3>;
clocks = <&clock GATE_PWM_MOTOR>,
<&clock_pwm 1>, <&clock_pwm 2>,
<&clock_pwm 5>, <&clock_pwm 6>,
<&clock_pwm 7>, <&clock_pwm 8>,
<&clock_pwm 10>, <&clock_pwm 11>,
<&clock_pwm 12>, <&clock_pwm 13>;
clock-names = "gate_timers",
"pwm-scaler0", "pwm-scaler1",
"pwm-tdiv0", "pwm-tdiv1",
"pwm-tdiv2", "pwm-tdiv3",
"pwm-tin0", "pwm-tin1",
"pwm-tin2", "pwm-tin3";
status = "ok";
};
clock_pwm: pwm-clock-controller@13970000 {
compatible = "samsung,exynos-pwm-clock";
reg = <0x0 0x13970000 0x50>;
#clock-cells = <1>;
};
exynos_adc: adc@105A0000 {
compatible = "samsung,exynos-adc-v3";
reg = <0x0 0x105A0000 0x100>;
interrupts = <0 63 0>;
#io-channel-cells = <1>;
io-channel-ranges;
clocks = <&clock GATE_WRAP_ADC_IF_0>;
clock-names = "gate_adcif";
};
watchdog@10060000 {
compatible = "samsung,exynos8-wdt";
reg = <0x0 0x10060000 0x100>;
interrupts = <0 233 0>;
clocks = <&clock OSCCLK>, <&clock GATE_WDT_CLUSTER1>;
clock-names = "rate_watchdog", "gate_watchdog";
timeout-sec = <30>;
samsung,syscon-phandle = <&pmu_system_controller>;
};
mailbox_gnss: mcu_ipc@105D0000 {
compatible = "samsung,exynos-shd-ipc-mailbox";
reg = <0x0 0x105D0000 180>;
mcu,name = "mcu_ipc_gnss";
mcu,id = <1>;
interrupts = <GIC_SPI 56 IRQ_TYPE_NONE>;
};
gnss_pdata {
status = "okay";
compatible = "samsung,gnss_shdmem_if";
shmem,name = "KEPLER";
shmem,device_node_name = "gnss_ipc";
/* ACTIVE WATCHDOG WAKEUP */
interrupts = <GIC_SPI 20 IRQ_TYPE_NONE>,
<GIC_SPI 165 IRQ_TYPE_NONE>,
<GIC_SPI 164 IRQ_TYPE_NONE>;
interrupt-names = "ACTIVE", "WATCHDOG", "WAKEUP";
memory-region = <&gnss_reserved>;
mbox_info = <&mailbox_gnss>;
mbx,int_ap2gnss_bcmd = <0>;
mbx,int_ap2gnss_req_fault_info = <1>;
mbx,int_ap2gnss_ipc_msg = <2>;
mbx,int_ap2gnss_ack_wake_set = <3>;
mbx,int_ap2gnss_ack_wake_clr = <4>;
mbx,irq_gnss2ap_bcmd = <0>;
mbx,irq_gnss2ap_rsp_fault_info = <1>;
mbx,irq_gnss2ap_ipc_msg = <2>;
mbx,irq_gnss2ap_req_wake_clr = <4>;
mbx,reg_bcmd_ctrl = <0>, <1>, <2>, <3>;
reg_rx_ipc_msg = <1 5>;
reg_tx_ipc_msg = <1 4>;
reg_rx_head = <1 3>;
reg_rx_tail = <1 2>;
reg_tx_head = <1 1>;
reg_tx_tail = <1 0>;
fault_info = <1 0x200000 0x180000>;
shmem,ipc_offset = <0x380000>;
shmem,ipc_size = <0x80000>;
shmem,ipc_reg_cnt = <32>;
};
/* USIM DETECTION FOR CP */
usim_det {
compatible = "samsung,exynos-usim-detect";
mbx_ap2cp_united_status = <2>;
mif,int_usim0_det_level = <4>;
mif,int_usim1_det_level = <5>;
sbi_usim0_det_mask = <1>;
sbi_usim0_det_pos = <18>;
sbi_usim1_det_mask = <1>;
sbi_usim1_det_pos = <19>;
};
exynos-pm {
compatible = "samsung,exynos-pm";
reg = <0x0 0x11CB0000 0x1000>,
<0x0 0x10601200 0x100>;
reg-names = "gpio_alive_base",
"gicd_ispendrn_base";
num-eint = <24>;
num-gic = <16>;
suspend_mode_idx = <8>; /* SYS_SLEEP */
suspend_psci_idx = <133>; /* PSCI_SYSTEM_SLEEP */
cp_call_mode_idx = <10>; /* SYS_SLEEP_AUD_ON */
cp_call_psci_idx = <133>; /* PSCI_SYSTEM_SLEEP */
wkup_stats = <0x600 0x604 0x608 0x640>;
wkup_by_eint = <0 0>; /* <wakeup_stat_idx bit_field> */
wkup_by_rtc_alarm = <0 1>; /* <wakeup_stat_idx bit_field> */
eint_wkup_masks = <0x0648>;
eint_pends = <0xa00 0xa04 0xa08>;
};
exynos-powermode {
cpd_residency = <3000>;
sicd_residency = <3000>;
cpd_enabled = <1>;
sicd_enabled = <1>;
idle-ip = "13970000.pwm", /* [ 0] pwm */
"105a0000.adc", /* [ 1] adc */
"138a0000.hsi2c", /* [ 2] hsi2c_0 */
"138b0000.hsi2c", /* [ 3] hsi2c_1 */
"138c0000.hsi2c", /* [ 4] hsi2c_2 */
"138d0000.hsi2c", /* [ 5] hsi2c_3 */
"13920000.hsi2c", /* [ 6] hsi2c_4 */
"13930000.hsi2c", /* [ 7] hsi2c_5 */
"13940000.hsi2c", /* [ 8] hsi2c_6 */
"13950000.hsi2c", /* [ 9] hsi2c_7 */
"13980000.hsi2c", /* [10] hsi2c_8 */
"13990000.hsi2c", /* [11] hsi2c_9 */
"13900000.spi", /* [12] spi_0 */
"13910000.spi", /* [13] spi_1 */
"13920000.spi", /* [14] spi_2 */
"13940000.spi", /* [15] spi_3 */
"13980000.spi", /* [16] spi_4 */
"13500000.dwmmc0", /* [17] dwmmc0 */
"13510000.dwmmc1", /* [18] dwmmc1 */
"13550000.dwmmc2", /* [19] dwmmc2 */
"13600000.usb", /* [20] usb */
"14860000.decon_f", /* [21] decon_f */
"14a50000.abox", /* [22] abox*/
/* index for power-domain */
"pd-g3d", /* [23] pd-g3d */
"pd-mfcmscl", /* [24] pd-mfcmcsl */
"pd-dispaud", /* [25] pd-dispaud */
"pd-isp"; /* [26] pd-isp */
fix-idle-ip = "acpm_dvfs";
fix-idle-ip-index = <96>;
eint-wakeup-mask = <0x0648>;
idle_ip_mask {
sicd: SYS_SICD {
mode-index = <0>;
ref-idle-ip = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>,
<10>, <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>,
<20>, <21>, <22>, <23>, <24>, <26>;
};
};
wakeup-masks {
/*
* wakeup_mask configuration
* SICD SICD_CPD AFTR STOP
* LPD LPA ALPA DSTOP
* SLEEP SLEEP_VTS_ON SLEEP_AUD_ON FAPO
* SICD_AUD_ON
*/
wakeup-mask {
mask = <0x400201C0>, <0x0>, <0x0>, <0x0>,
<0x0>, <0x0>, <0x0>, <0x0>,
<0x500F7E7E>, <0x500F7E7E>, <0x500F7E7E>, <0x0>,
<0x400001C0>;
reg-offset = <0x64c>;
};
wakeup-mask2 {
mask = <0x0>, <0x0>, <0x0>, <0x0>,
<0x0>, <0x0>, <0x0>, <0x0>,
<0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>,
<0x0>;
reg-offset = <0x650>;
};
wakeup-mask3 {
mask = <0x0>, <0x0>, <0x0>, <0x0>,
<0x0>, <0x0>, <0x0>, <0x0>,
<0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>,
<0x0>;
reg-offset = <0x654>;
};
wakeup-mask4 {
mask = <0x0>, <0x0>, <0x0>, <0x0>,
<0x0>, <0x0>, <0x0>, <0x0>,
<0x0>, <0x0>, <0x0>, <0x0>,
<0x0>;
reg-offset = <0x644>;
};
};
};
/* tbase */
tee {
compatible = "samsung,exynos-tee";
interrupts = <0 223 0>;
};
mmc-srpmb {
compatible = "samsung,mmc-srpmb";
interrupts = <0 222 0>;
};
/* Secure log */
seclog {
compatible = "samsung,exynos-seclog";
interrupts = <0 224 0>;
};
iommu-domain_aud {
compatible = "samsung,exynos-iommu-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges;
domain-clients = <&abox>;
};
sysmmu_aud0: sysmmu@14A30000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x0 0x14A30000 0x9000>;
interrupts = <0 129 0>;
qos = <15>;
clock-names = "aclk";
clocks = <&clock GATE_SMMU_ABOX>;
sysmmu,tlb_property =
<(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0) | SYSMMU_BL1) SYSMMU_NOID>;
sysmmu,no-suspend;
#iommu-cells = <0>;
};
abox_gic: abox_gic@0x14AF0000 {
compatible = "samsung,abox_gic";
reg = <0x0 0x14AF1000 0x1000>, <0x0 0x14AF2000 0x1004>;
reg-names = "gicd", "gicc";
interrupts = <0 119 0>;
};
abox: abox@0x14A50000 {
compatible = "samsung,abox";
reg = <0x0 0x14A50000 0x10000>, <0x0 0x14820000 0x10000>, <0x0 0x14B00000 0x28000>;
reg-names = "sfr", "sysreg", "sram";
#address-cells = <2>;
#size-cells = <1>;
ranges;
pinctrl-names = "default", "idle";
pinctrl-0 = <&aud_codec_mclk &aud_codec_bus &aud_fm_bus &aud_spk_bus &aud_loopback_bus>;
pinctrl-1 = <&aud_codec_mclk_idle &aud_codec_bus_idle &aud_fm_bus_idle &aud_spk_bus_idle &aud_loopback_bus_idle>;
samsung,power-domain = <&pd_dispaud>;
ipc_tx_offset = <0x22000>;
ipc_rx_offset = <0x22300>;
ipc_tx_ack_offset = <0x222FC>;
ipc_rx_ack_offset = <0x225FC>;
mailbox_offset = <0x22600>;
abox_gic = <&abox_gic>;
clocks = <&clock PLL_OUT_AUD>,<&clock DFS_ABOX>,
<&clock DOUT_CLK_ABOX_AUDIF>,
<&clock DOUT_CLK_ABOX_UAIF0>,<&clock DOUT_CLK_ABOX_UAIF2>,
<&clock DOUT_CLK_ABOX_UAIF3>,
<&clock GATE_UAIF0>, <&clock GATE_UAIF2>,
<&clock GATE_UAIF3>;
clock-names = "pll", "ca7", "audif",
"bclk0", "bclk2",
"bclk3",
"bclk0_gate", "bclk2_gate",
"bclk3_gate";
iommus = <&sysmmu_aud0>;
pm_qos_int = <533000 400000 0 0 0>;
abox_rdma_0: abox_rdma@0x14A51000 {
compatible = "samsung,abox-rdma";
reg = <0x0 0x14A51000 0x100>;
abox = <&abox>;
id = <0>;
type = "normal";
};
abox_rdma_1: abox_rdma@0x14A51100 {
compatible = "samsung,abox-rdma";
reg = <0x0 0x14A51100 0x100>;
abox = <&abox>;
id = <1>;
type = "normal";
};
abox_rdma_2: abox_rdma@0x14A51200 {
compatible = "samsung,abox-rdma";
reg = <0x0 0x14A51200 0x100>;
abox = <&abox>;
id = <2>;
type = "normal";
};
abox_rdma_3: abox_rdma@0x14A51300 {
compatible = "samsung,abox-rdma";
reg = <0x0 0x14A51300 0x100>;
abox = <&abox>;
id = <3>;
type = "normal";
};
abox_rdma_4: abox_rdma@0x14A51400 {
compatible = "samsung,abox-rdma";
reg = <0x0 0x14A51400 0x100>;
abox = <&abox>;
id = <4>;
type = "call";
};
abox_rdma_5: abox_rdma@0x14A51500 {
compatible = "samsung,abox-rdma";
reg = <0x0 0x14A51500 0x100>;
abox = <&abox>;
id = <5>;
/*type = "compress";*/
type = "normal";
};
abox_rdma_6: abox_rdma@0x14A51600 {
compatible = "samsung,abox-rdma";
reg = <0x0 0x14A51600 0x100>;
abox = <&abox>;
id = <6>;
type = "normal";
};
abox_rdma_7: abox_rdma@0x14A51700 {
compatible = "samsung,abox-rdma";
reg = <0x0 0x14A51700 0x100>;
abox = <&abox>;
id = <7>;
type = "realtime";
};
abox_wdma_0: abox_wdma@0x14A52000 {
compatible = "samsung,abox-wdma";
reg = <0x0 0x14A52000 0x100>;
abox = <&abox>;
id = <0>;
type = "call";
};
abox_wdma_1: abox_wdma@0x14A52100 {
compatible = "samsung,abox-wdma";
reg = <0x0 0x14A52100 0x100>;
abox = <&abox>;
id = <1>;
type = "normal";
};
abox_wdma_2: abox_wdma@0x14A52200 {
compatible = "samsung,abox-wdma";
reg = <0x0 0x14A52200 0x100>;
abox = <&abox>;
id = <2>;
type = "call";
};
abox_wdma_3: abox_wdma@0x14A52300 {
compatible = "samsung,abox-wdma";
reg = <0x0 0x14A52300 0x100>;
abox = <&abox>;
id = <3>;
type = "realtime";
};
abox_wdma_4: abox_wdma@0x14A52400 {
compatible = "samsung,abox-wdma";
reg = <0x0 0x14A52400 0x100>;
abox = <&abox>;
id = <4>;
type = "vi-sensing";
};
abox_debug: abox_debug@0 {
compatible = "samsung,abox-debug";
memory-region = <&abox_rmem>;
};
abox_vss: abox_vss@0 {
compatible = "samsung,abox-vss";
};
};
fimc_is: fimc_is@14440000 {
compatible = "samsung,exynos5-fimc-is";
reg = <0x0 0x14420000 0x10000>, /* CSIS-DMA */
<0x0 0x14430000 0x10000>, /* FIMC-3AA */
<0x0 0x14440000 0x10000>, /* FIMC-ISP */
<0x0 0x14450000 0x10000>, /* MC-SCALER */
<0x0 0x14460000 0x10000>, /* FIMC-VRA (Set A) */
<0x0 0x144D0000 0x10000>; /* FIMC-VRA (Set B) */
interrupts = <0 170 0>, /* 3AA_0 */
<0 171 0>, /* 3AA_1 */
<0 175 0>, /* ISP_0 */
<0 176 0>, /* ISP_1 */
<0 172 0>, /* MCSC */
<0 173 0>, /* VRA_0 */
<0 174 0>; /* VRA_1 */
samsung,power-domain = <&pd_isp>;
clocks = <&clock GATE_IS5P15P0_IS_ISP>,
<&clock GATE_IS5P15P0_IS_MCSC>,
<&clock GATE_IS5P15P0_IS_VRA>,
<&clock GATE_IS5P15P0_IS_CSIS_0>,
<&clock GATE_IS5P15P0_IS_CSIS_1>,
<&clock GATE_IS5P15P0_IS_IS_3AA>,
<&clock GATE_IS5P15P0_IS_TPU>,
<&clock GATE_IS5P15P0_IS_CSIS_DMA>,
<&clock GATE_SMMU_IS>,
<&clock CIS_CLK0>,
<&clock CIS_CLK1>,
<&clock CIS_CLK2>,
<&clock GATE_DFTMUX_TOP_CIS_CLK0>,
<&clock GATE_DFTMUX_TOP_CIS_CLK1>,
<&clock GATE_DFTMUX_TOP_CIS_CLK2>;
clock-names = "GATE_IS_ISP",
"GATE_IS_MCSC",
"GATE_IS_VRA",
"GATE_IS_CSIS_0",
"GATE_IS_CSIS_1",
"GATE_IS_3AA",
"GATE_IS_TPU",
"GATE_IS_CSIS_DMA",
"GATE_SMMU_IS",
"CIS_CLK0",
"CIS_CLK1",
"CIS_CLK2",
"MUX_CIS_CLK0",
"MUX_CIS_CLK1",
"MUX_CIS_CLK2";
status = "ok";
iommus = <&sysmmu_is>;
#cooling-cells = <2>; /* min followed by max */
};
mipi_phy_csis: phy_isp_csis@144C0840 {
compatible = "samsung,mipi-phy-s4";
reg = <0x0 0x144C0840 0x4>; /* SYSREG address for reset */
samsung,pmu-syscon = <&pmu_system_controller>;
isolation = <0x0678 0x067c>; /* PMU address offset */
reset = <0 8>; /* reset bit */
#phy-cells = <1>;
};
fimc_is_sensor0: fimc_is_sensor@14400000 {
/* BACK/CSIS0 */
compatible = "samsung,exynos5-fimc-is-sensor";
reg = <0x0 0x14400000 0x10000>; /* MIPI-CSI0 */
interrupts = <0 168 0>; /* MIPI-CSI0 */
samsung,power-domain = <&pd_isp>;
phys = <&mipi_phy_csis 0>;
phy-names = "csis_dphy";
clocks = <&clock CIS_CLK0>,
<&clock CIS_CLK1>,
<&clock CIS_CLK2>,
<&clock GATE_DFTMUX_TOP_CIS_CLK0>,
<&clock GATE_DFTMUX_TOP_CIS_CLK1>,
<&clock GATE_DFTMUX_TOP_CIS_CLK2>,
<&clock GATE_IS5P15P0_IS_CSIS_0>,
<&clock GATE_IS5P15P0_IS_CSIS_1>,
<&clock GATE_IS5P15P0_IS_CSIS_DMA>;
clock-names = "CIS_CLK0",
"CIS_CLK1",
"CIS_CLK2",
"MUX_CIS_CLK0",
"MUX_CIS_CLK1",
"MUX_CIS_CLK2",
"GATE_IS_CSIS_0",
"GATE_IS_CSIS_1",
"GATE_IS_CSIS_DMA";
iommus = <&sysmmu_is>;
};
fimc_is_sensor1: fimc_is_sensor@14410000 {
/* FRONT/CSIS1 */
compatible = "samsung,exynos5-fimc-is-sensor";
reg = <0x0 0x14410000 0x10000>; /* MIPI-CSI1 */
interrupts = <0 169 0>; /* MIPI-CSI1 */
samsung,power-domain = <&pd_isp>;
phys = <&mipi_phy_csis 1>;
phy-names = "csis_dphy";
clocks = <&clock CIS_CLK0>,
<&clock CIS_CLK1>,
<&clock CIS_CLK2>,
<&clock GATE_DFTMUX_TOP_CIS_CLK0>,
<&clock GATE_DFTMUX_TOP_CIS_CLK1>,
<&clock GATE_DFTMUX_TOP_CIS_CLK2>,
<&clock GATE_IS5P15P0_IS_CSIS_0>,
<&clock GATE_IS5P15P0_IS_CSIS_1>,
<&clock GATE_IS5P15P0_IS_CSIS_DMA>;
clock-names = "CIS_CLK0",
"CIS_CLK1",
"CIS_CLK2",
"MUX_CIS_CLK0",
"MUX_CIS_CLK1",
"MUX_CIS_CLK2",
"GATE_IS_CSIS_0",
"GATE_IS_CSIS_1",
"GATE_IS_CSIS_DMA";
iommus = <&sysmmu_is>;
};
camerapp_gdc: gdc@0x144E0000 {
compatible = "samsung,exynos5-camerapp-gdc";
reg = <0x0 0x144E0000 0x10000>;
interrupts = <0 177 0>;
samsung,power-domain = <&pd_isp>;
clocks = <&clock GATE_IS5P15P0_IS_TPU>,
<&clock GATE_SMMU_IS>;
clock-names = "gate",
"gate2";
iommus = <&sysmmu_is>;
};
/* USB PLL cmu BASE ADDRESS */
cmu_fsys: cmu_fsys@0x13400000 {
compatible = "samsung,exynos7872-cmu_fsys", "syscon";
reg = <0x0 0x13400000 0x2000>;
};
scsc_wifibt: scsc_wifibt@105c0000 {
compatible = "samsung,scsc_wifibt";
/* Mailbox registers */
reg = <0x0 0x105c0000 0x180>, /* R4 */
<0x0 0x105e0000 0x180>; /* M4 */
/* We ignore M4 incoming interrupt */
interrupts = <0 58 4>, <0 21 4>, <0 286 4>;
interrupt-names = "MBOX","ALIVE","WDOG";
/* PMU alive handle */
samsung,syscon-phandle = <&pmu_system_controller>;
/* USB_PLL ownership */
samsung,syscon-cmu_fsys = <&cmu_fsys>;
usbpll,owner="y";
usbpll,udelay=<20>;
status = "okay";
};
};