| #ifndef __EXYNOS8890_CMUSFR_H__ |
| #define __EXYNOS8890_CMUSFR_H__ |
| |
| #include "S5E8890-sfrbase.h" |
| |
| #define HWACG_QCH_ENABLE (0x000F1001) |
| #define HWACG_QCH_DISABLE (0x000F1000) |
| #define HWACG_QSTATE_CLOCK_ENABLE (0x00000003) |
| #define HWACG_QSTATE_ENABLE (0x00000001) |
| #define HWACG_QSTATE_DISABLE (0x00000000) |
| |
| /* Non Spin Lock */ |
| #define NSL (0x80000000) |
| |
| #define APOLLO_PLL_LOCK ((void *)(CMU_APOLLO_BASE + 0x0000 + NSL)) |
| #define APOLLO_PLL_CON0 ((void *)(CMU_APOLLO_BASE + 0x0100 + NSL)) |
| #define APOLLO_PLL_CON1 ((void *)(CMU_APOLLO_BASE + 0x0104 + NSL)) |
| #define APOLLO_PLL_FREQ_DET ((void *)(CMU_APOLLO_BASE + 0x010C + NSL)) |
| #define CLK_CON_MUX_APOLLO_PLL ((void *)(CMU_APOLLO_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_BUS_PLL_APOLLO_USER ((void *)(CMU_APOLLO_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_APOLLO ((void *)(CMU_APOLLO_BASE + 0x0208 + NSL)) |
| #define CLK_CON_DIV_APOLLO ((void *)(CMU_APOLLO_BASE + 0x0400 + NSL)) |
| #define CLK_CON_DIV_ACLK_APOLLO ((void *)(CMU_APOLLO_BASE + 0x0404 + NSL)) |
| #define CLK_CON_DIV_ATCLK_APOLLO ((void *)(CMU_APOLLO_BASE + 0x0408 + NSL)) |
| #define CLK_CON_DIV_PCLK_DBG_APOLLO ((void *)(CMU_APOLLO_BASE + 0x040C + NSL)) |
| #define CLK_CON_DIV_PCLK_APOLLO ((void *)(CMU_APOLLO_BASE + 0x0410 + NSL)) |
| #define CLK_CON_DIV_CNTCLK_APOLLO ((void *)(CMU_APOLLO_BASE + 0x0414 + NSL)) |
| #define CLK_CON_DIV_APOLLO_RUN_MONITOR ((void *)(CMU_APOLLO_BASE + 0x0418 + NSL)) |
| #define CLK_CON_DIV_SCLK_PROMISE_APOLLO ((void *)(CMU_APOLLO_BASE + 0x041C + NSL)) |
| #define CLK_CON_DIV_APOLLO_PLL ((void *)(CMU_APOLLO_BASE + 0x0420 + NSL)) |
| #define CLK_STAT_MUX_APOLLO_PLL ((void *)(CMU_APOLLO_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_BUS_PLL_APOLLO_USER ((void *)(CMU_APOLLO_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_APOLLO ((void *)(CMU_APOLLO_BASE + 0x0608 + NSL)) |
| #define CLK_ENABLE_ACLK_APOLLO ((void *)(CMU_APOLLO_BASE + 0x0800)) |
| #define CLK_ENABLE_ATCLK_APOLLO ((void *)(CMU_APOLLO_BASE + 0x0804)) |
| #define CLK_ENABLE_PCLK_DBG_APOLLO ((void *)(CMU_APOLLO_BASE + 0x0900)) |
| #define CLK_ENABLE_PCLK_APOLLO ((void *)(CMU_APOLLO_BASE + 0x0904)) |
| #define CLK_ENABLE_PCLK_HPM_APOLLO ((void *)(CMU_APOLLO_BASE + 0x0908)) |
| #define CLK_ENABLE_SCLK_APOLLO ((void *)(CMU_APOLLO_BASE + 0x0A00)) |
| #define CLK_ENABLE_SCLK_PROMISE_APOLLO ((void *)(CMU_APOLLO_BASE + 0x0A04)) |
| #define CLKOUT_CMU_APOLLO ((void *)(CMU_APOLLO_BASE + 0x0C00)) |
| #define CLKOUT_CMU_APOLLO_DIV_STAT ((void *)(CMU_APOLLO_BASE + 0x0C04)) |
| #define CLK_ENABLE_PDN_APOLLO ((void *)(CMU_APOLLO_BASE + 0x0D00)) |
| #define APOLLO_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_APOLLO_BASE + 0x0D04)) |
| #define CMU_APOLLO_SPARE0 ((void *)(CMU_APOLLO_BASE + 0x0D08)) |
| #define CMU_APOLLO_SPARE1 ((void *)(CMU_APOLLO_BASE + 0x0D0C)) |
| #define ARMCLK_STOPCTRL_APOLLO ((void *)(CMU_APOLLO_BASE + 0x1000)) |
| #define PWR_CTRL_APOLLO ((void *)(CMU_APOLLO_BASE + 0x1020)) |
| #define PWR_CTRL2_APOLLO ((void *)(CMU_APOLLO_BASE + 0x1024)) |
| #define PWR_CTRL3_APOLLO ((void *)(CMU_APOLLO_BASE + 0x1028)) |
| #define PWR_CTRL4_APOLLO ((void *)(CMU_APOLLO_BASE + 0x102C)) |
| #define INTR_SPREAD_ENABLE_APOLLO ((void *)(CMU_APOLLO_BASE + 0x1080)) |
| #define INTR_SPREAD_USE_STANDBYWFI_APOLLO ((void *)(CMU_APOLLO_BASE + 0x1084)) |
| #define INTR_SPREAD_BLOCKING_DURATION_APOLLO ((void *)(CMU_APOLLO_BASE + 0x1088)) |
| #define CLK_CON_MUX_AUD_PLL_USER ((void *)(CMU_AUD_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_SCLK_I2S ((void *)(CMU_AUD_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_SCLK_PCM ((void *)(CMU_AUD_BASE + 0x0208 + NSL)) |
| #define CLK_CON_MUX_CP2AP_AUD_CLK_USER ((void *)(CMU_AUD_BASE + 0x020C + NSL)) |
| #define CLK_CON_MUX_ACLK_CA5 ((void *)(CMU_AUD_BASE + 0x0210 + NSL)) |
| #define CLK_CON_MUX_CDCLK_AUD ((void *)(CMU_AUD_BASE + 0x0214 + NSL)) |
| #define CLK_CON_DIV_AUD_CA5 ((void *)(CMU_AUD_BASE + 0x0400 + NSL)) |
| #define CLK_CON_DIV_ACLK_AUD ((void *)(CMU_AUD_BASE + 0x0404 + NSL)) |
| #define CLK_CON_DIV_PCLK_DBG ((void *)(CMU_AUD_BASE + 0x0408 + NSL)) |
| #define CLK_CON_DIV_ATCLK_AUD ((void *)(CMU_AUD_BASE + 0x040C + NSL)) |
| #define CLK_CON_DIV_AUD_CDCLK ((void *)(CMU_AUD_BASE + 0x0410 + NSL)) |
| #define CLK_CON_DIV_SCLK_I2S ((void *)(CMU_AUD_BASE + 0x0414 + NSL)) |
| #define CLK_CON_DIV_SCLK_PCM ((void *)(CMU_AUD_BASE + 0x0418 + NSL)) |
| #define CLK_CON_DIV_SCLK_SLIMBUS ((void *)(CMU_AUD_BASE + 0x041C + NSL)) |
| #define CLK_CON_DIV_SCLK_CP_I2S ((void *)(CMU_AUD_BASE + 0x0424 + NSL)) |
| #define CLK_CON_DIV_SCLK_ASRC ((void *)(CMU_AUD_BASE + 0x0428 + NSL)) |
| #define CLK_CON_DIV_CP_CA5 ((void *)(CMU_AUD_BASE + 0x042C + NSL)) |
| #define CLK_CON_DIV_CP_CDCLK ((void *)(CMU_AUD_BASE + 0x0430 + NSL)) |
| #define CLK_STAT_MUX_AUD_PLL_USER ((void *)(CMU_AUD_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_CP2AP_AUD_CLK_USER ((void *)(CMU_AUD_BASE + 0x060C + NSL)) |
| #define CLK_STAT_MUX_ACLK_CA5 ((void *)(CMU_AUD_BASE + 0x0610 + NSL)) |
| #define CLK_STAT_MUX_CDCLK_AUD ((void *)(CMU_AUD_BASE + 0x0614 + NSL)) |
| #define CLK_ENABLE_SCLK_CA5 ((void *)(CMU_AUD_BASE + 0x0800)) |
| #define CLK_ENABLE_ACLK_AUD ((void *)(CMU_AUD_BASE + 0x0804)) |
| #define CLK_ENABLE_PCLK_AUD ((void *)(CMU_AUD_BASE + 0x0808)) |
| #define CLK_ENABLE_ACLK_ATCLK_AUD ((void *)(CMU_AUD_BASE + 0x080C)) |
| #define CLK_ENABLE_SCLK_I2S ((void *)(CMU_AUD_BASE + 0x0810)) |
| #define CLK_ENABLE_SCLK_PCM ((void *)(CMU_AUD_BASE + 0x0814)) |
| #define CLK_ENABLE_SCLK_SLIMBUS ((void *)(CMU_AUD_BASE + 0x0818)) |
| #define CLK_ENABLE_SCLK_CP_I2S ((void *)(CMU_AUD_BASE + 0x081C)) |
| #define CLK_ENABLE_SCLK_ASRC ((void *)(CMU_AUD_BASE + 0x0820)) |
| #define CLK_ENABLE_SCLK_SLIMBUS_CLKIN ((void *)(CMU_AUD_BASE + 0x0824)) |
| #define CLK_ENABLE_SCLK_I2S_BCLK ((void *)(CMU_AUD_BASE + 0x0828)) |
| #define CLKOUT_CMU_AUD ((void *)(CMU_AUD_BASE + 0x0D00)) |
| #define CLKOUT_CMU_AUD_DIV_STAT ((void *)(CMU_AUD_BASE + 0x0D04)) |
| #define CMU_AUD_SPARE0 ((void *)(CMU_AUD_BASE + 0x0D08)) |
| #define CMU_AUD_SPARE1 ((void *)(CMU_AUD_BASE + 0x0D0C)) |
| #define CLK_ENABLE_PDN_AUD ((void *)(CMU_AUD_BASE + 0x0E00)) |
| #define AUD_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_AUD_BASE + 0x0F28)) |
| #define CLK_CON_MUX_ACLK_BUS0_528_USER ((void *)(CMU_BUS0_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_ACLK_BUS0_200_USER ((void *)(CMU_BUS0_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_PCLK_BUS0_132_USER ((void *)(CMU_BUS0_BASE + 0x0208 + NSL)) |
| #define CLK_STAT_MUX_ACLK_BUS0_528_USER ((void *)(CMU_BUS0_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_ACLK_BUS0_200_USER ((void *)(CMU_BUS0_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_PCLK_BUS0_132_USER ((void *)(CMU_BUS0_BASE + 0x0608 + NSL)) |
| #define CLK_ENABLE_ACLK_BUS0_528_BUS0 ((void *)(CMU_BUS0_BASE + 0x0800)) |
| #define CLK_ENABLE_ACLK_BUS0_200_BUS0 ((void *)(CMU_BUS0_BASE + 0x0804)) |
| #define CLK_ENABLE_PCLK_BUS0_132_BUS0 ((void *)(CMU_BUS0_BASE + 0x0900)) |
| #define CG_CTRL_VAL_ACLK_BUS0_528_BUS0 ((void *)(CMU_BUS0_BASE + 0x0800)) |
| #define CG_CTRL_VAL_ACLK_BUS0_200_BUS0 ((void *)(CMU_BUS0_BASE + 0x0804)) |
| #define CG_CTRL_VAL_PCLK_BUS0_132_BUS0 ((void *)(CMU_BUS0_BASE + 0x0900)) |
| #define CLKOUT_CMU_BUS0 ((void *)(CMU_BUS0_BASE + 0x0D00)) |
| #define CLKOUT_CMU_BUS0_DIV_STAT ((void *)(CMU_BUS0_BASE + 0x0D04)) |
| #define CMU_BUS0_SPARE0 ((void *)(CMU_BUS0_BASE + 0x0D08)) |
| #define CMU_BUS0_SPARE1 ((void *)(CMU_BUS0_BASE + 0x0D0C)) |
| #define CLK_ENABLE_PDN_BUS0 ((void *)(CMU_BUS0_BASE + 0x0E00)) |
| #define BUS0_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_BUS0_BASE + 0x0F28)) |
| #define CG_CTRL_MAN_ACLK_BUS0_528 ((void *)(CMU_BUS0_BASE + 0x1800)) |
| #define CG_CTRL_MAN_ACLK_BUS0_200 ((void *)(CMU_BUS0_BASE + 0x1804)) |
| #define CG_CTRL_MAN_PCLK_BUS0_132 ((void *)(CMU_BUS0_BASE + 0x1900)) |
| #define CG_CTRL_STAT_ACLK_BUS0_528_0 ((void *)(CMU_BUS0_BASE + 0x1C00)) |
| #define CG_CTRL_STAT_ACLK_BUS0_528_1 ((void *)(CMU_BUS0_BASE + 0x1C04)) |
| #define CG_CTRL_STAT_ACLK_BUS0_200 ((void *)(CMU_BUS0_BASE + 0x1C08)) |
| #define CG_CTRL_STAT_PCLK_BUS0_132_0 ((void *)(CMU_BUS0_BASE + 0x1D00)) |
| #define CG_CTRL_STAT_PCLK_BUS0_132_1 ((void *)(CMU_BUS0_BASE + 0x1D04)) |
| #define CG_CTRL_STAT_PCLK_BUS0_132_2 ((void *)(CMU_BUS0_BASE + 0x1D08)) |
| #define QCH_CTRL_TREX_D_BUS0 ((void *)(CMU_BUS0_BASE + 0x2000)) |
| #define QCH_CTRL_CAM0_D ((void *)(CMU_BUS0_BASE + 0x2004)) |
| #define QCH_CTRL_CAM1_D ((void *)(CMU_BUS0_BASE + 0x2008)) |
| #define QCH_CTRL_DISP00_D ((void *)(CMU_BUS0_BASE + 0x200C)) |
| #define QCH_CTRL_DISP01_D ((void *)(CMU_BUS0_BASE + 0x2010)) |
| #define QCH_CTRL_DISP10_D ((void *)(CMU_BUS0_BASE + 0x2014)) |
| #define QCH_CTRL_DISP11_D ((void *)(CMU_BUS0_BASE + 0x201C)) |
| #define QCH_CTRL_ISP0_D ((void *)(CMU_BUS0_BASE + 0x2020)) |
| #define QCH_CTRL_FSYS1_D ((void *)(CMU_BUS0_BASE + 0x2024)) |
| #define QCH_CTRL_TREX_P_BUS0 ((void *)(CMU_BUS0_BASE + 0x2100)) |
| #define QCH_CTRL_ISP0_SFR ((void *)(CMU_BUS0_BASE + 0x2104)) |
| #define QCH_CTRL_ISP1_SFR ((void *)(CMU_BUS0_BASE + 0x2108)) |
| #define QCH_CTRL_DISP0_SFR ((void *)(CMU_BUS0_BASE + 0x210C)) |
| #define QCH_CTRL_DISP1_SFR ((void *)(CMU_BUS0_BASE + 0x2110)) |
| #define QCH_CTRL_PERIS_SFR ((void *)(CMU_BUS0_BASE + 0x2114)) |
| #define QCH_CTRL_PERIC0_SFR ((void *)(CMU_BUS0_BASE + 0x2118)) |
| #define QCH_CTRL_PERIC1_SFR ((void *)(CMU_BUS0_BASE + 0x211C)) |
| #define QCH_CTRL_FSYS1_SFR ((void *)(CMU_BUS0_BASE + 0x2120)) |
| #define QCH_CTRL_SYSREG_BUS0 ((void *)(CMU_BUS0_BASE + 0x2124)) |
| #define QCH_CTRL_PMU_BUS0 ((void *)(CMU_BUS0_BASE + 0x2128)) |
| #define QCH_CTRL_CMU_BUS0 ((void *)(CMU_BUS0_BASE + 0x212C)) |
| #define CLK_CON_MUX_ACLK_BUS1_528_USER ((void *)(CMU_BUS1_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_PCLK_BUS1_132_USER ((void *)(CMU_BUS1_BASE + 0x0204 + NSL)) |
| #define CLK_STAT_MUX_ACLK_BUS1_528_USER ((void *)(CMU_BUS1_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_PCLK_BUS1_132_USER ((void *)(CMU_BUS1_BASE + 0x0604 + NSL)) |
| #define CLK_ENABLE_ACLK_BUS1_528_BUS1 ((void *)(CMU_BUS1_BASE + 0x0800 + NSL)) |
| #define CLK_ENABLE_PCLK_BUS1_132_BUS1 ((void *)(CMU_BUS1_BASE + 0x0900 + NSL)) |
| #define CG_CTRL_VAL_ACLK_BUS1_528_BUS1 ((void *)(CMU_BUS1_BASE + 0x0800)) |
| #define CG_CTRL_VAL_PCLK_BUS1_132_BUS1 ((void *)(CMU_BUS1_BASE + 0x0900)) |
| #define CLKOUT_CMU_BUS1 ((void *)(CMU_BUS1_BASE + 0x0D00)) |
| #define CLKOUT_CMU_BUS1_DIV_STAT ((void *)(CMU_BUS1_BASE + 0x0D04)) |
| #define CMU_BUS1_SPARE0 ((void *)(CMU_BUS1_BASE + 0x0D08)) |
| #define CMU_BUS1_SPARE1 ((void *)(CMU_BUS1_BASE + 0x0D0C)) |
| #define CLK_ENABLE_PDN_BUS1 ((void *)(CMU_BUS1_BASE + 0x0E00)) |
| #define BUS1_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_BUS1_BASE + 0x0F28)) |
| #define CG_CTRL_MAN_ACLK_BUS1_528 ((void *)(CMU_BUS1_BASE + 0x1800)) |
| #define CG_CTRL_MAN_PCLK_BUS1_132 ((void *)(CMU_BUS1_BASE + 0x1900)) |
| #define CG_CTRL_STAT_ACLK_BUS1_528 ((void *)(CMU_BUS1_BASE + 0x1C00)) |
| #define CG_CTRL_STAT_PCLK_BUS1_132_0 ((void *)(CMU_BUS1_BASE + 0x1D00)) |
| #define CG_CTRL_STAT_PCLK_BUS1_132_1 ((void *)(CMU_BUS1_BASE + 0x1D04)) |
| #define QCH_CTRL_TREX_D_BUS1 ((void *)(CMU_BUS1_BASE + 0x2000)) |
| #define QCH_CTRL_FSYS0_D ((void *)(CMU_BUS1_BASE + 0x2004)) |
| #define QCH_CTRL_MFC0_D ((void *)(CMU_BUS1_BASE + 0x2008)) |
| #define QCH_CTRL_MFC1_D ((void *)(CMU_BUS1_BASE + 0x200C)) |
| #define QCH_CTRL_MSCL0_D ((void *)(CMU_BUS1_BASE + 0x2010)) |
| #define QCH_CTRL_MSCL1_D ((void *)(CMU_BUS1_BASE + 0x2014)) |
| #define QCH_CTRL_TREX_P_BUS1 ((void *)(CMU_BUS1_BASE + 0x2018)) |
| #define QCH_CTRL_FSYS0_SFR ((void *)(CMU_BUS1_BASE + 0x201C)) |
| #define QCH_CTRL_MFC_SFR ((void *)(CMU_BUS1_BASE + 0x2020)) |
| #define QCH_CTRL_MSCL_SFR ((void *)(CMU_BUS1_BASE + 0x2024)) |
| #define QCH_CTRL_PMU_BUS1 ((void *)(CMU_BUS1_BASE + 0x2028)) |
| #define QCH_CTRL_SYSREG_BUS1 ((void *)(CMU_BUS1_BASE + 0x202C)) |
| #define QCH_CTRL_CMU_BUS1 ((void *)(CMU_BUS1_BASE + 0x2030)) |
| #define CLK_CON_MUX_ACLK_CAM0_CSIS0_414_USER ((void *)(CMU_CAM0_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM0_CSIS1_168_USER ((void *)(CMU_CAM0_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM0_CSIS2_234_USER ((void *)(CMU_CAM0_BASE + 0x0208 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM0_CSIS3_132_USER ((void *)(CMU_CAM0_BASE + 0x020C + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM0_3AA0_414_USER ((void *)(CMU_CAM0_BASE + 0x0214 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM0_3AA1_414_USER ((void *)(CMU_CAM0_BASE + 0x0218 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM0_TREX_528_USER ((void *)(CMU_CAM0_BASE + 0x021C + NSL)) |
| #define CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS0_USER ((void *)(CMU_CAM0_BASE + 0x0220 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_RXBYTECLKHS1_CSIS0_USER ((void *)(CMU_CAM0_BASE + 0x0224 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_RXBYTECLKHS2_CSIS0_USER ((void *)(CMU_CAM0_BASE + 0x0228 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_RXBYTECLKHS3_CSIS0_USER ((void *)(CMU_CAM0_BASE + 0x022C + NSL)) |
| #define CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS1_USER ((void *)(CMU_CAM0_BASE + 0x0230 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_RXBYTECLKHS1_CSIS1_USER ((void *)(CMU_CAM0_BASE + 0x0234 + NSL)) |
| #define CLK_CON_DIV_PCLK_CAM0_CSIS0_207 ((void *)(CMU_CAM0_BASE + 0x0400 + NSL)) |
| #define CLK_CON_DIV_PCLK_CAM0_3AA0_207 ((void *)(CMU_CAM0_BASE + 0x040C + NSL)) |
| #define CLK_CON_DIV_PCLK_CAM0_3AA1_207 ((void *)(CMU_CAM0_BASE + 0x0410 + NSL)) |
| #define CLK_CON_DIV_PCLK_CAM0_TREX_264 ((void *)(CMU_CAM0_BASE + 0x0414 + NSL)) |
| #define CLK_CON_DIV_PCLK_CAM0_TREX_132 ((void *)(CMU_CAM0_BASE + 0x0418 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM0_CSIS0_414_USER ((void *)(CMU_CAM0_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM0_CSIS1_168_USER ((void *)(CMU_CAM0_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM0_CSIS2_234_USER ((void *)(CMU_CAM0_BASE + 0x0608 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM0_CSIS3_132_USER ((void *)(CMU_CAM0_BASE + 0x060C + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM0_3AA0_414_USER ((void *)(CMU_CAM0_BASE + 0x0614 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM0_3AA1_414_USER ((void *)(CMU_CAM0_BASE + 0x0618 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM0_TREX_528_USER ((void *)(CMU_CAM0_BASE + 0x061C + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_RXBYTECLKHS0_CSIS0_USER ((void *)(CMU_CAM0_BASE + 0x0620 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_RXBYTECLKHS1_CSIS0_USER ((void *)(CMU_CAM0_BASE + 0x0624 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_RXBYTECLKHS2_CSIS0_USER ((void *)(CMU_CAM0_BASE + 0x0628 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_RXBYTECLKHS3_CSIS0_USER ((void *)(CMU_CAM0_BASE + 0x062C + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_RXBYTECLKHS0_CSIS1_USER ((void *)(CMU_CAM0_BASE + 0x0630 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_RXBYTECLKHS1_CSIS1_USER ((void *)(CMU_CAM0_BASE + 0x0634 + NSL)) |
| #define CLK_ENABLE_ACLK_CAM0_CSIS0_414 ((void *)(CMU_CAM0_BASE + 0x0800)) |
| #define CLK_ENABLE_PCLK_CAM0_CSIS0_207 ((void *)(CMU_CAM0_BASE + 0x0804)) |
| #define CLK_ENABLE_ACLK_CAM0_CSIS1_168_CAM0 ((void *)(CMU_CAM0_BASE + 0x080C)) |
| #define CLK_ENABLE_ACLK_CAM0_CSIS2_234_CAM0 ((void *)(CMU_CAM0_BASE + 0x0818)) |
| #define CLK_ENABLE_ACLK_CAM0_CSIS3_132_CAM0 ((void *)(CMU_CAM0_BASE + 0x081C)) |
| #define CLK_ENABLE_ACLK_CAM0_3AA0_414_CAM0 ((void *)(CMU_CAM0_BASE + 0x0828)) |
| #define CLK_ENABLE_PCLK_CAM0_3AA0_207 ((void *)(CMU_CAM0_BASE + 0x082C)) |
| #define CLK_ENABLE_ACLK_CAM0_3AA1_414_CAM0 ((void *)(CMU_CAM0_BASE + 0x0830)) |
| #define CLK_ENABLE_PCLK_CAM0_3AA1_207 ((void *)(CMU_CAM0_BASE + 0x0834)) |
| #define CLK_ENABLE_ACLK_CAM0_TREX_528_CAM0 ((void *)(CMU_CAM0_BASE + 0x0838)) |
| #define CLK_ENABLE_PCLK_CAM0_TREX_264 ((void *)(CMU_CAM0_BASE + 0x083C)) |
| #define CLK_ENABLE_PCLK_CAM0_TREX_132 ((void *)(CMU_CAM0_BASE + 0x0840)) |
| #define CLK_ENABLE_SCLK_PROMISE_CAM0 ((void *)(CMU_CAM0_BASE + 0x0844)) |
| #define CLK_ENABLE_PHYCLK_HS0_CSIS0_RX_BYTE ((void *)(CMU_CAM0_BASE + 0x0848)) |
| #define CLK_ENABLE_PHYCLK_HS1_CSIS0_RX_BYTE ((void *)(CMU_CAM0_BASE + 0x084C)) |
| #define CLK_ENABLE_PHYCLK_HS2_CSIS0_RX_BYTE ((void *)(CMU_CAM0_BASE + 0x0850)) |
| #define CLK_ENABLE_PHYCLK_HS3_CSIS0_RX_BYTE ((void *)(CMU_CAM0_BASE + 0x0854)) |
| #define CLK_ENABLE_PHYCLK_HS0_CSIS1_RX_BYTE ((void *)(CMU_CAM0_BASE + 0x0858)) |
| #define CLK_ENABLE_PHYCLK_HS1_CSIS1_RX_BYTE ((void *)(CMU_CAM0_BASE + 0x085C)) |
| #define CLK_ENABLE_PCLK_HPM_APBIF_CAM0 ((void *)(CMU_CAM0_BASE + 0x0860)) |
| #define CLKOUT_CMU_CAM0 ((void *)(CMU_CAM0_BASE + 0x0D00)) |
| #define CLKOUT_CMU_CAM0_DIV_STAT ((void *)(CMU_CAM0_BASE + 0x0D04)) |
| #define CMU_CAM0_SPARE0 ((void *)(CMU_CAM0_BASE + 0x0D08)) |
| #define CMU_CAM0_SPARE1 ((void *)(CMU_CAM0_BASE + 0x0D0C)) |
| #define CLK_ENABLE_PDN_CAM0 ((void *)(CMU_CAM0_BASE + 0x0E00)) |
| #define CAM0_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_CAM0_BASE + 0x0F28)) |
| #define CLK_ENABLE_ACLK_CAM0_CSIS0_414_LOCAL ((void *)(CMU_CAM0_LOCAL_BASE + 0x0800)) |
| #define CLK_ENABLE_PCLK_CAM0_CSIS0_207_LOCAL ((void *)(CMU_CAM0_LOCAL_BASE + 0x0804)) |
| #define CLK_ENABLE_ACLK_CAM0_CSIS1_168_LOCAL ((void *)(CMU_CAM0_LOCAL_BASE + 0x080C)) |
| #define CLK_ENABLE_ACLK_CAM0_CSIS2_234_LOCAL ((void *)(CMU_CAM0_LOCAL_BASE + 0x0818)) |
| #define CLK_ENABLE_ACLK_CAM0_CSIS3_132_LOCAL ((void *)(CMU_CAM0_LOCAL_BASE + 0x081C)) |
| #define CLK_ENABLE_ACLK_CAM0_3AA0_414_LOCAL ((void *)(CMU_CAM0_LOCAL_BASE + 0x0828)) |
| #define CLK_ENABLE_PCLK_CAM0_3AA0_207_LOCAL ((void *)(CMU_CAM0_LOCAL_BASE + 0x082C)) |
| #define CLK_ENABLE_ACLK_CAM0_3AA1_414_LOCAL ((void *)(CMU_CAM0_LOCAL_BASE + 0x0830)) |
| #define CLK_ENABLE_PCLK_CAM0_3AA1_207_LOCAL ((void *)(CMU_CAM0_LOCAL_BASE + 0x0834)) |
| #define CLK_ENABLE_PCLK_CAM0_TREX_264_LOCAL ((void *)(CMU_CAM0_LOCAL_BASE + 0x083C)) |
| #define CLK_CON_MUX_ACLK_CAM1_ARM_672_USER ((void *)(CMU_CAM1_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM1_TREX_VRA_528_USER ((void *)(CMU_CAM1_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM1_TREX_B_528_USER ((void *)(CMU_CAM1_BASE + 0x0208 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM1_BUS_264_USER ((void *)(CMU_CAM1_BASE + 0x020C + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM1_PERI_84_USER ((void *)(CMU_CAM1_BASE + 0x0210 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM1_CSIS2_414_USER ((void *)(CMU_CAM1_BASE + 0x0214 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM1_CSIS3_132_USER ((void *)(CMU_CAM1_BASE + 0x0218 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM1_SCL_566_USER ((void *)(CMU_CAM1_BASE + 0x021C + NSL)) |
| #define CLK_CON_MUX_SCLK_CAM1_ISP_SPI0_USER ((void *)(CMU_CAM1_BASE + 0x0220 + NSL)) |
| #define CLK_CON_MUX_SCLK_CAM1_ISP_SPI1_USER ((void *)(CMU_CAM1_BASE + 0x0224 + NSL)) |
| #define CLK_CON_MUX_SCLK_CAM1_ISP_UART_USER ((void *)(CMU_CAM1_BASE + 0x0228 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS2_USER ((void *)(CMU_CAM1_BASE + 0x022C + NSL)) |
| #define CLK_CON_MUX_PHYCLK_RXBYTECLKHS1_CSIS2_USER ((void *)(CMU_CAM1_BASE + 0x0230 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_RXBYTECLKHS2_CSIS2_USER ((void *)(CMU_CAM1_BASE + 0x0234 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_RXBYTECLKHS3_CSIS2_USER ((void *)(CMU_CAM1_BASE + 0x0238 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS3_USER ((void *)(CMU_CAM1_BASE + 0x023C + NSL)) |
| #define CLK_CON_DIV_PCLK_CAM1_ARM_168 ((void *)(CMU_CAM1_BASE + 0x0400 + NSL)) |
| #define CLK_CON_DIV_PCLK_CAM1_TREX_VRA_264 ((void *)(CMU_CAM1_BASE + 0x0408 + NSL)) |
| #define CLK_CON_DIV_PCLK_CAM1_BUS_132 ((void *)(CMU_CAM1_BASE + 0x040C + NSL)) |
| #define CLK_CON_DIV_PCLK_CAM1_SCL_283 ((void *)(CMU_CAM1_BASE + 0x0418 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM1_ARM_672_USER ((void *)(CMU_CAM1_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM1_TREX_VRA_528_USER ((void *)(CMU_CAM1_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM1_TREX_B_528_USER ((void *)(CMU_CAM1_BASE + 0x0608 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM1_BUS_264_USER ((void *)(CMU_CAM1_BASE + 0x060C + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM1_PERI_84_USER ((void *)(CMU_CAM1_BASE + 0x0610 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM1_CSIS2_414_USER ((void *)(CMU_CAM1_BASE + 0x0614 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM1_CSIS3_132_USER ((void *)(CMU_CAM1_BASE + 0x0618 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM1_SCL_566_USER ((void *)(CMU_CAM1_BASE + 0x061C + NSL)) |
| #define CLK_STAT_MUX_SCLK_CAM1_ISP_SPI0_USER ((void *)(CMU_CAM1_BASE + 0x0620 + NSL)) |
| #define CLK_STAT_MUX_SCLK_CAM1_ISP_SPI1_USER ((void *)(CMU_CAM1_BASE + 0x0624 + NSL)) |
| #define CLK_STAT_MUX_SCLK_CAM1_ISP_UART_USER ((void *)(CMU_CAM1_BASE + 0x0628 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_RXBYTECLKHS0_CSIS2_USER ((void *)(CMU_CAM1_BASE + 0x062C + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_RXBYTECLKHS1_CSIS2_USER ((void *)(CMU_CAM1_BASE + 0x0630 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_RXBYTECLKHS2_CSIS2_USER ((void *)(CMU_CAM1_BASE + 0x0634 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_RXBYTECLKHS3_CSIS2_USER ((void *)(CMU_CAM1_BASE + 0x0638 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_RXBYTECLKHS0_CSIS3_USER ((void *)(CMU_CAM1_BASE + 0x063C + NSL)) |
| #define CLK_ENABLE_ACLK_CAM1_ARM_672_CAM1 ((void *)(CMU_CAM1_BASE + 0x0800)) |
| #define CLK_ENABLE_PCLK_CAM1_ARM_168 ((void *)(CMU_CAM1_BASE + 0x0804)) |
| #define CLK_ENABLE_ACLK_CAM1_TREX_VRA_528_CAM1 ((void *)(CMU_CAM1_BASE + 0x0808)) |
| #define CLK_ENABLE_PCLK_CAM1_TREX_VRA_264 ((void *)(CMU_CAM1_BASE + 0x080C)) |
| #define CLK_ENABLE_ACLK_CAM1_TREX_B_528_CAM1 ((void *)(CMU_CAM1_BASE + 0x0810)) |
| #define CLK_ENABLE_ACLK_CAM1_BUS_264_CAM1 ((void *)(CMU_CAM1_BASE + 0x0814)) |
| #define CLK_ENABLE_PCLK_CAM1_BUS_132 ((void *)(CMU_CAM1_BASE + 0x0818)) |
| #define CLK_ENABLE_PCLK_CAM1_PERI_84 ((void *)(CMU_CAM1_BASE + 0x081C)) |
| #define CLK_ENABLE_ACLK_CAM1_CSIS2_414_CAM1 ((void *)(CMU_CAM1_BASE + 0x0820)) |
| #define CLK_ENABLE_ACLK_CAM1_CSIS3_132_CAM1 ((void *)(CMU_CAM1_BASE + 0x0828)) |
| #define CLK_ENABLE_ACLK_CAM1_SCL_566_CAM1 ((void *)(CMU_CAM1_BASE + 0x0830)) |
| #define CLK_ENABLE_PCLK_CAM1_SCL_283 ((void *)(CMU_CAM1_BASE + 0x083C)) |
| #define CLK_ENABLE_PCLK_CAM1_MCS_132 ((void *)(CMU_CAM1_BASE + 0x083C)) |
| #define CLK_ENABLE_SCLK_CAM1_ISP_SPI0_CAM1 ((void *)(CMU_CAM1_BASE + 0x0840)) |
| #define CLK_ENABLE_SCLK_CAM1_ISP_SPI1_CAM1 ((void *)(CMU_CAM1_BASE + 0x0844)) |
| #define CLK_ENABLE_SCLK_CAM1_ISP_UART_CAM1 ((void *)(CMU_CAM1_BASE + 0x0848)) |
| #define CLK_ENABLE_SCLK_ISP_PERI_IS_B ((void *)(CMU_CAM1_BASE + 0x084C)) |
| #define CLK_ENABLE_PHYCLK_HS0_CSIS2_RX_BYTE ((void *)(CMU_CAM1_BASE + 0x0850)) |
| #define CLK_ENABLE_PHYCLK_HS1_CSIS2_RX_BYTE ((void *)(CMU_CAM1_BASE + 0x0854)) |
| #define CLK_ENABLE_PHYCLK_HS2_CSIS2_RX_BYTE ((void *)(CMU_CAM1_BASE + 0x0858)) |
| #define CLK_ENABLE_PHYCLK_HS3_CSIS2_RX_BYTE ((void *)(CMU_CAM1_BASE + 0x085C)) |
| #define CLK_ENABLE_PHYCLK_HS0_CSIS3_RX_BYTE ((void *)(CMU_CAM1_BASE + 0x0860)) |
| #define CLKOUT_CMU_CAM1 ((void *)(CMU_CAM1_BASE + 0x0D00)) |
| #define CLKOUT_CMU_CAM1_DIV_STAT ((void *)(CMU_CAM1_BASE + 0x0D04)) |
| #define CMU_CAM1_SPARE0 ((void *)(CMU_CAM1_BASE + 0x0D08)) |
| #define CMU_CAM1_SPARE1 ((void *)(CMU_CAM1_BASE + 0x0D0C)) |
| #define CLK_ENABLE_PDN_CAM1 ((void *)(CMU_CAM1_BASE + 0x0E00)) |
| #define CAM1_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_CAM1_BASE + 0x0F28)) |
| #define CLK_ENABLE_ACLK_CAM1_TREX_VRA_528_LOCAL ((void *)(CMU_CAM1_LOCAL_BASE + 0x0808)) |
| #define CLK_ENABLE_PCLK_CAM1_TREX_VRA_264_LOCAL ((void *)(CMU_CAM1_LOCAL_BASE + 0x080C)) |
| #define CLK_ENABLE_ACLK_CAM1_BUS_264_LOCAL ((void *)(CMU_CAM1_LOCAL_BASE + 0x0814)) |
| #define CLK_ENABLE_PCLK_CAM1_PERI_84_LOCAL ((void *)(CMU_CAM1_LOCAL_BASE + 0x081C)) |
| #define CLK_ENABLE_ACLK_CAM1_CSIS2_414_LOCAL ((void *)(CMU_CAM1_LOCAL_BASE + 0x0820)) |
| #define CLK_ENABLE_ACLK_CAM1_CSIS3_132_LOCAL ((void *)(CMU_CAM1_LOCAL_BASE + 0x0828)) |
| #define CLK_ENABLE_ACLK_CAM1_SCL_566_LOCAL ((void *)(CMU_CAM1_LOCAL_BASE + 0x0830)) |
| #define CLK_CON_MUX_ACLK_CCORE_800_USER ((void *)(CMU_CCORE_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_ACLK_CCORE_264_USER ((void *)(CMU_CCORE_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_ACLK_CCORE_G3D_800_USER ((void *)(CMU_CCORE_BASE + 0x0208 + NSL)) |
| #define CLK_CON_MUX_ACLK_CCORE_528_USER ((void *)(CMU_CCORE_BASE + 0x020C + NSL)) |
| #define CLK_CON_MUX_ACLK_CCORE_132_USER ((void *)(CMU_CCORE_BASE + 0x0210 + NSL)) |
| #define CLK_CON_MUX_PCLK_CCORE_66_USER ((void *)(CMU_CCORE_BASE + 0x0214 + NSL)) |
| #define CLK_CON_DIV_SCLK_HPM_CCORE ((void *)(CMU_CCORE_BASE + 0x0400 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CCORE_800_USER ((void *)(CMU_CCORE_BASE + 0x0500 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CCORE_264_USER ((void *)(CMU_CCORE_BASE + 0x0504 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CCORE_G3D_800_USER ((void *)(CMU_CCORE_BASE + 0x0508 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CCORE_528_USER ((void *)(CMU_CCORE_BASE + 0x050C + NSL)) |
| #define CLK_STAT_MUX_ACLK_CCORE_132_USER ((void *)(CMU_CCORE_BASE + 0x0510 + NSL)) |
| #define CLK_STAT_MUX_PCLK_CCORE_66_USER ((void *)(CMU_CCORE_BASE + 0x0514 + NSL)) |
| #define CLK_ENABLE_ACLK_CCORE0 ((void *)(CMU_CCORE_BASE + 0x0800)) |
| #define CLK_ENABLE_ACLK_CCORE1 ((void *)(CMU_CCORE_BASE + 0x0804)) |
| #define CLK_ENABLE_ACLK_CCORE2 ((void *)(CMU_CCORE_BASE + 0x0808)) |
| #define CLK_ENABLE_ACLK_CCORE3 ((void *)(CMU_CCORE_BASE + 0x080C)) |
| #define CLK_ENABLE_ACLK_CCORE4 ((void *)(CMU_CCORE_BASE + 0x0810)) |
| #define CLK_ENABLE_ACLK_CCORE_AP ((void *)(CMU_CCORE_BASE + 0x0814)) |
| #define CLK_ENABLE_ACLK_CCORE_CP ((void *)(CMU_CCORE_BASE + 0x0818)) |
| #define CLK_ENABLE_PCLK_CCORE_AP ((void *)(CMU_CCORE_BASE + 0x0900)) |
| #define CLK_ENABLE_PCLK_CCORE_CP ((void *)(CMU_CCORE_BASE + 0x0904)) |
| #define CLK_ENABLE_SCLK_HPM_CCORE ((void *)(CMU_CCORE_BASE + 0x0A00)) |
| #define CG_CTRL_VAL_ACLK_CCORE0 ((void *)(CMU_CCORE_BASE + 0x0800)) |
| #define CG_CTRL_VAL_ACLK_CCORE1 ((void *)(CMU_CCORE_BASE + 0x0804)) |
| #define CG_CTRL_VAL_ACLK_CCORE2 ((void *)(CMU_CCORE_BASE + 0x0808)) |
| #define CG_CTRL_VAL_ACLK_CCORE3 ((void *)(CMU_CCORE_BASE + 0x080C)) |
| #define CG_CTRL_VAL_ACLK_CCORE4 ((void *)(CMU_CCORE_BASE + 0x0810)) |
| #define CG_CTRL_VAL_ACLK_CCORE_AP ((void *)(CMU_CCORE_BASE + 0x0814)) |
| #define CG_CTRL_VAL_ACLK_CCORE_CP ((void *)(CMU_CCORE_BASE + 0x0818)) |
| #define CG_CTRL_VAL_PCLK_CCORE_AP ((void *)(CMU_CCORE_BASE + 0x0900)) |
| #define CG_CTRL_VAL_PCLK_CCORE_CP ((void *)(CMU_CCORE_BASE + 0x0904)) |
| #define CG_CTRL_VAL_SCLK_HPM_CCORE ((void *)(CMU_CCORE_BASE + 0x0A00)) |
| #define CLKOUT_CMU_CCORE ((void *)(CMU_CCORE_BASE + 0x0C00)) |
| #define CLKOUT_CMU_CCORE_DIV_STAT ((void *)(CMU_CCORE_BASE + 0x0C04)) |
| #define CLK_ENABLE_PDN_CCORE ((void *)(CMU_CCORE_BASE + 0x0E00)) |
| #define CCORE_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_CCORE_BASE + 0x0F28)) |
| #define PSCDC_CTRL_CCORE ((void *)(CMU_CCORE_BASE + 0x1000)) |
| #define CLK_STOPCTRL_CCORE ((void *)(CMU_CCORE_BASE + 0x1004)) |
| #define CG_CTRL_MAN_ACLK_CCORE0 ((void *)(CMU_CCORE_BASE + 0x1800)) |
| #define CG_CTRL_MAN_ACLK_CCORE1 ((void *)(CMU_CCORE_BASE + 0x1804)) |
| #define CG_CTRL_MAN_ACLK_CCORE2 ((void *)(CMU_CCORE_BASE + 0x1808)) |
| #define CG_CTRL_MAN_ACLK_CCORE3 ((void *)(CMU_CCORE_BASE + 0x180C)) |
| #define CG_CTRL_MAN_ACLK_CCORE4 ((void *)(CMU_CCORE_BASE + 0x1810)) |
| #define CG_CTRL_MAN_ACLK_CCORE_AP ((void *)(CMU_CCORE_BASE + 0x1814)) |
| #define CG_CTRL_MAN_ACLK_CCORE_CP ((void *)(CMU_CCORE_BASE + 0x1818)) |
| #define CG_CTRL_MAN_PCLK_CCORE_AP ((void *)(CMU_CCORE_BASE + 0x1900)) |
| #define CG_CTRL_MAN_PCLK_CCORE_CP ((void *)(CMU_CCORE_BASE + 0x1904)) |
| #define CG_CTRL_MAN_SCLK_HPM_CCORE ((void *)(CMU_CCORE_BASE + 0x1A00)) |
| #define CG_CTRL_STAT_ACLK_CCORE0_0 ((void *)(CMU_CCORE_BASE + 0x1C00)) |
| #define CG_CTRL_STAT_ACLK_CCORE0_1 ((void *)(CMU_CCORE_BASE + 0x1C04)) |
| #define CG_CTRL_STAT_ACLK_CCORE1_0 ((void *)(CMU_CCORE_BASE + 0x1C08)) |
| #define CG_CTRL_STAT_ACLK_CCORE1_1 ((void *)(CMU_CCORE_BASE + 0x1C0C)) |
| #define CG_CTRL_STAT_ACLK_CCORE2 ((void *)(CMU_CCORE_BASE + 0x1C10)) |
| #define CG_CTRL_STAT_ACLK_CCORE3 ((void *)(CMU_CCORE_BASE + 0x1C14)) |
| #define CG_CTRL_STAT_ACLK_CCORE4_0 ((void *)(CMU_CCORE_BASE + 0x1C18)) |
| #define CG_CTRL_STAT_ACLK_CCORE4_1 ((void *)(CMU_CCORE_BASE + 0x1C1C)) |
| #define CG_CTRL_STAT_ACLK_CCORE4_2 ((void *)(CMU_CCORE_BASE + 0x1C20)) |
| #define CG_CTRL_STAT_ACLK_CCORE4_3 ((void *)(CMU_CCORE_BASE + 0x1C24)) |
| #define CG_CTRL_STAT_ACLK_CCORE_AP ((void *)(CMU_CCORE_BASE + 0x1C28)) |
| #define CG_CTRL_STAT_ACLK_CCORE_CP ((void *)(CMU_CCORE_BASE + 0x1C2C)) |
| #define CG_CTRL_STAT_PCLK_CCORE_AP ((void *)(CMU_CCORE_BASE + 0x1D00)) |
| #define CG_CTRL_STAT_PCLK_CCORE_CP ((void *)(CMU_CCORE_BASE + 0x1D04)) |
| #define CG_CTRL_STAT_SCLK_HPM_CCORE ((void *)(CMU_CCORE_BASE + 0x1E00)) |
| #define CMU_CCORE_SPARE0 ((void *)(CMU_CCORE_BASE + 0x1100)) |
| #define CMU_CCORE_SPARE1 ((void *)(CMU_CCORE_BASE + 0x1104)) |
| #define QCH_CTRL_TREX_CCORE ((void *)(CMU_CCORE_BASE + 0x2000)) |
| #define QCH_CTRL_TREX_P_CCORE ((void *)(CMU_CCORE_BASE + 0x2004)) |
| #define QCH_CTRL_LH_G3DIRAM ((void *)(CMU_CCORE_BASE + 0x2008)) |
| #define QCH_CTRL_LH_CCORESFRX ((void *)(CMU_CCORE_BASE + 0x200C)) |
| #define QCH_CTRL_LH_CPPERI ((void *)(CMU_CCORE_BASE + 0x2010)) |
| #define QCH_CTRL_LH_G3D0 ((void *)(CMU_CCORE_BASE + 0x2014)) |
| #define QCH_CTRL_LH_G3D1 ((void *)(CMU_CCORE_BASE + 0x2018)) |
| #define QCH_CTRL_LH_AUD ((void *)(CMU_CCORE_BASE + 0x201C)) |
| #define QCH_CTRL_LH_IMEM ((void *)(CMU_CCORE_BASE + 0x2020)) |
| #define QCH_CTRL_LH_CPDATA ((void *)(CMU_CCORE_BASE + 0x2024)) |
| #define QCH_CTRL_LH_AUDP ((void *)(CMU_CCORE_BASE + 0x2028)) |
| #define QCH_CTRL_LH_G3DP ((void *)(CMU_CCORE_BASE + 0x202C)) |
| #define QCH_CTRL_LH_MIF0P ((void *)(CMU_CCORE_BASE + 0x2030)) |
| #define QCH_CTRL_LH_MIF1P ((void *)(CMU_CCORE_BASE + 0x2034)) |
| #define QCH_CTRL_LH_MIF2P ((void *)(CMU_CCORE_BASE + 0x2038)) |
| #define QCH_CTRL_LH_MIF3P ((void *)(CMU_CCORE_BASE + 0x203C)) |
| #define QCH_CTRL_PMU_CCORE ((void *)(CMU_CCORE_BASE + 0x2040)) |
| #define QCH_CTRL_SYSREG_CCORE ((void *)(CMU_CCORE_BASE + 0x2044)) |
| #define QCH_CTRL_CMU_CCORE ((void *)(CMU_CCORE_BASE + 0x2048)) |
| #define QSTATE_CTRL_AXI_AS_MI_MNGSCS_CCORETD ((void *)(CMU_CCORE_BASE + 0x2400)) |
| #define QSTATE_CTRL_ATB_APL_MNGS ((void *)(CMU_CCORE_BASE + 0x2404)) |
| #define QSTATE_CTRL_APB_AS_MI_MNGSCS_CCOREBDU ((void *)(CMU_CCORE_BASE + 0x2408)) |
| #define QSTATE_CTRL_APB_PDU ((void *)(CMU_CCORE_BASE + 0x240C)) |
| #define QSTATE_CTRL_HSI2C ((void *)(CMU_CCORE_BASE + 0x2410)) |
| #define QSTATE_CTRL_HSI2C_BAT_AP ((void *)(CMU_CCORE_BASE + 0x2414)) |
| #define QSTATE_CTRL_HSI2C_BAT_CP ((void *)(CMU_CCORE_BASE + 0x2418)) |
| #define QSTATE_CTRL_PROMISE ((void *)(CMU_CCORE_BASE + 0x241C)) |
| #define QSTATE_CTRL_AXI_AS_SI_CCORETP_MNGS ((void *)(CMU_CCORE_BASE + 0x2420)) |
| #define QSTATE_CTRL_AXI_AS_SI_CCORETP_APL ((void *)(CMU_CCORE_BASE + 0x2424)) |
| #define DISP_PLL_LOCK ((void *)(CMU_DISP0_BASE + 0x0000)) |
| #define DISP_PLL_CON0 ((void *)(CMU_DISP0_BASE + 0x0100)) |
| #define DISP_PLL_CON1 ((void *)(CMU_DISP0_BASE + 0x0104)) |
| #define DISP_PLL_FREQ_DET ((void *)(CMU_DISP0_BASE + 0x010C)) |
| #define CLK_CON_MUX_DISP_PLL ((void *)(CMU_DISP0_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_ACLK_DISP0_0_400_USER ((void *)(CMU_DISP0_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_ACLK_DISP0_1_400_USER ((void *)(CMU_DISP0_BASE + 0x0208 + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP0_DECON0_ECLK0_USER ((void *)(CMU_DISP0_BASE + 0x020C + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK0_USER ((void *)(CMU_DISP0_BASE + 0x0210 + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK1_USER ((void *)(CMU_DISP0_BASE + 0x0214 + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP0_HDMI_AUDIO_USER ((void *)(CMU_DISP0_BASE + 0x0218 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_HDMIPHY_PIXEL_CLKO_USER ((void *)(CMU_DISP0_BASE + 0x021C + NSL)) |
| #define CLK_CON_MUX_PHYCLK_HDMIPHY_TMDS_CLKO_USER ((void *)(CMU_DISP0_BASE + 0x0220 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_MIPIDPHY0_RXCLKESC0_USER ((void *)(CMU_DISP0_BASE + 0x0224 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER_DISP0 ((void *)(CMU_DISP0_BASE + 0x0228 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER ((void *)(CMU_DISP0_BASE + 0x022C + NSL)) |
| #define CLK_CON_MUX_PHYCLK_MIPIDPHY1_RXCLKESC0_USER ((void *)(CMU_DISP0_BASE + 0x0230 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER_DISP0 ((void *)(CMU_DISP0_BASE + 0x0234 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER ((void *)(CMU_DISP0_BASE + 0x0238 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_MIPIDPHY2_RXCLKESC0_USER ((void *)(CMU_DISP0_BASE + 0x023C + NSL)) |
| #define CLK_CON_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER_DISP0 ((void *)(CMU_DISP0_BASE + 0x0240 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV8_USER ((void *)(CMU_DISP0_BASE + 0x0244 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_DPPHY_CH0_TXD_CLK_USER ((void *)(CMU_DISP0_BASE + 0x0248 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_DPPHY_CH1_TXD_CLK_USER ((void *)(CMU_DISP0_BASE + 0x024C + NSL)) |
| #define CLK_CON_MUX_PHYCLK_DPPHY_CH2_TXD_CLK_USER ((void *)(CMU_DISP0_BASE + 0x0250 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_DPPHY_CH3_TXD_CLK_USER ((void *)(CMU_DISP0_BASE + 0x0254 + NSL)) |
| #define CLK_CON_MUX_ACLK_DISP0_1_400_DISP0 ((void *)(CMU_DISP0_BASE + 0x0258 + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP0_DECON0_ECLK0_DISP0 ((void *)(CMU_DISP0_BASE + 0x025C + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK0_DISP0 ((void *)(CMU_DISP0_BASE + 0x0260 + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK1_DISP0 ((void *)(CMU_DISP0_BASE + 0x0264 + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP0_HDMI_AUDIO_DISP0 ((void *)(CMU_DISP0_BASE + 0x0268 + NSL)) |
| #define CLK_CON_DIV_PCLK_DISP0_0_133 ((void *)(CMU_DISP0_BASE + 0x0400 + NSL)) |
| #define CLK_CON_DIV_SCLK_DECON0_ECLK0 ((void *)(CMU_DISP0_BASE + 0x0404 + NSL)) |
| #define CLK_CON_DIV_SCLK_DECON0_VCLK0 ((void *)(CMU_DISP0_BASE + 0x0408 + NSL)) |
| #define CLK_CON_DIV_SCLK_DECON0_VCLK1 ((void *)(CMU_DISP0_BASE + 0x040C + NSL)) |
| #define CLK_CON_DIV_PHYCLK_HDMIPHY_PIXEL_CLKO ((void *)(CMU_DISP0_BASE + 0x0410 + NSL)) |
| #define CLK_CON_DIV_PHYCLK_HDMIPHY_TMDS_20B_CLKO ((void *)(CMU_DISP0_BASE + 0x0414 + NSL)) |
| #define CLK_CON_DSM_DIV_M_SCLK_HDMI_AUDIO ((void *)(CMU_DISP0_BASE + 0x0500 + NSL)) |
| #define CLK_CON_DSM_DIV_N_SCLK_HDMI_AUDIO ((void *)(CMU_DISP0_BASE + 0x0504 + NSL)) |
| #define CLK_STAT_MUX_DISP_PLL ((void *)(CMU_DISP0_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_ACLK_DISP0_0_400_USER ((void *)(CMU_DISP0_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_ACLK_DISP0_1_400_USER ((void *)(CMU_DISP0_BASE + 0x0608 + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP0_HDMI_AUDIO_USER ((void *)(CMU_DISP0_BASE + 0x060C + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP0_DECON0_ECLK0_USER ((void *)(CMU_DISP0_BASE + 0x0610 + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP0_DECON0_VCLK0_USER ((void *)(CMU_DISP0_BASE + 0x0614 + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP0_DECON0_VCLK1_USER ((void *)(CMU_DISP0_BASE + 0x0618 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_HDMIPHY_PIXEL_CLKO_USER ((void *)(CMU_DISP0_BASE + 0x061C + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_HDMIPHY_TMDS_CLKO_USER ((void *)(CMU_DISP0_BASE + 0x0620 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_MIPIDPHY0_RXCLKESC0_USER ((void *)(CMU_DISP0_BASE + 0x0624 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER_DISP0 ((void *)(CMU_DISP0_BASE + 0x0628 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER ((void *)(CMU_DISP0_BASE + 0x062C + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_MIPIDPHY1_RXCLKESC0_USER ((void *)(CMU_DISP0_BASE + 0x0630 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER_DISP0 ((void *)(CMU_DISP0_BASE + 0x0634 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER ((void *)(CMU_DISP0_BASE + 0x0638 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_MIPIDPHY2_RXCLKESC0_USER ((void *)(CMU_DISP0_BASE + 0x063C + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER_DISP0 ((void *)(CMU_DISP0_BASE + 0x0640 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV8_USER ((void *)(CMU_DISP0_BASE + 0x0644 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_DPPHY_CH0_TXD_CLK_USER ((void *)(CMU_DISP0_BASE + 0x0648 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_DPPHY_CH1_TXD_CLK_USER ((void *)(CMU_DISP0_BASE + 0x064C + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_DPPHY_CH2_TXD_CLK_USER ((void *)(CMU_DISP0_BASE + 0x0650 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_DPPHY_CH3_TXD_CLK_USER ((void *)(CMU_DISP0_BASE + 0x0654 + NSL)) |
| #define CLK_STAT_MUX_ACLK_DISP0_1_400_DISP0 ((void *)(CMU_DISP0_BASE + 0x0658 + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP0_DECON0_ECLK0_DISP0 ((void *)(CMU_DISP0_BASE + 0x065C + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP0_DECON0_VCLK0_DISP0 ((void *)(CMU_DISP0_BASE + 0x0660 + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP0_DECON0_VCLK1_DISP0 ((void *)(CMU_DISP0_BASE + 0x0664 + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP0_HDMI_AUDIO_DISP0 ((void *)(CMU_DISP0_BASE + 0x0668 + NSL)) |
| #define CG_CTRL_VAL_ACLK_DISP0_0_400 ((void *)(CMU_DISP0_BASE + 0x0800)) |
| #define CG_CTRL_VAL_ACLK_DISP0_1_400 ((void *)(CMU_DISP0_BASE + 0x0804)) |
| #define CG_CTRL_VAL_ACLK_DISP0_0_400_SECURE_SFW_DISP0_0 ((void *)(CMU_DISP0_BASE + 0x0808)) |
| #define CG_CTRL_VAL_ACLK_DISP0_1_400_SECURE_SFW_DISP0_1 ((void *)(CMU_DISP0_BASE + 0x080C)) |
| #define CG_CTRL_VAL_PCLK_DISP0_0_133 ((void *)(CMU_DISP0_BASE + 0x0820)) |
| #define CG_CTRL_VAL_PCLK_DISP0_0_133_HPM_APBIF_DISP0 ((void *)(CMU_DISP0_BASE + 0x0824)) |
| #define CG_CTRL_VAL_PCLK_DISP0_0_133_SECURE_DECON0 ((void *)(CMU_DISP0_BASE + 0x0828)) |
| #define CG_CTRL_VAL_PCLK_DISP0_0_133_SECURE_VPP0 ((void *)(CMU_DISP0_BASE + 0x082C)) |
| #define CG_CTRL_VAL_PCLK_DISP0_0_133_SECURE_SFW_DISP0_0 ((void *)(CMU_DISP0_BASE + 0x0830)) |
| #define CG_CTRL_VAL_PCLK_DISP0_0_133_SECURE_SFW_DISP0_1 ((void *)(CMU_DISP0_BASE + 0x0834)) |
| #define CG_CTRL_VAL_SCLK_DISP1_400 ((void *)(CMU_DISP0_BASE + 0x0840)) |
| #define CG_CTRL_VAL_SCLK_DECON0_ECLK0 ((void *)(CMU_DISP0_BASE + 0x0844)) |
| #define CG_CTRL_VAL_SCLK_DECON0_VCLK0 ((void *)(CMU_DISP0_BASE + 0x0848)) |
| #define CG_CTRL_VAL_SCLK_DECON0_VCLK1 ((void *)(CMU_DISP0_BASE + 0x084C)) |
| #define CG_CTRL_VAL_SCLK_HDMI_AUDIO ((void *)(CMU_DISP0_BASE + 0x0850)) |
| #define CG_CTRL_VAL_SCLK_DISP0_PROMISE ((void *)(CMU_DISP0_BASE + 0x0854)) |
| #define CG_CTRL_VAL_PHYCLK_HDMIPHY ((void *)(CMU_DISP0_BASE + 0x0858)) |
| #define CG_CTRL_VAL_PHYCLK_MIPIDPHY0 ((void *)(CMU_DISP0_BASE + 0x085C)) |
| #define CG_CTRL_VAL_PHYCLK_MIPIDPHY1 ((void *)(CMU_DISP0_BASE + 0x0860)) |
| #define CG_CTRL_VAL_PHYCLK_MIPIDPHY2 ((void *)(CMU_DISP0_BASE + 0x0864)) |
| #define CG_CTRL_VAL_PHYCLK_DPPHY ((void *)(CMU_DISP0_BASE + 0x0868)) |
| #define CG_CTRL_VAL_OSCCLK ((void *)(CMU_DISP0_BASE + 0x086C)) |
| #define CLKOUT_CMU_DISP0 ((void *)(CMU_DISP0_BASE + 0x0C00)) |
| #define CLKOUT_CMU_DISP0_DIV_STAT ((void *)(CMU_DISP0_BASE + 0x0C04)) |
| #define DISP0_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_DISP0_BASE + 0x0D04)) |
| #define CMU_DISP0_SPARE0 ((void *)(CMU_DISP0_BASE + 0x0D08)) |
| #define CMU_DISP0_SPARE1 ((void *)(CMU_DISP0_BASE + 0x0D0C)) |
| #define CG_CTRL_MAN_ACLK_DISP0_0_400 ((void *)(CMU_DISP0_BASE + 0x1800)) |
| #define CG_CTRL_MAN_ACLK_DISP0_1_400 ((void *)(CMU_DISP0_BASE + 0x1804)) |
| #define CG_CTRL_MAN_ACLK_DISP0_0_400_SECURE_SFW_DISP0_0 ((void *)(CMU_DISP0_BASE + 0x1808)) |
| #define CG_CTRL_MAN_ACLK_DISP0_1_400_SECURE_SFW_DISP0_1 ((void *)(CMU_DISP0_BASE + 0x180C)) |
| #define CG_CTRL_MAN_PCLK_DISP0_0_133 ((void *)(CMU_DISP0_BASE + 0x1820)) |
| #define CG_CTRL_MAN_PCLK_DISP0_0_133_HPM_APBIF_DISP0 ((void *)(CMU_DISP0_BASE + 0x1824)) |
| #define CG_CTRL_MAN_PCLK_DISP0_0_133_SECURE_DECON0 ((void *)(CMU_DISP0_BASE + 0x1828)) |
| #define CG_CTRL_MAN_PCLK_DISP0_0_133_SECURE_VPP0 ((void *)(CMU_DISP0_BASE + 0x182C)) |
| #define CG_CTRL_MAN_PCLK_DISP0_0_133_SECURE_SFW_DISP0_0 ((void *)(CMU_DISP0_BASE + 0x1830)) |
| #define CG_CTRL_MAN_PCLK_DISP0_0_133_SECURE_SFW_DISP0_1 ((void *)(CMU_DISP0_BASE + 0x1834)) |
| #define CG_CTRL_MAN_SCLK_DISP1_400 ((void *)(CMU_DISP0_BASE + 0x1840)) |
| #define CG_CTRL_MAN_SCLK_DECON0_ECLK0 ((void *)(CMU_DISP0_BASE + 0x1844)) |
| #define CG_CTRL_MAN_SCLK_DECON0_VCLK0 ((void *)(CMU_DISP0_BASE + 0x1848)) |
| #define CG_CTRL_MAN_SCLK_DECON0_VCLK1 ((void *)(CMU_DISP0_BASE + 0x184C)) |
| #define CG_CTRL_MAN_SCLK_HDMI_AUDIO ((void *)(CMU_DISP0_BASE + 0x1850)) |
| #define CG_CTRL_MAN_SCLK_DISP0_PROMISE ((void *)(CMU_DISP0_BASE + 0x1854)) |
| #define CG_CTRL_MAN_PHYCLK_HDMIPHY ((void *)(CMU_DISP0_BASE + 0x1858)) |
| #define CG_CTRL_MAN_PHYCLK_MIPIDPHY0 ((void *)(CMU_DISP0_BASE + 0x185C)) |
| #define CG_CTRL_MAN_PHYCLK_MIPIDPHY1 ((void *)(CMU_DISP0_BASE + 0x1860)) |
| #define CG_CTRL_MAN_PHYCLK_MIPIDPHY2 ((void *)(CMU_DISP0_BASE + 0x1864)) |
| #define CG_CTRL_MAN_PHYCLK_DPPHY ((void *)(CMU_DISP0_BASE + 0x1868)) |
| #define CG_CTRL_MAN_OSCCLK ((void *)(CMU_DISP0_BASE + 0x186C)) |
| #define CG_CTRL_STAT_ACLK_DISP0_0_400 ((void *)(CMU_DISP0_BASE + 0x1C00)) |
| #define CG_CTRL_STAT_ACLK_DISP0_1_400 ((void *)(CMU_DISP0_BASE + 0x1C04)) |
| #define CG_CTRL_STAT_ACLK_DISP0_0_400_SECURE_SFW_DISP0_0 ((void *)(CMU_DISP0_BASE + 0x1C08)) |
| #define CG_CTRL_STAT_ACLK_DISP0_1_400_SECURE_SFW_DISP0_1 ((void *)(CMU_DISP0_BASE + 0x1C0C)) |
| #define CG_CTRL_STAT_PCLK_DISP0_0_133_0 ((void *)(CMU_DISP0_BASE + 0x1C20)) |
| #define CG_CTRL_STAT_PCLK_DISP0_0_133_1 ((void *)(CMU_DISP0_BASE + 0x1C24)) |
| #define CG_CTRL_STAT_PCLK_DISP0_0_133_2 ((void *)(CMU_DISP0_BASE + 0x1C28)) |
| #define CG_CTRL_STAT_PCLK_DISP0_0_133_HPM_APBIF_DISP0 ((void *)(CMU_DISP0_BASE + 0x1C2C)) |
| #define CG_CTRL_STAT_PCLK_DISP0_0_133_SECURE_DECON0 ((void *)(CMU_DISP0_BASE + 0x1C30)) |
| #define CG_CTRL_STAT_PCLK_DISP0_0_133_SECURE_VPP0 ((void *)(CMU_DISP0_BASE + 0x1C34)) |
| #define CG_CTRL_STAT_PCLK_DISP0_0_133_SECURE_SFW_DISP0_0 ((void *)(CMU_DISP0_BASE + 0x1C38)) |
| #define CG_CTRL_STAT_PCLK_DISP0_0_133_SECURE_SFW_DISP0_1 ((void *)(CMU_DISP0_BASE + 0x1C3C)) |
| #define CG_CTRL_STAT_SCLK_DISP1_400 ((void *)(CMU_DISP0_BASE + 0x1C40)) |
| #define CG_CTRL_STAT_SCLK_DECON0_ECLK0 ((void *)(CMU_DISP0_BASE + 0x1C44)) |
| #define CG_CTRL_STAT_SCLK_DECON0_VCLK0 ((void *)(CMU_DISP0_BASE + 0x1C48)) |
| #define CG_CTRL_STAT_SCLK_DECON0_VCLK1 ((void *)(CMU_DISP0_BASE + 0x1C4C)) |
| #define CG_CTRL_STAT_SCLK_HDMI_AUDIO ((void *)(CMU_DISP0_BASE + 0x1C50)) |
| #define CG_CTRL_STAT_SCLK_DISP0_PROMISE ((void *)(CMU_DISP0_BASE + 0x1C54)) |
| #define CG_CTRL_STAT_PHYCLK_HDMIPHY ((void *)(CMU_DISP0_BASE + 0x1C58)) |
| #define CG_CTRL_STAT_PHYCLK_MIPIDPHY0 ((void *)(CMU_DISP0_BASE + 0x1C5C)) |
| #define CG_CTRL_STAT_PHYCLK_MIPIDPHY1 ((void *)(CMU_DISP0_BASE + 0x1C60)) |
| #define CG_CTRL_STAT_PHYCLK_MIPIDPHY2 ((void *)(CMU_DISP0_BASE + 0x1C64)) |
| #define CG_CTRL_STAT_PHYCLK_DPPHY ((void *)(CMU_DISP0_BASE + 0x1C68)) |
| #define CG_CTRL_STAT_OSCCLK ((void *)(CMU_DISP0_BASE + 0x1C6C)) |
| #define QCH_CTRL_AXI_LH_ASYNC_MI_DISP0SFR ((void *)(CMU_DISP0_BASE + 0x2000)) |
| #define QCH_CTRL_CMU_DISP0 ((void *)(CMU_DISP0_BASE + 0x2004)) |
| #define QCH_CTRL_PMU_DISP0 ((void *)(CMU_DISP0_BASE + 0x2008)) |
| #define QCH_CTRL_SYSREG_DISP0 ((void *)(CMU_DISP0_BASE + 0x200C)) |
| #define QCH_CTRL_DECON0 ((void *)(CMU_DISP0_BASE + 0x2010)) |
| #define QCH_CTRL_VPP0 ((void *)(CMU_DISP0_BASE + 0x2014)) |
| #define QCH_CTRL_VPP0_G0 ((void *)(CMU_DISP0_BASE + 0x2014)) |
| #define QCH_CTRL_VPP0_G1 ((void *)(CMU_DISP0_BASE + 0x2018)) |
| #define QCH_CTRL_DSIM0 ((void *)(CMU_DISP0_BASE + 0x2020)) |
| #define QCH_CTRL_DSIM1 ((void *)(CMU_DISP0_BASE + 0x2024)) |
| #define QCH_CTRL_DSIM2 ((void *)(CMU_DISP0_BASE + 0x2028)) |
| #define QCH_CTRL_HDMI ((void *)(CMU_DISP0_BASE + 0x202C)) |
| #define QCH_CTRL_DP ((void *)(CMU_DISP0_BASE + 0x2030)) |
| #define QCH_CTRL_PPMU_DISP0_0 ((void *)(CMU_DISP0_BASE + 0x2034)) |
| #define QCH_CTRL_PPMU_DISP0_1 ((void *)(CMU_DISP0_BASE + 0x203C)) |
| #define QCH_CTRL_SMMU_DISP0_0 ((void *)(CMU_DISP0_BASE + 0x2040)) |
| #define QCH_CTRL_SMMU_DISP0_1 ((void *)(CMU_DISP0_BASE + 0x2044)) |
| #define QCH_CTRL_SFW_DISP0_0 ((void *)(CMU_DISP0_BASE + 0x2048)) |
| #define QCH_CTRL_SFW_DISP0_1 ((void *)(CMU_DISP0_BASE + 0x204C)) |
| #define QCH_CTRL_LH_ASYNC_SI_R_TOP_DISP ((void *)(CMU_DISP0_BASE + 0x2050)) |
| #define QCH_CTRL_LH_ASYNC_SI_TOP_DISP ((void *)(CMU_DISP0_BASE + 0x2054)) |
| #define QSTATE_CTRL_DSIM0 ((void *)(CMU_DISP0_BASE + 0x240C)) |
| #define QSTATE_CTRL_DSIM1 ((void *)(CMU_DISP0_BASE + 0x2410)) |
| #define QSTATE_CTRL_DSIM2 ((void *)(CMU_DISP0_BASE + 0x2414)) |
| #define QSTATE_CTRL_HDMI ((void *)(CMU_DISP0_BASE + 0x2418)) |
| #define QSTATE_CTRL_HDMI_AUDIO ((void *)(CMU_DISP0_BASE + 0x241C)) |
| #define QSTATE_CTRL_DP ((void *)(CMU_DISP0_BASE + 0x2420)) |
| #define QSTATE_CTRL_DISP0_MUX ((void *)(CMU_DISP0_BASE + 0x2424)) |
| #define QSTATE_CTRL_HDMI_PHY ((void *)(CMU_DISP0_BASE + 0x2428)) |
| #define QSTATE_CTRL_DISP1_400 ((void *)(CMU_DISP0_BASE + 0x2434)) |
| #define QSTATE_CTRL_DECON0 ((void *)(CMU_DISP0_BASE + 0x2438)) |
| #define QSTATE_CTRL_HPM_APBIF_DISP0 ((void *)(CMU_DISP0_BASE + 0x2444)) |
| #define QSTATE_CTRL_PROMISE_DISP0 ((void *)(CMU_DISP0_BASE + 0x2448)) |
| #define QSTATE_CTRL_DPTX_PHY ((void *)(CMU_DISP0_BASE + 0x2484)) |
| #define QSTATE_CTRL_MIPI_DPHY_M1S0 ((void *)(CMU_DISP0_BASE + 0x2488)) |
| #define QSTATE_CTRL_MIPI_DPHY_M4S0 ((void *)(CMU_DISP0_BASE + 0x248C)) |
| #define QSTATE_CTRL_MIPI_DPHY_M4S4 ((void *)(CMU_DISP0_BASE + 0x2490)) |
| #define CLK_CON_MUX_ACLK_DISP1_0_400_USER ((void *)(CMU_DISP1_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_ACLK_DISP1_1_400_USER ((void *)(CMU_DISP1_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK0_USER ((void *)(CMU_DISP1_BASE + 0x0208 + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK1_USER ((void *)(CMU_DISP1_BASE + 0x020C + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP1_600_USER ((void *)(CMU_DISP1_BASE + 0x0210 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER_DISP1 ((void *)(CMU_DISP1_BASE + 0x0214 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER_DISP1 ((void *)(CMU_DISP1_BASE + 0x0218 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER_DISP1 ((void *)(CMU_DISP1_BASE + 0x021C + NSL)) |
| #define CLK_CON_MUX_PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_USER ((void *)(CMU_DISP1_BASE + 0x0220 + NSL)) |
| #define CLK_CON_MUX_ACLK_DISP1_1_400_DISP1 ((void *)(CMU_DISP1_BASE + 0x0224 + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK0_DISP1 ((void *)(CMU_DISP1_BASE + 0x0228 + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK1_DISP1 ((void *)(CMU_DISP1_BASE + 0x022C + NSL)) |
| #define CLK_CON_MUX_SCLK_DECON1_ECLK1 ((void *)(CMU_DISP1_BASE + 0x0230 + NSL)) |
| #define CLK_CON_DIV_PCLK_DISP1_0_133 ((void *)(CMU_DISP1_BASE + 0x0400 + NSL)) |
| #define CLK_CON_DIV_SCLK_DECON1_ECLK0 ((void *)(CMU_DISP1_BASE + 0x0404 + NSL)) |
| #define CLK_CON_DIV_SCLK_DECON1_ECLK1 ((void *)(CMU_DISP1_BASE + 0x0408 + NSL)) |
| #define CLK_STAT_MUX_ACLK_DISP1_0_400_USER ((void *)(CMU_DISP1_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_ACLK_DISP1_1_400_USER ((void *)(CMU_DISP1_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP1_DECON1_ECLK0_USER ((void *)(CMU_DISP1_BASE + 0x0608 + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP1_DECON1_ECLK1_USER ((void *)(CMU_DISP1_BASE + 0x060C + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER_DISP1 ((void *)(CMU_DISP1_BASE + 0x0610 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER_DISP1 ((void *)(CMU_DISP1_BASE + 0x0614 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER_DISP1 ((void *)(CMU_DISP1_BASE + 0x0618 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_USER ((void *)(CMU_DISP1_BASE + 0x061C + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP1_600_USER ((void *)(CMU_DISP1_BASE + 0x0620 + NSL)) |
| #define CLK_STAT_MUX_ACLK_DISP1_1_400_DISP1 ((void *)(CMU_DISP1_BASE + 0x0624 + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP1_DECON1_ECLK0_DISP1 ((void *)(CMU_DISP1_BASE + 0x0628 + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP1_DECON1_ECLK1_DISP1 ((void *)(CMU_DISP1_BASE + 0x062C + NSL)) |
| #define CLK_STAT_MUX_SCLK_DECON1_ECLK1 ((void *)(CMU_DISP1_BASE + 0x0630 + NSL)) |
| #define CG_CTRL_VAL_ACLK_DISP1_0_400 ((void *)(CMU_DISP1_BASE + 0x0800)) |
| #define CG_CTRL_VAL_ACLK_DISP1_1_400 ((void *)(CMU_DISP1_BASE + 0x0804)) |
| #define CG_CTRL_VAL_ACLK_DISP1_0_400_SECURE_SFW_DISP1_0 ((void *)(CMU_DISP1_BASE + 0x0808)) |
| #define CG_CTRL_VAL_ACLK_DISP1_1_400_SECURE_SFW_DISP1_1 ((void *)(CMU_DISP1_BASE + 0x080C)) |
| #define CG_CTRL_VAL_PCLK_DISP1_0_133 ((void *)(CMU_DISP1_BASE + 0x0820)) |
| #define CG_CTRL_VAL_PCLK_DISP1_0_133_HPM_APBIF_DISP1 ((void *)(CMU_DISP1_BASE + 0x0824)) |
| #define CG_CTRL_VAL_PCLK_DISP1_0_133_SECURE_SFW_DISP1_0 ((void *)(CMU_DISP1_BASE + 0x0828)) |
| #define CG_CTRL_VAL_PCLK_DISP1_0_133_SECURE_SFW_DISP1_1 ((void *)(CMU_DISP1_BASE + 0x082C)) |
| #define CG_CTRL_VAL_SCLK_DECON1_ECLK_0 ((void *)(CMU_DISP1_BASE + 0x0840)) |
| #define CG_CTRL_VAL_SCLK_DECON1_ECLK_1 ((void *)(CMU_DISP1_BASE + 0x0844)) |
| #define CG_CTRL_VAL_SCLK_DISP1_PROMISE ((void *)(CMU_DISP1_BASE + 0x0848)) |
| #define CLKOUT_CMU_DISP1 ((void *)(CMU_DISP1_BASE + 0x0C00)) |
| #define CLKOUT_CMU_DISP1_DIV_STAT ((void *)(CMU_DISP1_BASE + 0x0C04)) |
| #define DISP1_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_DISP1_BASE + 0x0D04)) |
| #define CMU_DISP1_SPARE0 ((void *)(CMU_DISP1_BASE + 0x0D08)) |
| #define CMU_DISP1_SPARE1 ((void *)(CMU_DISP1_BASE + 0x0D0C)) |
| #define CG_CTRL_MAN_ACLK_DISP1_0_400 ((void *)(CMU_DISP1_BASE + 0x1800)) |
| #define CG_CTRL_MAN_ACLK_DISP1_1_400 ((void *)(CMU_DISP1_BASE + 0x1804)) |
| #define CG_CTRL_MAN_ACLK_DISP1_0_400_SECURE_SFW_DISP1_0 ((void *)(CMU_DISP1_BASE + 0x1808)) |
| #define CG_CTRL_MAN_ACLK_DISP1_1_400_SECURE_SFW_DISP1_1 ((void *)(CMU_DISP1_BASE + 0x180C)) |
| #define CG_CTRL_MAN_PCLK_DISP1_0_133 ((void *)(CMU_DISP1_BASE + 0x1820)) |
| #define CG_CTRL_MAN_PCLK_DISP1_0_133_HPM_APBIF_DISP1 ((void *)(CMU_DISP1_BASE + 0x1824)) |
| #define CG_CTRL_MAN_PCLK_DISP1_0_133_SECURE_SFW_DISP1_0 ((void *)(CMU_DISP1_BASE + 0x1828)) |
| #define CG_CTRL_MAN_PCLK_DISP1_0_133_SECURE_SFW_DISP1_1 ((void *)(CMU_DISP1_BASE + 0x182C)) |
| #define CG_CTRL_MAN_SCLK_DECON1_ECLK_0 ((void *)(CMU_DISP1_BASE + 0x1840)) |
| #define CG_CTRL_MAN_SCLK_DECON1_ECLK_1 ((void *)(CMU_DISP1_BASE + 0x1844)) |
| #define CG_CTRL_MAN_SCLK_DISP1_PROMISE ((void *)(CMU_DISP1_BASE + 0x1848)) |
| #define CG_CTRL_STAT_ACLK_DISP1_0_400 ((void *)(CMU_DISP1_BASE + 0x1C00)) |
| #define CG_CTRL_STAT_ACLK_DISP1_1_400 ((void *)(CMU_DISP1_BASE + 0x1C04)) |
| #define CG_CTRL_STAT_ACLK_DISP1_0_400_SECURE_SFW_DISP1_0 ((void *)(CMU_DISP1_BASE + 0x1C08)) |
| #define CG_CTRL_STAT_ACLK_DISP1_1_400_SECURE_SFW_DISP1_1 ((void *)(CMU_DISP1_BASE + 0x1C0C)) |
| #define CG_CTRL_STAT_PCLK_DISP1_0_133_0 ((void *)(CMU_DISP1_BASE + 0x1C20)) |
| #define CG_CTRL_STAT_PCLK_DISP1_0_133_1 ((void *)(CMU_DISP1_BASE + 0x1C24)) |
| #define CG_CTRL_STAT_PCLK_DISP1_0_133_2 ((void *)(CMU_DISP1_BASE + 0x1C28)) |
| #define CG_CTRL_STAT_PCLK_DISP1_0_133_HPM_APBIF_DISP1 ((void *)(CMU_DISP1_BASE + 0x1C2C)) |
| #define CG_CTRL_STAT_PCLK_DISP1_0_133_SECURE_SFW_DISP1_0 ((void *)(CMU_DISP1_BASE + 0x1C30)) |
| #define CG_CTRL_STAT_PCLK_DISP1_0_133_SECURE_SFW_DISP1_1 ((void *)(CMU_DISP1_BASE + 0x1C34)) |
| #define CG_CTRL_STAT_SCLK_DECON1_ECLK_0 ((void *)(CMU_DISP1_BASE + 0x1C40)) |
| #define CG_CTRL_STAT_SCLK_DECON1_ECLK_1 ((void *)(CMU_DISP1_BASE + 0x1C44)) |
| #define CG_CTRL_STAT_SCLK_DISP1_PROMISE ((void *)(CMU_DISP1_BASE + 0x1C48)) |
| #define QCH_CTRL_AXI_LH_ASYNC_MI_DISP1SFR ((void *)(CMU_DISP1_BASE + 0x2000)) |
| #define QCH_CTRL_CMU_DISP1 ((void *)(CMU_DISP1_BASE + 0x2004)) |
| #define QCH_CTRL_PMU_DISP1 ((void *)(CMU_DISP1_BASE + 0x2008)) |
| #define QCH_CTRL_SYSREG_DISP1 ((void *)(CMU_DISP1_BASE + 0x200C)) |
| #define QCH_CTRL_VPP1 ((void *)(CMU_DISP1_BASE + 0x2010)) |
| #define QCH_CTRL_VPP1_G2 ((void *)(CMU_DISP1_BASE + 0x2010)) |
| #define QCH_CTRL_VPP1_G3 ((void *)(CMU_DISP1_BASE + 0x2014)) |
| #define QCH_CTRL_DECON1_PCLK_0 ((void *)(CMU_DISP1_BASE + 0x201C)) |
| #define QCH_CTRL_DECON1_PCLK_1 ((void *)(CMU_DISP1_BASE + 0x2020)) |
| #define QCH_CTRL_PPMU_DISP1_0 ((void *)(CMU_DISP1_BASE + 0x2028)) |
| #define QCH_CTRL_PPMU_DISP1_1 ((void *)(CMU_DISP1_BASE + 0x202C)) |
| #define QCH_CTRL_SMMU_DISP1_0 ((void *)(CMU_DISP1_BASE + 0x2030)) |
| #define QCH_CTRL_SMMU_DISP1_1 ((void *)(CMU_DISP1_BASE + 0x2034)) |
| #define QCH_CTRL_SFW_DISP1_0 ((void *)(CMU_DISP1_BASE + 0x2038)) |
| #define QCH_CTRL_SFW_DISP1_1 ((void *)(CMU_DISP1_BASE + 0x203C)) |
| #define QCH_CTRL_AXI_LH_ASYNC_SI_DISP1_0 ((void *)(CMU_DISP1_BASE + 0x2040)) |
| #define QCH_CTRL_AXI_LH_ASYNC_SI_DISP1_1 ((void *)(CMU_DISP1_BASE + 0x2044)) |
| #define QSTATE_CTRL_DECON1_ECLK_0 ((void *)(CMU_DISP1_BASE + 0x240C)) |
| #define QSTATE_CTRL_DECON1_ECLK_1 ((void *)(CMU_DISP1_BASE + 0x2410)) |
| #define QSTATE_CTRL_HPM_APBIF_DISP1 ((void *)(CMU_DISP1_BASE + 0x241C)) |
| #define QSTATE_CTRL_PROMISE_DISP1 ((void *)(CMU_DISP1_BASE + 0x2420)) |
| #define CLK_CON_MUX_ACLK_FSYS0_200_USER ((void *)(CMU_FSYS0_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS0_USBDRD30_USER ((void *)(CMU_FSYS0_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS0_MMC0_USER ((void *)(CMU_FSYS0_BASE + 0x0208 + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_USER ((void *)(CMU_FSYS0_BASE + 0x020C + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS0_24M_USER ((void *)(CMU_FSYS0_BASE + 0x0210 + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_CFG_USER ((void *)(CMU_FSYS0_BASE + 0x0214 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER ((void *)(CMU_FSYS0_BASE + 0x0218 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER ((void *)(CMU_FSYS0_BASE + 0x021C + NSL)) |
| #define CLK_CON_MUX_PHYCLK_UFS_TX0_SYMBOL_USER ((void *)(CMU_FSYS0_BASE + 0x0220 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_UFS_RX0_SYMBOL_USER ((void *)(CMU_FSYS0_BASE + 0x0224 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_USBHOST20_PHYCLOCK_USER ((void *)(CMU_FSYS0_BASE + 0x0228 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_USBHOST20_FREECLK_USER ((void *)(CMU_FSYS0_BASE + 0x022C + NSL)) |
| #define CLK_CON_MUX_PHYCLK_USBHOST20_CLK48MOHCI_USER ((void *)(CMU_FSYS0_BASE + 0x0230 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_USBHOST20PHY_REF_CLK ((void *)(CMU_FSYS0_BASE + 0x0234 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_UFS_RX_PWM_CLK_USER ((void *)(CMU_FSYS0_BASE + 0x0238 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_UFS_TX_PWM_CLK_USER ((void *)(CMU_FSYS0_BASE + 0x023C + NSL)) |
| #define CLK_CON_MUX_PHYCLK_UFS_REFCLK_OUT_SOC_USER ((void *)(CMU_FSYS0_BASE + 0x0240 + NSL)) |
| #define CLK_STAT_MUX_ACLK_FSYS0_200_USER ((void *)(CMU_FSYS0_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS0_USBDRD30_USER ((void *)(CMU_FSYS0_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS0_MMC0_USER ((void *)(CMU_FSYS0_BASE + 0x0608 + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_USER ((void *)(CMU_FSYS0_BASE + 0x060C + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS0_24M_USER ((void *)(CMU_FSYS0_BASE + 0x0610 + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_CFG_USER ((void *)(CMU_FSYS0_BASE + 0x0614 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER ((void *)(CMU_FSYS0_BASE + 0x0618 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER ((void *)(CMU_FSYS0_BASE + 0x061C + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_UFS_TX0_SYMBOL_USER ((void *)(CMU_FSYS0_BASE + 0x0620 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_UFS_RX0_SYMBOL_USER ((void *)(CMU_FSYS0_BASE + 0x0624 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_USBHOST20_PHYCLOCK_USER ((void *)(CMU_FSYS0_BASE + 0x0628 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_USBHOST20_FREECLK_USER ((void *)(CMU_FSYS0_BASE + 0x062C + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_USBHOST20_CLK48MOHCI_USER ((void *)(CMU_FSYS0_BASE + 0x0630 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_USBHOST20PHY_REF_CLK ((void *)(CMU_FSYS0_BASE + 0x0634 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_UFS_RX_PWM_CLK_USER ((void *)(CMU_FSYS0_BASE + 0x0638 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_UFS_TX_PWM_CLK_USER ((void *)(CMU_FSYS0_BASE + 0x063C + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_UFS_REFCLK_OUT_SOC_USER ((void *)(CMU_FSYS0_BASE + 0x0640 + NSL)) |
| #define CG_CTRL_VAL_ACLK_FSYS0_200 ((void *)(CMU_FSYS0_BASE + 0x0800)) |
| #define CG_CTRL_VAL_PCLK_HPM_APBIF_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x0820)) |
| #define CG_CTRL_VAL_SCLK_USBDRD30_SUSPEND_CLK ((void *)(CMU_FSYS0_BASE + 0x0840)) |
| #define CG_CTRL_VAL_SCLK_MMC0 ((void *)(CMU_FSYS0_BASE + 0x0844)) |
| #define CG_CTRL_VAL_SCLK_UFSUNIPRO_EMBEDDED ((void *)(CMU_FSYS0_BASE + 0x0848)) |
| #define CG_CTRL_VAL_SCLK_USBDRD30_REF_CLK ((void *)(CMU_FSYS0_BASE + 0x084C)) |
| #define CG_CTRL_VAL_PHYCLK_USBDRD30_UDRD30_PHYCLOCK ((void *)(CMU_FSYS0_BASE + 0x0850)) |
| #define CG_CTRL_VAL_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK ((void *)(CMU_FSYS0_BASE + 0x0854)) |
| #define CG_CTRL_VAL_PHYCLK_UFS_TX0_SYMBOL ((void *)(CMU_FSYS0_BASE + 0x0858)) |
| #define CG_CTRL_VAL_PHYCLK_UFS_RX0_SYMBOL ((void *)(CMU_FSYS0_BASE + 0x085C)) |
| #define CG_CTRL_VAL_PHYCLK_USBHOST20_PHYCLOCK ((void *)(CMU_FSYS0_BASE + 0x0860)) |
| #define CG_CTRL_VAL_SCLK_USBHOST20_REF_CLK ((void *)(CMU_FSYS0_BASE + 0x0864)) |
| #define CG_CTRL_VAL_PHYCLK_USBHOST20_FREECLK ((void *)(CMU_FSYS0_BASE + 0x0864)) |
| #define CG_CTRL_VAL_PHYCLK_USBHOST20_CLK48MOHCI ((void *)(CMU_FSYS0_BASE + 0x0868)) |
| #define CG_CTRL_VAL_PHYCLK_UFS_RX_PWM_CLK ((void *)(CMU_FSYS0_BASE + 0x086C)) |
| #define CG_CTRL_VAL_PHYCLK_UFS_TX_PWM_CLK ((void *)(CMU_FSYS0_BASE + 0x0870)) |
| #define CG_CTRL_VAL_PHYCLK_UFS_REFCLK_OUT_SOC ((void *)(CMU_FSYS0_BASE + 0x0874)) |
| #define CG_CTRL_VAL_SCLK_PROMISE_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x0878)) |
| #define CG_CTRL_VAL_SCLK_USBHOST20PHY_REF_CLK ((void *)(CMU_FSYS0_BASE + 0x087C)) |
| #define CG_CTRL_VAL_SCLK_UFSUNIPRO_EMBEDDED_CFG ((void *)(CMU_FSYS0_BASE + 0x0880)) |
| #define CLKOUT_CMU_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x0C00)) |
| #define CLKOUT_CMU_FSYS0_DIV_STAT ((void *)(CMU_FSYS0_BASE + 0x0C04)) |
| #define FSYS0_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_FSYS0_BASE + 0x0D04)) |
| #define CMU_FSYS0_SPARE0 ((void *)(CMU_FSYS0_BASE + 0x0D08)) |
| #define CMU_FSYS0_SPARE1 ((void *)(CMU_FSYS0_BASE + 0x0D0C)) |
| #define CG_CTRL_MAN_ACLK_FSYS0_200 ((void *)(CMU_FSYS0_BASE + 0x1800)) |
| #define CG_CTRL_MAN_PCLK_HPM_APBIF_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x1820)) |
| #define CG_CTRL_MAN_SCLK_USBDRD30_SUSPEND_CLK ((void *)(CMU_FSYS0_BASE + 0x1840)) |
| #define CG_CTRL_MAN_SCLK_MMC0 ((void *)(CMU_FSYS0_BASE + 0x1844)) |
| #define CG_CTRL_MAN_SCLK_UFSUNIPRO_EMBEDDED ((void *)(CMU_FSYS0_BASE + 0x1848)) |
| #define CG_CTRL_MAN_SCLK_USBDRD30_REF_CLK ((void *)(CMU_FSYS0_BASE + 0x184C)) |
| #define CG_CTRL_MAN_PHYCLK_USBDRD30_UDRD30_PHYCLOCK ((void *)(CMU_FSYS0_BASE + 0x1850)) |
| #define CG_CTRL_MAN_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK ((void *)(CMU_FSYS0_BASE + 0x1854)) |
| #define CG_CTRL_MAN_PHYCLK_UFS_TX0_SYMBOL ((void *)(CMU_FSYS0_BASE + 0x1858)) |
| #define CG_CTRL_MAN_PHYCLK_UFS_RX0_SYMBOL ((void *)(CMU_FSYS0_BASE + 0x185C)) |
| #define CG_CTRL_MAN_PHYCLK_USBHOST20_PHYCLOCK ((void *)(CMU_FSYS0_BASE + 0x1860)) |
| #define CG_CTRL_MAN_PHYCLK_USBHOST20_FREECLK ((void *)(CMU_FSYS0_BASE + 0x1864)) |
| #define CG_CTRL_MAN_PHYCLK_USBHOST20_CLK48MOHCI ((void *)(CMU_FSYS0_BASE + 0x1868)) |
| #define CG_CTRL_MAN_PHYCLK_UFS_RX_PWM_CLK ((void *)(CMU_FSYS0_BASE + 0x186C)) |
| #define CG_CTRL_MAN_PHYCLK_UFS_TX_PWM_CLK ((void *)(CMU_FSYS0_BASE + 0x1870)) |
| #define CG_CTRL_MAN_PHYCLK_UFS_REFCLK_OUT_SOC ((void *)(CMU_FSYS0_BASE + 0x1874)) |
| #define CG_CTRL_MAN_SCLK_USBHOST20_REF_CLK ((void *)(CMU_FSYS0_BASE + 0x1864)) |
| #define CG_CTRL_MAN_SCLK_PROMISE_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x1878)) |
| #define CG_CTRL_MAN_SCLK_USBHOST20PHY_REF_CLK ((void *)(CMU_FSYS0_BASE + 0x187C)) |
| #define CG_CTRL_MAN_SCLK_UFSUNIPRO_EMBEDDED_CFG ((void *)(CMU_FSYS0_BASE + 0x1880)) |
| #define CG_CTRL_STAT_ACLK_FSYS0_200_0 ((void *)(CMU_FSYS0_BASE + 0x1C00)) |
| #define CG_CTRL_STAT_ACLK_FSYS0_200_1 ((void *)(CMU_FSYS0_BASE + 0x1C04)) |
| #define CG_CTRL_STAT_ACLK_FSYS0_200_2 ((void *)(CMU_FSYS0_BASE + 0x1C08)) |
| #define CG_CTRL_STAT_ACLK_FSYS0_200_3 ((void *)(CMU_FSYS0_BASE + 0x1C0C)) |
| #define CG_CTRL_STAT_ACLK_FSYS0_200_4 ((void *)(CMU_FSYS0_BASE + 0x1C10)) |
| #define CG_CTRL_STAT_PCLK_HPM_APBIF_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x1C20)) |
| #define CG_CTRL_STAT_SCLK_USBDRD30_SUSPEND_CLK ((void *)(CMU_FSYS0_BASE + 0x1C40)) |
| #define CG_CTRL_STAT_SCLK_MMC0 ((void *)(CMU_FSYS0_BASE + 0x1C44)) |
| #define CG_CTRL_STAT_SCLK_UFSUNIPRO_EMBEDDED ((void *)(CMU_FSYS0_BASE + 0x1C48)) |
| #define CG_CTRL_STAT_SCLK_USBDRD30_REF_CLK ((void *)(CMU_FSYS0_BASE + 0x1C4C)) |
| #define CG_CTRL_STAT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK ((void *)(CMU_FSYS0_BASE + 0x1C50)) |
| #define CG_CTRL_STAT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK ((void *)(CMU_FSYS0_BASE + 0x1C54)) |
| #define CG_CTRL_STAT_PHYCLK_UFS_TX0_SYMBOL ((void *)(CMU_FSYS0_BASE + 0x1C58)) |
| #define CG_CTRL_STAT_PHYCLK_UFS_RX0_SYMBOL ((void *)(CMU_FSYS0_BASE + 0x1C5C)) |
| #define CG_CTRL_STAT_PHYCLK_USBHOST20_PHYCLOCK ((void *)(CMU_FSYS0_BASE + 0x1C60)) |
| #define CG_CTRL_STAT_PHYCLK_USBHOST20_FREECLK ((void *)(CMU_FSYS0_BASE + 0x1C64)) |
| #define CG_CTRL_STAT_PHYCLK_USBHOST20_CLK48MOHCI ((void *)(CMU_FSYS0_BASE + 0x1C68)) |
| #define CG_CTRL_STAT_PHYCLK_UFS_RX_PWM_CLK ((void *)(CMU_FSYS0_BASE + 0x1C6C)) |
| #define CG_CTRL_STAT_PHYCLK_UFS_TX_PWM_CLK ((void *)(CMU_FSYS0_BASE + 0x1C70)) |
| #define CG_CTRL_STAT_PHYCLK_UFS_REFCLK_OUT_SOC ((void *)(CMU_FSYS0_BASE + 0x1C74)) |
| #define CG_CTRL_STAT_SCLK_PROMISE_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x1C78)) |
| #define CG_CTRL_STAT_SCLK_USBHOST20PHY_REF_CLK ((void *)(CMU_FSYS0_BASE + 0x1C7C)) |
| #define CG_CTRL_STAT_SCLK_UFSUNIPRO_EMBEDDED_CFG ((void *)(CMU_FSYS0_BASE + 0x1C80)) |
| #define QCH_CTRL_AXI_LH_ASYNC_MI_TOP_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x2000)) |
| #define QCH_CTRL_AXI_LH_ASYNC_MI_ETR_USB_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x2004)) |
| #define QCH_CTRL_ETR_USB_FSYS0_ACLK ((void *)(CMU_FSYS0_BASE + 0x2008)) |
| #define QCH_CTRL_ETR_USB_FSYS0_PCLK ((void *)(CMU_FSYS0_BASE + 0x200C)) |
| #define QCH_CTRL_CMU_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x2010)) |
| #define QCH_CTRL_PMU_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x2014)) |
| #define QCH_CTRL_SYSREG_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x2018)) |
| #define QCH_CTRL_USBDRD30 ((void *)(CMU_FSYS0_BASE + 0x201C)) |
| #define QCH_CTRL_MMC0 ((void *)(CMU_FSYS0_BASE + 0x2020)) |
| #define QCH_CTRL_UFS_LINK_EMBEDDED ((void *)(CMU_FSYS0_BASE + 0x2024)) |
| #define QCH_CTRL_USBHOST20 ((void *)(CMU_FSYS0_BASE + 0x2028)) |
| #define QCH_CTRL_PDMA0 ((void *)(CMU_FSYS0_BASE + 0x202C)) |
| #define QCH_CTRL_PDMAS ((void *)(CMU_FSYS0_BASE + 0x2034)) |
| #define QCH_CTRL_PPMU_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x2038)) |
| #define QCH_CTRL_ACEL_LH_ASYNC_SI_TOP_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x203C)) |
| #define QCH_CTRL_USBDRD30_PHYCTRL ((void *)(CMU_FSYS0_BASE + 0x2040)) |
| #define QCH_CTRL_USBHOST20_PHYCTRL ((void *)(CMU_FSYS0_BASE + 0x2044)) |
| #define QSTATE_CTRL_USBDRD30 ((void *)(CMU_FSYS0_BASE + 0x2400)) |
| #define QSTATE_CTRL_UFS_LINK_EMBEDDED ((void *)(CMU_FSYS0_BASE + 0x2404)) |
| #define QSTATE_CTRL_USBHOST20 ((void *)(CMU_FSYS0_BASE + 0x2408)) |
| #define QSTATE_CTRL_USBHOST20_PHY ((void *)(CMU_FSYS0_BASE + 0x240C)) |
| #define QSTATE_CTRL_GPIO_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x2410)) |
| #define QSTATE_CTRL_HPM_APBIF_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x2414)) |
| #define QSTATE_CTRL_PROMISE_FSYS0 ((void *)(CMU_FSYS0_BASE + 0x2418)) |
| #define PCIE_PLL_LOCK ((void *)(CMU_FSYS1_BASE + 0x0000 + NSL)) |
| #define PCIE_PLL_CON0 ((void *)(CMU_FSYS1_BASE + 0x0100 + NSL)) |
| #define PCIE_PLL_CON1 ((void *)(CMU_FSYS1_BASE + 0x0104 + NSL)) |
| #define CLK_CON_MUX_ACLK_FSYS1_200_USER ((void *)(CMU_FSYS1_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS1_MMC2_USER ((void *)(CMU_FSYS1_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_USER ((void *)(CMU_FSYS1_BASE + 0x020C + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_CFG_USER ((void *)(CMU_FSYS1_BASE + 0x0210 + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS1_PCIE_PHY_USER ((void *)(CMU_FSYS1_BASE + 0x0214 + NSL)) |
| #define CLK_CON_MUX_PCIE_PLL ((void *)(CMU_FSYS1_BASE + 0x0218 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_USER ((void *)(CMU_FSYS1_BASE + 0x0220 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_USER ((void *)(CMU_FSYS1_BASE + 0x0224 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_PCIE_WIFI0_TX0_USER ((void *)(CMU_FSYS1_BASE + 0x0230 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_PCIE_WIFI0_RX0_USER ((void *)(CMU_FSYS1_BASE + 0x0234 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_PCIE_WIFI1_TX0_USER ((void *)(CMU_FSYS1_BASE + 0x0238 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_PCIE_WIFI1_RX0_USER ((void *)(CMU_FSYS1_BASE + 0x023C + NSL)) |
| #define CLK_CON_MUX_PHYCLK_PCIE_WIFI0_DIG_REFCLK_USER ((void *)(CMU_FSYS1_BASE + 0x0240 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_PCIE_WIFI1_DIG_REFCLK_USER ((void *)(CMU_FSYS1_BASE + 0x0244 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_UFS_LINK_SDCARD_RX_PWM_CLK_USER ((void *)(CMU_FSYS1_BASE + 0x0248 + NSL)) |
| #define CLK_CON_MUX_PHYCLK_UFS_LINK_SDCARD_TX_PWM_CLK_USER ((void *)(CMU_FSYS1_BASE + 0x024C + NSL)) |
| #define CLK_CON_MUX_PHYCLK_UFS_LINK_SDCARD_REFCLK_OUT_SOC_USER ((void *)(CMU_FSYS1_BASE + 0x0250 + NSL)) |
| #define CLK_CON_DIV_PCLK_COMBO_PHY_WIFI ((void *)(CMU_FSYS1_BASE + 0x0400 + NSL)) |
| #define CLK_STAT_MUX_ACLK_FSYS1_200_USER ((void *)(CMU_FSYS1_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS1_MMC2_USER ((void *)(CMU_FSYS1_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_USER ((void *)(CMU_FSYS1_BASE + 0x060C + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_CFG_USER ((void *)(CMU_FSYS1_BASE + 0x0610 + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS1_PCIE_PHY_USER ((void *)(CMU_FSYS1_BASE + 0x0614 + NSL)) |
| #define CLK_STAT_MUX_PCIE_PLL ((void *)(CMU_FSYS1_BASE + 0x0618 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_USER ((void *)(CMU_FSYS1_BASE + 0x0620 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_USER ((void *)(CMU_FSYS1_BASE + 0x0624 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_PCIE_WIFI0_TX0_USER ((void *)(CMU_FSYS1_BASE + 0x0630 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_PCIE_WIFI0_RX0_USER ((void *)(CMU_FSYS1_BASE + 0x0634 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_PCIE_WIFI1_TX0_USER ((void *)(CMU_FSYS1_BASE + 0x0638 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_PCIE_WIFI1_RX0_USER ((void *)(CMU_FSYS1_BASE + 0x063C + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_PCIE_WIFI0_DIG_REFCLK_USER ((void *)(CMU_FSYS1_BASE + 0x0640 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_PCIE_WIFI1_DIG_REFCLK_USER ((void *)(CMU_FSYS1_BASE + 0x0644 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_UFS_LINK_SDCARD_RX_PWM_CLK_USER ((void *)(CMU_FSYS1_BASE + 0x0648 + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_UFS_LINK_SDCARD_TX_PWM_CLK_USER ((void *)(CMU_FSYS1_BASE + 0x064C + NSL)) |
| #define CLK_STAT_MUX_PHYCLK_UFS_LINK_SDCARD_REFCLK_OUT_SOC_USER ((void *)(CMU_FSYS1_BASE + 0x0650 + NSL)) |
| #define CG_CTRL_VAL_ACLK_FSYS1_200 ((void *)(CMU_FSYS1_BASE + 0x0800)) |
| #define CG_CTRL_VAL_PCLK_HPM_APBIF_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x0820)) |
| #define CG_CTRL_VAL_PCLK_COMBO_PHY_WIFI ((void *)(CMU_FSYS1_BASE + 0x0824)) |
| #define CG_CTRL_VAL_SCLK_MMC2 ((void *)(CMU_FSYS1_BASE + 0x0840)) |
| #define CG_CTRL_VAL_SCLK_UFSUNIPRO_SDCARD ((void *)(CMU_FSYS1_BASE + 0x0844)) |
| #define CG_CTRL_VAL_SCLK_UFSUNIPRO_SDCARD_CFG ((void *)(CMU_FSYS1_BASE + 0x0848)) |
| #define CG_CTRL_VAL_SCLK_FSYS1_PCIE0_PHY ((void *)(CMU_FSYS1_BASE + 0x084C)) |
| #define CG_CTRL_VAL_SCLK_FSYS1_PCIE1_PHY ((void *)(CMU_FSYS1_BASE + 0x0850)) |
| #define CG_CTRL_VAL_SCLK_PCIE_LINK_WIFI0 ((void *)(CMU_FSYS1_BASE + 0x0854)) |
| #define CG_CTRL_VAL_SCLK_PCIE_LINK_WIFI1 ((void *)(CMU_FSYS1_BASE + 0x0858)) |
| #define CG_CTRL_VAL_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL ((void *)(CMU_FSYS1_BASE + 0x085C)) |
| #define CG_CTRL_VAL_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL ((void *)(CMU_FSYS1_BASE + 0x0860)) |
| #define CG_CTRL_VAL_PHYCLK_PCIE_WIFI0_TX0 ((void *)(CMU_FSYS1_BASE + 0x086C)) |
| #define CG_CTRL_VAL_PHYCLK_PCIE_WIFI0_RX0 ((void *)(CMU_FSYS1_BASE + 0x0870)) |
| #define CG_CTRL_VAL_PHYCLK_PCIE_WIFI1_TX0 ((void *)(CMU_FSYS1_BASE + 0x0874)) |
| #define CG_CTRL_VAL_PHYCLK_PCIE_WIFI1_RX0 ((void *)(CMU_FSYS1_BASE + 0x0878)) |
| #define CG_CTRL_VAL_PHYCLK_PCIE_WIFI0_DIG_REFCLK ((void *)(CMU_FSYS1_BASE + 0x087C)) |
| #define CG_CTRL_VAL_PHYCLK_PCIE_WIFI1_DIG_REFCLK ((void *)(CMU_FSYS1_BASE + 0x0880)) |
| #define CG_CTRL_VAL_PHYCLK_UFS_LINK_SDCARD_RX_PWM_CLK ((void *)(CMU_FSYS1_BASE + 0x0884)) |
| #define CG_CTRL_VAL_PHYCLK_UFS_LINK_SDCARD_TX_PWM_CLK ((void *)(CMU_FSYS1_BASE + 0x0888)) |
| #define CG_CTRL_VAL_PHYCLK_UFS_LINK_SDCARD_REFCLK_OUT_SOC ((void *)(CMU_FSYS1_BASE + 0x088C)) |
| #define CG_CTRL_VAL_SCLK_PROMISE_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x0890)) |
| #define CLKOUT_CMU_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x0C00)) |
| #define CLKOUT_CMU_FSYS1_DIV_STAT ((void *)(CMU_FSYS1_BASE + 0x0C04)) |
| #define FSYS1_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_FSYS1_BASE + 0x0D04)) |
| #define CMU_FSYS1_SPARE0 ((void *)(CMU_FSYS1_BASE + 0x0D08)) |
| #define CMU_FSYS1_SPARE1 ((void *)(CMU_FSYS1_BASE + 0x0D0C)) |
| #define CG_CTRL_MAN_ACLK_FSYS1_200 ((void *)(CMU_FSYS1_BASE + 0x1800)) |
| #define CG_CTRL_MAN_PCLK_HPM_APBIF_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x1820)) |
| #define CG_CTRL_MAN_PCLK_COMBO_PHY_WIFI ((void *)(CMU_FSYS1_BASE + 0x1824)) |
| #define CG_CTRL_MAN_SCLK_MMC2 ((void *)(CMU_FSYS1_BASE + 0x1840)) |
| #define CG_CTRL_MAN_SCLK_UFSUNIPRO_SDCARD ((void *)(CMU_FSYS1_BASE + 0x1844)) |
| #define CG_CTRL_MAN_SCLK_UFSUNIPRO_SDCARD_CFG ((void *)(CMU_FSYS1_BASE + 0x1848)) |
| #define CG_CTRL_MAN_SCLK_FSYS1_PCIE0_PHY ((void *)(CMU_FSYS1_BASE + 0x184C)) |
| #define CG_CTRL_MAN_SCLK_FSYS1_PCIE1_PHY ((void *)(CMU_FSYS1_BASE + 0x1850)) |
| #define CG_CTRL_MAN_SCLK_PCIE_LINK_WIFI0 ((void *)(CMU_FSYS1_BASE + 0x1854)) |
| #define CG_CTRL_MAN_SCLK_PCIE_LINK_WIFI1 ((void *)(CMU_FSYS1_BASE + 0x1858)) |
| #define CG_CTRL_MAN_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL ((void *)(CMU_FSYS1_BASE + 0x185C)) |
| #define CG_CTRL_MAN_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL ((void *)(CMU_FSYS1_BASE + 0x1860)) |
| #define CG_CTRL_MAN_PHYCLK_PCIE_WIFI0_TX0 ((void *)(CMU_FSYS1_BASE + 0x186C)) |
| #define CG_CTRL_MAN_PHYCLK_PCIE_WIFI0_RX0 ((void *)(CMU_FSYS1_BASE + 0x1870)) |
| #define CG_CTRL_MAN_PHYCLK_PCIE_WIFI1_TX0 ((void *)(CMU_FSYS1_BASE + 0x1874)) |
| #define CG_CTRL_MAN_PHYCLK_PCIE_WIFI1_RX0 ((void *)(CMU_FSYS1_BASE + 0x1878)) |
| #define CG_CTRL_MAN_PHYCLK_PCIE_WIFI0_DIG_REFCLK ((void *)(CMU_FSYS1_BASE + 0x187C)) |
| #define CG_CTRL_MAN_PHYCLK_PCIE_WIFI1_DIG_REFCLK ((void *)(CMU_FSYS1_BASE + 0x1880)) |
| #define CG_CTRL_MAN_PHYCLK_UFS_LINK_SDCARD_RX_PWM_CLK ((void *)(CMU_FSYS1_BASE + 0x1884)) |
| #define CG_CTRL_MAN_PHYCLK_UFS_LINK_SDCARD_TX_PWM_CLK ((void *)(CMU_FSYS1_BASE + 0x1888)) |
| #define CG_CTRL_MAN_PHYCLK_UFS_LINK_SDCARD_REFCLK_OUT_SOC ((void *)(CMU_FSYS1_BASE + 0x188C)) |
| #define CG_CTRL_MAN_SCLK_PROMISE_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x1890)) |
| #define CG_CTRL_STAT_ACLK_FSYS1_200_0 ((void *)(CMU_FSYS1_BASE + 0x1C00)) |
| #define CG_CTRL_STAT_ACLK_FSYS1_200_1 ((void *)(CMU_FSYS1_BASE + 0x1C04)) |
| #define CG_CTRL_STAT_ACLK_FSYS1_200_2 ((void *)(CMU_FSYS1_BASE + 0x1C08)) |
| #define CG_CTRL_STAT_ACLK_FSYS1_200_3 ((void *)(CMU_FSYS1_BASE + 0x1C0C)) |
| #define CG_CTRL_STAT_ACLK_FSYS1_200_4 ((void *)(CMU_FSYS1_BASE + 0x1C10)) |
| #define CG_CTRL_STAT_PCLK_HPM_APBIF_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x1C20)) |
| #define CG_CTRL_STAT_PCLK_COMBO_PHY_WIFI ((void *)(CMU_FSYS1_BASE + 0x1C24)) |
| #define CG_CTRL_STAT_SCLK_MMC2 ((void *)(CMU_FSYS1_BASE + 0x1C40)) |
| #define CG_CTRL_STAT_SCLK_UFSUNIPRO_SDCARD ((void *)(CMU_FSYS1_BASE + 0x1C44)) |
| #define CG_CTRL_STAT_SCLK_UFSUNIPRO_SDCARD_CFG ((void *)(CMU_FSYS1_BASE + 0x1C48)) |
| #define CG_CTRL_STAT_SCLK_FSYS1_PCIE0_PHY ((void *)(CMU_FSYS1_BASE + 0x1C4C)) |
| #define CG_CTRL_STAT_SCLK_FSYS1_PCIE1_PHY ((void *)(CMU_FSYS1_BASE + 0x1C50)) |
| #define CG_CTRL_STAT_SCLK_PCIE_LINK_WIFI0 ((void *)(CMU_FSYS1_BASE + 0x1C54)) |
| #define CG_CTRL_STAT_SCLK_PCIE_LINK_WIFI1 ((void *)(CMU_FSYS1_BASE + 0x1C58)) |
| #define CG_CTRL_STAT_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL ((void *)(CMU_FSYS1_BASE + 0x1C5C)) |
| #define CG_CTRL_STAT_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL ((void *)(CMU_FSYS1_BASE + 0x1C60)) |
| #define CG_CTRL_STAT_PHYCLK_PCIE_WIFI0_TX0 ((void *)(CMU_FSYS1_BASE + 0x1C6C)) |
| #define CG_CTRL_STAT_PHYCLK_PCIE_WIFI0_RX0 ((void *)(CMU_FSYS1_BASE + 0x1C70)) |
| #define CG_CTRL_STAT_PHYCLK_PCIE_WIFI1_TX0 ((void *)(CMU_FSYS1_BASE + 0x1C74)) |
| #define CG_CTRL_STAT_PHYCLK_PCIE_WIFI1_RX0 ((void *)(CMU_FSYS1_BASE + 0x1C78)) |
| #define CG_CTRL_STAT_PHYCLK_PCIE_WIFI0_DIG_REFCLK ((void *)(CMU_FSYS1_BASE + 0x1C7C)) |
| #define CG_CTRL_STAT_PHYCLK_PCIE_WIFI1_DIG_REFCLK ((void *)(CMU_FSYS1_BASE + 0x1C80)) |
| #define CG_CTRL_STAT_PHYCLK_UFS_LINK_SDCARD_RX_PWM_CLK ((void *)(CMU_FSYS1_BASE + 0x1C84)) |
| #define CG_CTRL_STAT_PHYCLK_UFS_LINK_SDCARD_TX_PWM_CLK ((void *)(CMU_FSYS1_BASE + 0x1C88)) |
| #define CG_CTRL_STAT_PHYCLK_UFS_LINK_SDCARD_REFCLK_OUT_SOC ((void *)(CMU_FSYS1_BASE + 0x1C8C)) |
| #define CG_CTRL_STAT_SCLK_PROMISE_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x1C90)) |
| #define QCH_CTRL_AXI_LH_ASYNC_MI_TOP_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x2000)) |
| #define QCH_CTRL_CMU_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x2004)) |
| #define QCH_CTRL_PMU_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x2008)) |
| #define QCH_CTRL_SYSREG_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x200C)) |
| #define QCH_CTRL_MMC2 ((void *)(CMU_FSYS1_BASE + 0x2010)) |
| #define QCH_CTRL_UFS_LINK_SDCARD ((void *)(CMU_FSYS1_BASE + 0x2014)) |
| #define QCH_CTRL_PPMU_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x2018)) |
| #define QCH_CTRL_ACEL_LH_ASYNC_SI_TOP_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x201C)) |
| #define QCH_CTRL_PCIE_RC_LINK_WIFI0_SLV ((void *)(CMU_FSYS1_BASE + 0x2020)) |
| #define QCH_CTRL_PCIE_RC_LINK_WIFI0_DBI ((void *)(CMU_FSYS1_BASE + 0x2024)) |
| #define QCH_CTRL_PCIE_RC_LINK_WIFI1_SLV ((void *)(CMU_FSYS1_BASE + 0x2028)) |
| #define QCH_CTRL_PCIE_RC_LINK_WIFI1_DBI ((void *)(CMU_FSYS1_BASE + 0x202C)) |
| #define QSTATE_CTRL_SROMC_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x241C)) |
| #define QSTATE_CTRL_GPIO_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x2420)) |
| #define QSTATE_CTRL_HPM_APBIF_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x2424)) |
| #define QSTATE_CTRL_PROMISE_FSYS1 ((void *)(CMU_FSYS1_BASE + 0x2428)) |
| #define QSTATE_CTRL_PCIE_RC_LINK_WIFI0 ((void *)(CMU_FSYS1_BASE + 0x242C)) |
| #define QSTATE_CTRL_PCIE_RC_LINK_WIFI1 ((void *)(CMU_FSYS1_BASE + 0x2430)) |
| #define QSTATE_CTRL_PCIE_PCS_WIFI0 ((void *)(CMU_FSYS1_BASE + 0x2434)) |
| #define QSTATE_CTRL_PCIE_PCS_WIFI1 ((void *)(CMU_FSYS1_BASE + 0x2438)) |
| #define QSTATE_CTRL_PCIE_PHY_FSYS1_WIFI0 ((void *)(CMU_FSYS1_BASE + 0x243C)) |
| #define QSTATE_CTRL_PCIE_PHY_FSYS1_WIFI1 ((void *)(CMU_FSYS1_BASE + 0x2440)) |
| #define QSTATE_CTRL_UFS_LINK_SDCARD ((void *)(CMU_FSYS1_BASE + 0x2444)) |
| #define CLK_CON_MUX_G3D_PLL_USER ((void *)(CMU_G3D_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_BUS_PLL_USER_G3D ((void *)(CMU_G3D_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_G3D ((void *)(CMU_G3D_BASE + 0x020C + NSL)) |
| #define CLK_CON_MUX_ACLK_G3D ((void *)(CMU_G3D_BASE + 0x0210 + NSL)) |
| #define CLK_CON_MUX_PCLK_G3D ((void *)(CMU_G3D_BASE + 0x0214 + NSL)) |
| #define CLK_CON_DIV_ACLK_G3D ((void *)(CMU_G3D_BASE + 0x0400 + NSL)) |
| #define CLK_CON_DIV_PCLK_G3D ((void *)(CMU_G3D_BASE + 0x0404 + NSL)) |
| #define CLK_CON_DIV_SCLK_HPM_G3D ((void *)(CMU_G3D_BASE + 0x0408 + NSL)) |
| #define CLK_CON_DIV_SCLK_ATE_G3D ((void *)(CMU_G3D_BASE + 0x040C + NSL)) |
| #define CLK_STAT_MUX_G3D_PLL_USER ((void *)(CMU_G3D_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_BUS_PLL_USER_G3D ((void *)(CMU_G3D_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_G3D ((void *)(CMU_G3D_BASE + 0x060C + NSL)) |
| #define CLK_STAT_MUX_ACLK_G3D ((void *)(CMU_G3D_BASE + 0x0610 + NSL)) |
| #define CLK_STAT_MUX_PCLK_G3D ((void *)(CMU_G3D_BASE + 0x0614 + NSL)) |
| #define CLK_ENABLE_ACLK_G3D ((void *)(CMU_G3D_BASE + 0x0800)) |
| #define CLK_ENABLE_ACLK_G3D_BUS ((void *)(CMU_G3D_BASE + 0x0804)) |
| #define CLK_ENABLE_PCLK_G3D ((void *)(CMU_G3D_BASE + 0x0900)) |
| #define CLK_ENABLE_SCLK_HPM_G3D ((void *)(CMU_G3D_BASE + 0x0A00)) |
| #define CLK_ENABLE_SCLK_ATE_G3D ((void *)(CMU_G3D_BASE + 0x0A04)) |
| #define CLKOUT_CMU_G3D ((void *)(CMU_G3D_BASE + 0x0C00)) |
| #define CLKOUT_CMU_G3D_DIV_STAT ((void *)(CMU_G3D_BASE + 0x0C04)) |
| #define CLK_ENABLE_PDN_G3D ((void *)(CMU_G3D_BASE + 0x0E00)) |
| #define G3D_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_G3D_BASE + 0x0F28)) |
| #define CLK_STOPCTRL_G3D ((void *)(CMU_G3D_BASE + 0x1000)) |
| #define CMU_G3D_SPARE0 ((void *)(CMU_G3D_BASE + 0x1100)) |
| #define CMU_G3D_SPARE1 ((void *)(CMU_G3D_BASE + 0x1104)) |
| #define CLK_CON_MUX_ACLK_IMEM_266_USER ((void *)(CMU_IMEM_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_ACLK_IMEM_200_USER ((void *)(CMU_IMEM_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_ACLK_IMEM_100_USER ((void *)(CMU_IMEM_BASE + 0x0208 + NSL)) |
| #define CLK_STAT_MUX_ACLK_IMEM_266_USER ((void *)(CMU_IMEM_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_ACLK_IMEM_200_USER ((void *)(CMU_IMEM_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_ACLK_IMEM_100_USER ((void *)(CMU_IMEM_BASE + 0x0608 + NSL)) |
| #define CG_CTRL_VAL_ACLK_IMEM_266 ((void *)(CMU_IMEM_BASE + 0x0800)) |
| #define CG_CTRL_VAL_ACLK_IMEM_266_SECURE_SSS ((void *)(CMU_IMEM_BASE + 0x0804)) |
| #define CG_CTRL_VAL_ACLK_IMEM_266_SECURE_RTIC ((void *)(CMU_IMEM_BASE + 0x0808)) |
| #define CG_CTRL_VAL_ACLK_IMEM_200 ((void *)(CMU_IMEM_BASE + 0x080C)) |
| #define CG_CTRL_VAL_PCLK_IMEM_200_SECURE_SSS ((void *)(CMU_IMEM_BASE + 0x0810)) |
| #define CG_CTRL_VAL_PCLK_IMEM_200_SECURE_RTIC ((void *)(CMU_IMEM_BASE + 0x0814)) |
| #define CG_CTRL_VAL_ACLK_IMEM_100 ((void *)(CMU_IMEM_BASE + 0x0818)) |
| #define CG_CTRL_VAL_ACLK_IMEM_100_SECURE_CM3_APM ((void *)(CMU_IMEM_BASE + 0x081C)) |
| #define CG_CTRL_VAL_ACLK_IMEM_100_SECURE_APM ((void *)(CMU_IMEM_BASE + 0x0820)) |
| #define CG_CTRL_VAL_ACLK_IMEM_100_SECURE_AHB_BUSMATRIX_APM ((void *)(CMU_IMEM_BASE + 0x0820)) |
| #define CG_CTRL_VAL_ACLK_IMEM_100_SECURE_ISRAMC_APM ((void *)(CMU_IMEM_BASE + 0x0824)) |
| #define CG_CTRL_VAL_ACLK_IMEM_100_SECURE_AHB2APB_BRIDGE_APM ((void *)(CMU_IMEM_BASE + 0x0828)) |
| #define CG_CTRL_VAL_ACLK_IMEM_100_SECURE_MAILBOX_APM ((void *)(CMU_IMEM_BASE + 0x082C)) |
| #define CG_CTRL_VAL_ACLK_IMEM_100_SECURE_TIMER_APM ((void *)(CMU_IMEM_BASE + 0x0830)) |
| #define CG_CTRL_VAL_ACLK_IMEM_100_SECURE_WDT_APM ((void *)(CMU_IMEM_BASE + 0x0834)) |
| #define CG_CTRL_VAL_ACLK_IMEM_100_SECURE_ISRAMC_SFR_APM ((void *)(CMU_IMEM_BASE + 0x0838)) |
| #define CG_CTRL_VAL_ACLK_IMEM_100_SECURE_SFR_APM ((void *)(CMU_IMEM_BASE + 0x083C)) |
| #define CLKOUT_CMU_IMEM ((void *)(CMU_IMEM_BASE + 0x0C00)) |
| #define CLKOUT_CMU_IMEM_DIV_STAT ((void *)(CMU_IMEM_BASE + 0x0C04)) |
| #define CMU_IMEM_SPARE0 ((void *)(CMU_IMEM_BASE + 0x0C08)) |
| #define CMU_IMEM_SPARE1 ((void *)(CMU_IMEM_BASE + 0x0C0C)) |
| #define IMEM_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_IMEM_BASE + 0x0D04)) |
| #define CG_CTRL_MAN_ACLK_IMEM_266 ((void *)(CMU_IMEM_BASE + 0x1800)) |
| #define CG_CTRL_MAN_ACLK_IMEM_266_SECURE_SSS ((void *)(CMU_IMEM_BASE + 0x1804)) |
| #define CG_CTRL_MAN_ACLK_IMEM_266_SECURE_RTIC ((void *)(CMU_IMEM_BASE + 0x1808)) |
| #define CG_CTRL_MAN_ACLK_IMEM_200 ((void *)(CMU_IMEM_BASE + 0x180C)) |
| #define CG_CTRL_MAN_PCLK_IMEM_200_SECURE_SSS ((void *)(CMU_IMEM_BASE + 0x1810)) |
| #define CG_CTRL_MAN_PCLK_IMEM_200_SECURE_RTIC ((void *)(CMU_IMEM_BASE + 0x1814)) |
| #define CG_CTRL_MAN_ACLK_IMEM_100 ((void *)(CMU_IMEM_BASE + 0x1818)) |
| #define CG_CTRL_MAN_ACLK_IMEM_100_SECURE_CM3_APM ((void *)(CMU_IMEM_BASE + 0x181C)) |
| #define CG_CTRL_MAN_ACLK_IMEM_100_SECURE_AHB_BUSMATRIX_APM ((void *)(CMU_IMEM_BASE + 0x1820)) |
| #define CG_CTRL_MAN_ACLK_IMEM_100_SECURE_ISRAMC_APM ((void *)(CMU_IMEM_BASE + 0x1824)) |
| #define CG_CTRL_MAN_ACLK_IMEM_100_SECURE_AHB2APB_BRIDGE_APM ((void *)(CMU_IMEM_BASE + 0x1828)) |
| #define CG_CTRL_MAN_ACLK_IMEM_100_SECURE_MAILBOX_APM ((void *)(CMU_IMEM_BASE + 0x182C)) |
| #define CG_CTRL_MAN_ACLK_IMEM_100_SECURE_TIMER_APM ((void *)(CMU_IMEM_BASE + 0x1830)) |
| #define CG_CTRL_MAN_ACLK_IMEM_100_SECURE_WDT_APM ((void *)(CMU_IMEM_BASE + 0x1834)) |
| #define CG_CTRL_MAN_ACLK_IMEM_100_SECURE_ISRAMC_SFR_APM ((void *)(CMU_IMEM_BASE + 0x1838)) |
| #define CG_CTRL_MAN_ACLK_IMEM_100_SECURE_SFR_APM ((void *)(CMU_IMEM_BASE + 0x183C)) |
| #define CG_CTRL_STAT_ACLK_IMEM_266_0 ((void *)(CMU_IMEM_BASE + 0x1C00)) |
| #define CG_CTRL_STAT_ACLK_IMEM_266_1 ((void *)(CMU_IMEM_BASE + 0x1C04)) |
| #define CG_CTRL_STAT_ACLK_IMEM_266_SECURE_SSS ((void *)(CMU_IMEM_BASE + 0x1C08)) |
| #define CG_CTRL_STAT_ACLK_IMEM_266_SECURE_RTIC ((void *)(CMU_IMEM_BASE + 0x1C0C)) |
| #define CG_CTRL_STAT_ACLK_IMEM_200_0 ((void *)(CMU_IMEM_BASE + 0x1C10)) |
| #define CG_CTRL_STAT_ACLK_IMEM_200_1 ((void *)(CMU_IMEM_BASE + 0x1C14)) |
| #define CG_CTRL_STAT_ACLK_IMEM_200_2 ((void *)(CMU_IMEM_BASE + 0x1C18)) |
| #define CG_CTRL_STAT_PCLK_IMEM_200_SECURE_SSS ((void *)(CMU_IMEM_BASE + 0x1C1C)) |
| #define CG_CTRL_STAT_PCLK_IMEM_200_SECURE_RTIC ((void *)(CMU_IMEM_BASE + 0x1C20)) |
| #define CG_CTRL_STAT_ACLK_IMEM_100 ((void *)(CMU_IMEM_BASE + 0x1C24)) |
| #define CG_CTRL_STAT_ACLK_IMEM_100_SECURE_CM3_APM ((void *)(CMU_IMEM_BASE + 0x1C28)) |
| #define CG_CTRL_STAT_ACLK_IMEM_100_SECURE_AHB_BUSMATRIX_APM ((void *)(CMU_IMEM_BASE + 0x1C2C)) |
| #define CG_CTRL_STAT_ACLK_IMEM_100_SECURE_ISRAMC_APM ((void *)(CMU_IMEM_BASE + 0x1C30)) |
| #define CG_CTRL_STAT_ACLK_IMEM_100_SECURE_AHB2APB_BRIDGE_APM ((void *)(CMU_IMEM_BASE + 0x1C34)) |
| #define CG_CTRL_STAT_ACLK_IMEM_100_SECURE_MAILBOX_APM ((void *)(CMU_IMEM_BASE + 0x1C38)) |
| #define CG_CTRL_STAT_ACLK_IMEM_100_SECURE_TIMER_APM ((void *)(CMU_IMEM_BASE + 0x1C3C)) |
| #define CG_CTRL_STAT_ACLK_IMEM_100_SECURE_WDT_APM ((void *)(CMU_IMEM_BASE + 0x1C40)) |
| #define CG_CTRL_STAT_ACLK_IMEM_100_SECURE_ISRAMC_SFR_APM ((void *)(CMU_IMEM_BASE + 0x1C44)) |
| #define CG_CTRL_STAT_ACLK_IMEM_100_SECURE_SFR_APM ((void *)(CMU_IMEM_BASE + 0x1C48)) |
| #define QCH_CTRL_AXI_LH_ASYNC_MI_IMEM ((void *)(CMU_IMEM_BASE + 0x2000)) |
| #define QCH_CTRL_SSS ((void *)(CMU_IMEM_BASE + 0x2004)) |
| #define QCH_CTRL_RTIC ((void *)(CMU_IMEM_BASE + 0x2008)) |
| #define QCH_CTRL_INT_MEM ((void *)(CMU_IMEM_BASE + 0x200C)) |
| #define QCH_CTRL_INT_MEM_ALV ((void *)(CMU_IMEM_BASE + 0x2010)) |
| #define QCH_CTRL_MCOMP ((void *)(CMU_IMEM_BASE + 0x2014)) |
| #define QCH_CTRL_CMU_IMEM ((void *)(CMU_IMEM_BASE + 0x2018)) |
| #define QCH_CTRL_PMU_IMEM ((void *)(CMU_IMEM_BASE + 0x201C)) |
| #define QCH_CTRL_SYSREG_IMEM ((void *)(CMU_IMEM_BASE + 0x2020)) |
| #define QCH_CTRL_PPMU_SSSX ((void *)(CMU_IMEM_BASE + 0x2024)) |
| #define QCH_CTRL_LH_ASYNC_SI_IMEM ((void *)(CMU_IMEM_BASE + 0x2028)) |
| #define QCH_CTRL_APM ((void *)(CMU_IMEM_BASE + 0x202C)) |
| #define QCH_CTRL_CM3_APM ((void *)(CMU_IMEM_BASE + 0x2030)) |
| #define QSTATE_CTRL_GIC ((void *)(CMU_IMEM_BASE + 0x2400)) |
| #define QSTATE_CTRL_APM ((void *)(CMU_IMEM_BASE + 0x2404)) |
| #define QSTATE_CTRL_ASYNCAHBM_SSS_ATLAS ((void *)(CMU_IMEM_BASE + 0x2408)) |
| #define CLK_CON_MUX_ACLK_ISP0_528_USER ((void *)(CMU_ISP0_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_ACLK_ISP0_TPU_400_USER ((void *)(CMU_ISP0_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_ACLK_ISP0_TREX_528_USER ((void *)(CMU_ISP0_BASE + 0x0208 + NSL)) |
| #define CLK_CON_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_USER ((void *)(CMU_ISP0_BASE + 0x020C + NSL)) |
| #define CLK_CON_DIV_PCLK_ISP0 ((void *)(CMU_ISP0_BASE + 0x0400 + NSL)) |
| #define CLK_CON_DIV_PCLK_ISP0_TPU ((void *)(CMU_ISP0_BASE + 0x0404 + NSL)) |
| #define CLK_CON_DIV_PCLK_ISP0_TREX_264 ((void *)(CMU_ISP0_BASE + 0x0408 + NSL)) |
| #define CLK_CON_DIV_PCLK_ISP0_TREX_132 ((void *)(CMU_ISP0_BASE + 0x040C + NSL)) |
| #define CLK_STAT_MUX_ACLK_ISP0_528_USER ((void *)(CMU_ISP0_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_ACLK_ISP0_TPU_400_USER ((void *)(CMU_ISP0_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_ACLK_ISP0_TREX_528_USER ((void *)(CMU_ISP0_BASE + 0x0608 + NSL)) |
| #define CLK_STAT_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_USER ((void *)(CMU_ISP0_BASE + 0x060C + NSL)) |
| #define CLK_ENABLE_ACLK_ISP0 ((void *)(CMU_ISP0_BASE + 0x0800)) |
| #define CLK_ENABLE_PCLK_ISP0 ((void *)(CMU_ISP0_BASE + 0x0808)) |
| #define CLK_ENABLE_ACLK_ISP0_TPU ((void *)(CMU_ISP0_BASE + 0x080C)) |
| #define CLK_ENABLE_PCLK_ISP0_TPU ((void *)(CMU_ISP0_BASE + 0x0814)) |
| #define CLK_ENABLE_ACLK_ISP0_TREX ((void *)(CMU_ISP0_BASE + 0x0818)) |
| #define CLK_ENABLE_PCLK_TREX_264 ((void *)(CMU_ISP0_BASE + 0x081C)) |
| #define CLK_ENABLE_PCLK_HPM_APBIF_ISP0 ((void *)(CMU_ISP0_BASE + 0x0820)) |
| #define CLK_ENABLE_PCLK_TREX_132 ((void *)(CMU_ISP0_BASE + 0x0824)) |
| #define CLK_ENABLE_SCLK_PROMISE_ISP0 ((void *)(CMU_ISP0_BASE + 0x0828)) |
| #define CLK_ENABLE_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D ((void *)(CMU_ISP0_BASE + 0x082C)) |
| #define CLKOUT_CMU_ISP0 ((void *)(CMU_ISP0_BASE + 0x0D00)) |
| #define CLKOUT_CMU_ISP0_DIV_STAT ((void *)(CMU_ISP0_BASE + 0x0D04)) |
| #define CMU_ISP0_SPARE0 ((void *)(CMU_ISP0_BASE + 0x0D08)) |
| #define CMU_ISP0_SPARE1 ((void *)(CMU_ISP0_BASE + 0x0D0C)) |
| #define CLK_ENABLE_PDN_ISP0 ((void *)(CMU_ISP0_BASE + 0x0E00)) |
| #define ISP0_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_ISP0_BASE + 0x0E04)) |
| #define CLK_ENABLE_ACLK_ISP0_LOCAL ((void *)(CMU_ISP0_LOCAL_BASE + 0x0800)) |
| #define CLK_ENABLE_PCLK_ISP0_LOCAL ((void *)(CMU_ISP0_LOCAL_BASE + 0x0808)) |
| #define CLK_ENABLE_ACLK_ISP0_TPU_LOCAL ((void *)(CMU_ISP0_LOCAL_BASE + 0x080C)) |
| #define CLK_ENABLE_PCLK_ISP0_TPU_LOCAL ((void *)(CMU_ISP0_LOCAL_BASE + 0x0814)) |
| #define CLK_ENABLE_ACLK_ISP0_TREX_LOCAL ((void *)(CMU_ISP0_LOCAL_BASE + 0x0818)) |
| #define CLK_ENABLE_PCLK_TREX_132_LOCAL ((void *)(CMU_ISP0_LOCAL_BASE + 0x0824)) |
| #define CLK_ENABLE_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_LOCAL ((void *)(CMU_ISP0_LOCAL_BASE + 0x0828)) |
| #define CLK_CON_MUX_ACLK_ISP1_468_USER ((void *)(CMU_ISP1_BASE + 0x0200 + NSL)) |
| #define CLK_CON_DIV_PCLK_ISP1_234 ((void *)(CMU_ISP1_BASE + 0x0400 + NSL)) |
| #define CLK_STAT_MUX_ACLK_ISP1_468_USER ((void *)(CMU_ISP1_BASE + 0x0600 + NSL)) |
| #define CLK_ENABLE_ACLK_ISP1 ((void *)(CMU_ISP1_BASE + 0x0800)) |
| #define CLK_ENABLE_PCLK_ISP1_234 ((void *)(CMU_ISP1_BASE + 0x0808)) |
| #define CLK_ENABLE_PCLK_HPM_APBIF_ISP1 ((void *)(CMU_ISP1_BASE + 0x080C)) |
| #define CLK_ENABLE_SCLK_PROMISE_ISP1 ((void *)(CMU_ISP1_BASE + 0x0810)) |
| #define CLKOUT_CMU_ISP1 ((void *)(CMU_ISP1_BASE + 0x0D00)) |
| #define CLKOUT_CMU_ISP1_DIV_STAT ((void *)(CMU_ISP1_BASE + 0x0D04)) |
| #define CMU_ISP1_SPARE0 ((void *)(CMU_ISP1_BASE + 0x0D08)) |
| #define CMU_ISP1_SPARE1 ((void *)(CMU_ISP1_BASE + 0x0D0C)) |
| #define CLK_ENABLE_PDN_ISP1 ((void *)(CMU_ISP1_BASE + 0x0E00)) |
| #define ISP1_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_ISP1_BASE + 0x0E04)) |
| #define CLK_ENABLE_ACLK_ISP1_LOCAL ((void *)(CMU_ISP1_LOCAL_BASE + 0x0800)) |
| #define CLK_ENABLE_PCLK_ISP1_234_LOCAL ((void *)(CMU_ISP1_LOCAL_BASE + 0x0808)) |
| #define CLK_CON_MUX_ACLK_MFC_600_USER ((void *)(CMU_MFC_BASE + 0x0200 + NSL)) |
| #define CLK_CON_DIV_PCLK_MFC_150 ((void *)(CMU_MFC_BASE + 0x0400 + NSL)) |
| #define CLK_STAT_MUX_ACLK_MFC_600_USER ((void *)(CMU_MFC_BASE + 0x0600 + NSL)) |
| #define CG_CTRL_VAL_ACLK_MFC_600 ((void *)(CMU_MFC_BASE + 0x0800)) |
| #define CG_CTRL_VAL_ACLK_MFC_600_SECURE_SFW_MFC_0 ((void *)(CMU_MFC_BASE + 0x0804)) |
| #define CG_CTRL_VAL_ACLK_MFC_600_SECURE_SFW_MFC_1 ((void *)(CMU_MFC_BASE + 0x0808)) |
| #define CG_CTRL_VAL_PCLK_MFC_150 ((void *)(CMU_MFC_BASE + 0x0820)) |
| #define CG_CTRL_VAL_PCLK_MFC_150_HPM_APBIF_MFC ((void *)(CMU_MFC_BASE + 0x0824)) |
| #define CG_CTRL_VAL_PCLK_MFC_150_SECURE_SFW_MFC_0 ((void *)(CMU_MFC_BASE + 0x0828)) |
| #define CG_CTRL_VAL_PCLK_MFC_150_SECURE_SFW_MFC_1 ((void *)(CMU_MFC_BASE + 0x082C)) |
| #define CG_CTRL_VAL_SCLK_MFC_PROMISE ((void *)(CMU_MFC_BASE + 0x0840)) |
| #define CLKOUT_CMU_MFC ((void *)(CMU_MFC_BASE + 0x0C00)) |
| #define CLKOUT_CMU_MFC_DIV_STAT ((void *)(CMU_MFC_BASE + 0x0C04)) |
| #define MFC_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_MFC_BASE + 0x0D04)) |
| #define CMU_MFC_SPARE0 ((void *)(CMU_MFC_BASE + 0x0D08)) |
| #define CMU_MFC_SPARE1 ((void *)(CMU_MFC_BASE + 0x0D0C)) |
| #define CG_CTRL_MAN_ACLK_MFC_600 ((void *)(CMU_MFC_BASE + 0x1800)) |
| #define CG_CTRL_MAN_ACLK_MFC_600_SECURE_SFW_MFC_0 ((void *)(CMU_MFC_BASE + 0x1804)) |
| #define CG_CTRL_MAN_ACLK_MFC_600_SECURE_SFW_MFC_1 ((void *)(CMU_MFC_BASE + 0x1808)) |
| #define CG_CTRL_MAN_PCLK_MFC_150 ((void *)(CMU_MFC_BASE + 0x1820)) |
| #define CG_CTRL_MAN_PCLK_MFC_150_HPM_APBIF_MFC ((void *)(CMU_MFC_BASE + 0x1824)) |
| #define CG_CTRL_MAN_PCLK_MFC_150_SECURE_SFW_MFC_0 ((void *)(CMU_MFC_BASE + 0x1828)) |
| #define CG_CTRL_MAN_PCLK_MFC_150_SECURE_SFW_MFC_1 ((void *)(CMU_MFC_BASE + 0x182C)) |
| #define CG_CTRL_MAN_SCLK_MFC_PROMISE ((void *)(CMU_MFC_BASE + 0x1840)) |
| #define CG_CTRL_STAT_ACLK_MFC_600 ((void *)(CMU_MFC_BASE + 0x1C00)) |
| #define CG_CTRL_STAT_ACLK_MFC_600_SECURE_SFW_MFC_0 ((void *)(CMU_MFC_BASE + 0x1C04)) |
| #define CG_CTRL_STAT_ACLK_MFC_600_SECURE_SFW_MFC_1 ((void *)(CMU_MFC_BASE + 0x1C08)) |
| #define CG_CTRL_STAT_PCLK_MFC_150_0 ((void *)(CMU_MFC_BASE + 0x1C20)) |
| #define CG_CTRL_STAT_PCLK_MFC_150_1 ((void *)(CMU_MFC_BASE + 0x1C24)) |
| #define CG_CTRL_STAT_PCLK_MFC_150_HPM_APBIF_MFC ((void *)(CMU_MFC_BASE + 0x1C28)) |
| #define CG_CTRL_STAT_PCLK_MFC_150_SECURE_SFW_MFC_0 ((void *)(CMU_MFC_BASE + 0x1C2C)) |
| #define CG_CTRL_STAT_PCLK_MFC_150_SECURE_SFW_MFC_1 ((void *)(CMU_MFC_BASE + 0x1C30)) |
| #define CG_CTRL_STAT_SCLK_MFC_PROMISE ((void *)(CMU_MFC_BASE + 0x1C40)) |
| #define QCH_CTRL_MFC ((void *)(CMU_MFC_BASE + 0x2000)) |
| #define QCH_CTRL_LH_M_MFC ((void *)(CMU_MFC_BASE + 0x2004)) |
| #define QCH_CTRL_CMU_MFC ((void *)(CMU_MFC_BASE + 0x2008)) |
| #define QCH_CTRL_PMU_MFC ((void *)(CMU_MFC_BASE + 0x200C)) |
| #define QCH_CTRL_SYSREG_MFC ((void *)(CMU_MFC_BASE + 0x2010)) |
| #define QCH_CTRL_PPMU_MFC_0 ((void *)(CMU_MFC_BASE + 0x2014)) |
| #define QCH_CTRL_PPMU_MFC_1 ((void *)(CMU_MFC_BASE + 0x2018)) |
| #define QCH_CTRL_SFW_MFC_0 ((void *)(CMU_MFC_BASE + 0x201C)) |
| #define QCH_CTRL_SFW_MFC_1 ((void *)(CMU_MFC_BASE + 0x2020)) |
| #define QCH_CTRL_SMMU_MFC_0 ((void *)(CMU_MFC_BASE + 0x2024)) |
| #define QCH_CTRL_SMMU_MFC_1 ((void *)(CMU_MFC_BASE + 0x2028)) |
| #define QCH_CTRL_LH_S_MFC_0 ((void *)(CMU_MFC_BASE + 0x202C)) |
| #define QCH_CTRL_LH_S_MFC_1 ((void *)(CMU_MFC_BASE + 0x2030)) |
| #define QSTATE_CTRL_HPM_APBIF_MFC ((void *)(CMU_MFC_BASE + 0x2404)) |
| #define QSTATE_CTRL_PROMISE_MFC ((void *)(CMU_MFC_BASE + 0x2408)) |
| #define MIF0_PLL_LOCK ((void *)(CMU_MIF0_BASE + 0x0000 + NSL)) |
| #define MIF0_PLL_CON0 ((void *)(CMU_MIF0_BASE + 0x0100 + NSL)) |
| #define MIF0_PLL_CON1 ((void *)(CMU_MIF0_BASE + 0x0104 + NSL)) |
| #define MIF0_PLL_FREQ_DET ((void *)(CMU_MIF0_BASE + 0x010C + NSL)) |
| #define CLK_CON_MUX_MIF0_PLL ((void *)(CMU_MIF0_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_BUS_PLL_USER_MIF0 ((void *)(CMU_MIF0_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_ACLK_MIF0_PLL ((void *)(CMU_MIF0_BASE + 0x0208 + NSL)) |
| #define CLK_CON_MUX_PCLK_MIF0 ((void *)(CMU_MIF0_BASE + 0x0210 + NSL)) |
| #define CLK_CON_MUX_SCLK_HPM_MIF0 ((void *)(CMU_MIF0_BASE + 0x0214 + NSL)) |
| #define CLK_CON_MUX_PCLK_SMC_MIF0 ((void *)(CMU_MIF0_BASE + 0x0218 + NSL)) |
| #define CLK_CON_DIV_PCLK_MIF0 ((void *)(CMU_MIF0_BASE + 0x0400 + NSL)) |
| #define CLK_CON_DIV_PCLK_SMC_MIF0 ((void *)(CMU_MIF0_BASE + 0x0404 + NSL)) |
| #define CLK_CON_DIV_SCLK_HPM_MIF0 ((void *)(CMU_MIF0_BASE + 0x0408 + NSL)) |
| #define CLK_STAT_MUX_MIF0_PLL ((void *)(CMU_MIF0_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_BUS_PLL_USER_MIF0 ((void *)(CMU_MIF0_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_ACLK_MIF0_PLL ((void *)(CMU_MIF0_BASE + 0x0608 + NSL)) |
| #define CLK_STAT_MUX_PCLK_MIF0 ((void *)(CMU_MIF0_BASE + 0x0610 + NSL)) |
| #define CLK_STAT_MUX_SCLK_HPM_MIF0 ((void *)(CMU_MIF0_BASE + 0x0614 + NSL)) |
| #define CLK_STAT_MUX_PCLK_SMC_MIF0 ((void *)(CMU_MIF0_BASE + 0x0618 + NSL)) |
| #define CLK_ENABLE_ACLK_MIF0 ((void *)(CMU_MIF0_BASE + 0x0800)) |
| #define CLK_ENABLE_PCLK_MIF0 ((void *)(CMU_MIF0_BASE + 0x0900)) |
| #define CLK_ENABLE_ACLK_MIF0_SECURE_DREX_TZ ((void *)(CMU_MIF0_BASE + 0x0904)) |
| #define CLK_ENABLE_SCLK_HPM_MIF0 ((void *)(CMU_MIF0_BASE + 0x0A00)) |
| #define CLK_ENABLE_SCLK_RCLK_DREX_MIF0 ((void *)(CMU_MIF0_BASE + 0x0A04)) |
| #define CG_CTRL_VAL_PCLK_MIF0 ((void *)(CMU_MIF0_BASE + 0x0900)) |
| #define CG_CTRL_VAL_SCLK_HPM_MIF0 ((void *)(CMU_MIF0_BASE + 0x0A00)) |
| #define CG_CTRL_VAL_SCLK_RCLK_DREX0 ((void *)(CMU_MIF0_BASE + 0x0A04)) |
| #define CG_CTRL_VAL_DDRPHY0 ((void *)(CMU_MIF0_BASE + 0x0A08)) |
| #define CLKOUT_CMU_MIF0 ((void *)(CMU_MIF0_BASE + 0x0C00)) |
| #define CLKOUT_CMU_MIF0_DIV_STAT ((void *)(CMU_MIF0_BASE + 0x0C04)) |
| #define CLK_ENABLE_PDN_MIF0 ((void *)(CMU_MIF0_BASE + 0x0E00)) |
| #define MIF0_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_MIF0_BASE + 0x0F28)) |
| #define PSCDC_CTRL_MIF0 ((void *)(CMU_MIF0_BASE + 0x1000)) |
| #define CLK_STOPCTRL_MIF0 ((void *)(CMU_MIF0_BASE + 0x1004)) |
| #define CMU_MIF0_SPARE0 ((void *)(CMU_MIF0_BASE + 0x1100)) |
| #define CMU_MIF0_SPARE1 ((void *)(CMU_MIF0_BASE + 0x1104)) |
| #define CG_CTRL_MAN_PCLK_MIF0 ((void *)(CMU_MIF0_BASE + 0x1900)) |
| #define CG_CTRL_MAN_SCLK_HPM_MIF0 ((void *)(CMU_MIF0_BASE + 0x1A00)) |
| #define CG_CTRL_MAN_SCLK_RCLK_DREX0 ((void *)(CMU_MIF0_BASE + 0x1A04)) |
| #define CG_CTRL_MAN_DDRPHY0 ((void *)(CMU_MIF0_BASE + 0x1A08)) |
| #define CG_CTRL_STAT_PCLK_MIF0_0 ((void *)(CMU_MIF0_BASE + 0x1D00)) |
| #define CG_CTRL_STAT_PCLK_MIF0_1 ((void *)(CMU_MIF0_BASE + 0x1D04)) |
| #define CG_CTRL_STAT_SCLK_HPM_MIF0 ((void *)(CMU_MIF0_BASE + 0x1E00)) |
| #define CG_CTRL_STAT_SCLK_RCLK_DREX0 ((void *)(CMU_MIF0_BASE + 0x1E04)) |
| #define CG_CTRL_STAT_DDRPHY0 ((void *)(CMU_MIF0_BASE + 0x1E08)) |
| #define QCH_CTRL_LH_AXI_P_MIF0 ((void *)(CMU_MIF0_BASE + 0x2000)) |
| #define QCH_CTRL_PMU_MIF0 ((void *)(CMU_MIF0_BASE + 0x2004)) |
| #define QCH_CTRL_SYSREG_MIF0 ((void *)(CMU_MIF0_BASE + 0x2008)) |
| #define QCH_CTRL_CMU_MIF0 ((void *)(CMU_MIF0_BASE + 0x200C)) |
| #define QCH_CTRL_SMC_MIF0 ((void *)(CMU_MIF0_BASE + 0x2010)) |
| #define QSTATE_CTRL_PROMISE_MIF0 ((void *)(CMU_MIF0_BASE + 0x2400)) |
| #define QSTATE_CTRL_RCLK_DREX0 ((void *)(CMU_MIF0_BASE + 0x2404)) |
| #define MIF1_PLL_LOCK ((void *)(CMU_MIF1_BASE + 0x0000 + NSL)) |
| #define MIF1_PLL_CON0 ((void *)(CMU_MIF1_BASE + 0x0100 + NSL)) |
| #define MIF1_PLL_CON1 ((void *)(CMU_MIF1_BASE + 0x0104 + NSL)) |
| #define MIF1_PLL_FREQ_DET ((void *)(CMU_MIF1_BASE + 0x010C + NSL)) |
| #define CLK_CON_MUX_MIF1_PLL ((void *)(CMU_MIF1_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_BUS_PLL_USER_MIF1 ((void *)(CMU_MIF1_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_ACLK_MIF1_PLL ((void *)(CMU_MIF1_BASE + 0x0208 + NSL)) |
| #define CLK_CON_MUX_PCLK_MIF1 ((void *)(CMU_MIF1_BASE + 0x0210 + NSL)) |
| #define CLK_CON_MUX_SCLK_HPM_MIF1 ((void *)(CMU_MIF1_BASE + 0x0214 + NSL)) |
| #define CLK_CON_MUX_PCLK_SMC_MIF1 ((void *)(CMU_MIF1_BASE + 0x0218 + NSL)) |
| #define CLK_CON_DIV_PCLK_MIF1 ((void *)(CMU_MIF1_BASE + 0x0400 + NSL)) |
| #define CLK_CON_DIV_PCLK_SMC_MIF1 ((void *)(CMU_MIF1_BASE + 0x0404 + NSL)) |
| #define CLK_CON_DIV_SCLK_HPM_MIF1 ((void *)(CMU_MIF1_BASE + 0x0408 + NSL)) |
| #define CLK_STAT_MUX_MIF1_PLL ((void *)(CMU_MIF1_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_BUS_PLL_USER_MIF1 ((void *)(CMU_MIF1_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_ACLK_MIF1_PLL ((void *)(CMU_MIF1_BASE + 0x0608 + NSL)) |
| #define CLK_STAT_MUX_PCLK_MIF1 ((void *)(CMU_MIF1_BASE + 0x0610 + NSL)) |
| #define CLK_STAT_MUX_SCLK_HPM_MIF1 ((void *)(CMU_MIF1_BASE + 0x0614 + NSL)) |
| #define CLK_STAT_MUX_PCLK_SMC_MIF1 ((void *)(CMU_MIF1_BASE + 0x0618 + NSL)) |
| #define CLK_ENABLE_ACLK_MIF1 ((void *)(CMU_MIF1_BASE + 0x0800)) |
| #define CLK_ENABLE_PCLK_MIF1 ((void *)(CMU_MIF1_BASE + 0x0900)) |
| #define CLK_ENABLE_ACLK_MIF1_SECURE_DREX_TZ ((void *)(CMU_MIF1_BASE + 0x0904)) |
| #define CLK_ENABLE_SCLK_HPM_MIF1 ((void *)(CMU_MIF1_BASE + 0x0A00)) |
| #define CLK_ENABLE_SCLK_RCLK_DREX_MIF1 ((void *)(CMU_MIF1_BASE + 0x0A04)) |
| #define CG_CTRL_VAL_PCLK_MIF1 ((void *)(CMU_MIF1_BASE + 0x0900)) |
| #define CG_CTRL_VAL_SCLK_HPM_MIF1 ((void *)(CMU_MIF1_BASE + 0x0A00)) |
| #define CG_CTRL_VAL_SCLK_RCLK_DREX1 ((void *)(CMU_MIF1_BASE + 0x0A04)) |
| #define CG_CTRL_VAL_DDRPHY1 ((void *)(CMU_MIF1_BASE + 0x0A08)) |
| #define CLKOUT_CMU_MIF1 ((void *)(CMU_MIF1_BASE + 0x0C00)) |
| #define CLKOUT_CMU_MIF1_DIV_STAT ((void *)(CMU_MIF1_BASE + 0x0C04)) |
| #define CLK_ENABLE_PDN_MIF1 ((void *)(CMU_MIF1_BASE + 0x0E00)) |
| #define MIF1_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_MIF1_BASE + 0x0F28)) |
| #define PSCDC_CTRL_MIF1 ((void *)(CMU_MIF1_BASE + 0x1000)) |
| #define CLK_STOPCTRL_MIF1 ((void *)(CMU_MIF1_BASE + 0x1004)) |
| #define CMU_MIF1_SPARE0 ((void *)(CMU_MIF1_BASE + 0x1100)) |
| #define CMU_MIF1_SPARE1 ((void *)(CMU_MIF1_BASE + 0x1104)) |
| #define CG_CTRL_MAN_PCLK_MIF1 ((void *)(CMU_MIF1_BASE + 0x1900)) |
| #define CG_CTRL_MAN_SCLK_HPM_MIF1 ((void *)(CMU_MIF1_BASE + 0x1A00)) |
| #define CG_CTRL_MAN_SCLK_RCLK_DREX1 ((void *)(CMU_MIF1_BASE + 0x1A04)) |
| #define CG_CTRL_MAN_DDRPHY1 ((void *)(CMU_MIF1_BASE + 0x1A08)) |
| #define CG_CTRL_STAT_PCLK_MIF1_0 ((void *)(CMU_MIF1_BASE + 0x1D00)) |
| #define CG_CTRL_STAT_PCLK_MIF1_1 ((void *)(CMU_MIF1_BASE + 0x1D04)) |
| #define CG_CTRL_STAT_SCLK_HPM_MIF1 ((void *)(CMU_MIF1_BASE + 0x1E00)) |
| #define CG_CTRL_STAT_SCLK_RCLK_DREX1 ((void *)(CMU_MIF1_BASE + 0x1E04)) |
| #define CG_CTRL_STAT_DDRPHY1 ((void *)(CMU_MIF1_BASE + 0x1E08)) |
| #define QCH_CTRL_LH_AXI_P_MIF1 ((void *)(CMU_MIF1_BASE + 0x2000)) |
| #define QCH_CTRL_PMU_MIF1 ((void *)(CMU_MIF1_BASE + 0x2004)) |
| #define QCH_CTRL_SYSREG_MIF1 ((void *)(CMU_MIF1_BASE + 0x2008)) |
| #define QCH_CTRL_CMU_MIF1 ((void *)(CMU_MIF1_BASE + 0x200C)) |
| #define QCH_CTRL_SMC_MIF1 ((void *)(CMU_MIF1_BASE + 0x2010)) |
| #define QSTATE_CTRL_PROMISE_MIF1 ((void *)(CMU_MIF1_BASE + 0x2400)) |
| #define QSTATE_CTRL_RCLK_DREX1 ((void *)(CMU_MIF1_BASE + 0x2404)) |
| #define MIF2_PLL_LOCK ((void *)(CMU_MIF2_BASE + 0x0000 + NSL)) |
| #define MIF2_PLL_CON0 ((void *)(CMU_MIF2_BASE + 0x0100 + NSL)) |
| #define MIF2_PLL_CON1 ((void *)(CMU_MIF2_BASE + 0x0104 + NSL)) |
| #define MIF2_PLL_FREQ_DET ((void *)(CMU_MIF2_BASE + 0x010C + NSL)) |
| #define CLK_CON_MUX_MIF2_PLL ((void *)(CMU_MIF2_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_BUS_PLL_USER_MIF2 ((void *)(CMU_MIF2_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_ACLK_MIF2_PLL ((void *)(CMU_MIF2_BASE + 0x0208 + NSL)) |
| #define CLK_CON_MUX_PCLK_MIF2 ((void *)(CMU_MIF2_BASE + 0x0210 + NSL)) |
| #define CLK_CON_MUX_SCLK_HPM_MIF2 ((void *)(CMU_MIF2_BASE + 0x0214 + NSL)) |
| #define CLK_CON_MUX_PCLK_SMC_MIF2 ((void *)(CMU_MIF2_BASE + 0x0218 + NSL)) |
| #define CLK_CON_DIV_PCLK_MIF2 ((void *)(CMU_MIF2_BASE + 0x0400 + NSL)) |
| #define CLK_CON_DIV_PCLK_SMC_MIF2 ((void *)(CMU_MIF2_BASE + 0x0404 + NSL)) |
| #define CLK_CON_DIV_SCLK_HPM_MIF2 ((void *)(CMU_MIF2_BASE + 0x0408 + NSL)) |
| #define CLK_STAT_MUX_MIF2_PLL ((void *)(CMU_MIF2_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_BUS_PLL_USER_MIF2 ((void *)(CMU_MIF2_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_ACLK_MIF2_PLL ((void *)(CMU_MIF2_BASE + 0x0608 + NSL)) |
| #define CLK_STAT_MUX_PCLK_MIF2 ((void *)(CMU_MIF2_BASE + 0x0610 + NSL)) |
| #define CLK_STAT_MUX_SCLK_HPM_MIF2 ((void *)(CMU_MIF2_BASE + 0x0614 + NSL)) |
| #define CLK_STAT_MUX_PCLK_SMC_MIF2 ((void *)(CMU_MIF2_BASE + 0x0618 + NSL)) |
| #define CLK_ENABLE_ACLK_MIF2 ((void *)(CMU_MIF2_BASE + 0x0800)) |
| #define CLK_ENABLE_PCLK_MIF2 ((void *)(CMU_MIF2_BASE + 0x0900)) |
| #define CLK_ENABLE_ACLK_MIF2_SECURE_DREX_TZ ((void *)(CMU_MIF2_BASE + 0x0904)) |
| #define CLK_ENABLE_SCLK_HPM_MIF2 ((void *)(CMU_MIF2_BASE + 0x0A00)) |
| #define CLK_ENABLE_SCLK_RCLK_DREX_MIF2 ((void *)(CMU_MIF2_BASE + 0x0A04)) |
| #define CG_CTRL_VAL_PCLK_MIF2 ((void *)(CMU_MIF2_BASE + 0x0900)) |
| #define CG_CTRL_VAL_SCLK_HPM_MIF2 ((void *)(CMU_MIF2_BASE + 0x0A00)) |
| #define CG_CTRL_VAL_SCLK_RCLK_DREX2 ((void *)(CMU_MIF2_BASE + 0x0A04)) |
| #define CG_CTRL_VAL_DDRPHY2 ((void *)(CMU_MIF2_BASE + 0x0A08)) |
| #define CLKOUT_CMU_MIF2 ((void *)(CMU_MIF2_BASE + 0x0C00)) |
| #define CLKOUT_CMU_MIF2_DIV_STAT ((void *)(CMU_MIF2_BASE + 0x0C04)) |
| #define CLK_ENABLE_PDN_MIF2 ((void *)(CMU_MIF2_BASE + 0x0E00)) |
| #define MIF2_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_MIF2_BASE + 0x0F28)) |
| #define PSCDC_CTRL_MIF2 ((void *)(CMU_MIF2_BASE + 0x1000)) |
| #define CLK_STOPCTRL_MIF2 ((void *)(CMU_MIF2_BASE + 0x1004)) |
| #define CMU_MIF2_SPARE0 ((void *)(CMU_MIF2_BASE + 0x1100)) |
| #define CMU_MIF2_SPARE1 ((void *)(CMU_MIF2_BASE + 0x1104)) |
| #define CG_CTRL_MAN_PCLK_MIF2 ((void *)(CMU_MIF2_BASE + 0x1900)) |
| #define CG_CTRL_MAN_SCLK_HPM_MIF2 ((void *)(CMU_MIF2_BASE + 0x1A00)) |
| #define CG_CTRL_MAN_SCLK_RCLK_DREX2 ((void *)(CMU_MIF2_BASE + 0x1A04)) |
| #define CG_CTRL_MAN_DDRPHY2 ((void *)(CMU_MIF2_BASE + 0x1A08)) |
| #define CG_CTRL_STAT_PCLK_MIF2_0 ((void *)(CMU_MIF2_BASE + 0x1D00)) |
| #define CG_CTRL_STAT_PCLK_MIF2_1 ((void *)(CMU_MIF2_BASE + 0x1D04)) |
| #define CG_CTRL_STAT_SCLK_HPM_MIF2 ((void *)(CMU_MIF2_BASE + 0x1E00)) |
| #define CG_CTRL_STAT_SCLK_RCLK_DREX2 ((void *)(CMU_MIF2_BASE + 0x1E04)) |
| #define CG_CTRL_STAT_DDRPHY2 ((void *)(CMU_MIF2_BASE + 0x1E08)) |
| #define QCH_CTRL_LH_AXI_P_MIF2 ((void *)(CMU_MIF2_BASE + 0x2000)) |
| #define QCH_CTRL_PMU_MIF2 ((void *)(CMU_MIF2_BASE + 0x2004)) |
| #define QCH_CTRL_SYSREG_MIF2 ((void *)(CMU_MIF2_BASE + 0x2008)) |
| #define QCH_CTRL_CMU_MIF2 ((void *)(CMU_MIF2_BASE + 0x200C)) |
| #define QCH_CTRL_SMC_MIF2 ((void *)(CMU_MIF2_BASE + 0x2010)) |
| #define QSTATE_CTRL_PROMISE_MIF2 ((void *)(CMU_MIF2_BASE + 0x2400)) |
| #define QSTATE_CTRL_RCLK_DREX2 ((void *)(CMU_MIF2_BASE + 0x2404)) |
| #define MIF3_PLL_LOCK ((void *)(CMU_MIF3_BASE + 0x0000 + NSL)) |
| #define MIF3_PLL_CON0 ((void *)(CMU_MIF3_BASE + 0x0100 + NSL)) |
| #define MIF3_PLL_CON1 ((void *)(CMU_MIF3_BASE + 0x0104 + NSL)) |
| #define MIF3_PLL_FREQ_DET ((void *)(CMU_MIF3_BASE + 0x010C + NSL)) |
| #define CLK_CON_MUX_MIF3_PLL ((void *)(CMU_MIF3_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_BUS_PLL_USER_MIF3 ((void *)(CMU_MIF3_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_ACLK_MIF3_PLL ((void *)(CMU_MIF3_BASE + 0x0208 + NSL)) |
| #define CLK_CON_MUX_PCLK_MIF3 ((void *)(CMU_MIF3_BASE + 0x0210 + NSL)) |
| #define CLK_CON_MUX_SCLK_HPM_MIF3 ((void *)(CMU_MIF3_BASE + 0x0214 + NSL)) |
| #define CLK_CON_MUX_PCLK_SMC_MIF3 ((void *)(CMU_MIF3_BASE + 0x0218 + NSL)) |
| #define CLK_CON_DIV_PCLK_MIF3 ((void *)(CMU_MIF3_BASE + 0x0400 + NSL)) |
| #define CLK_CON_DIV_PCLK_SMC_MIF3 ((void *)(CMU_MIF3_BASE + 0x0404 + NSL)) |
| #define CLK_CON_DIV_SCLK_HPM_MIF3 ((void *)(CMU_MIF3_BASE + 0x0408 + NSL)) |
| #define CLK_STAT_MUX_MIF3_PLL ((void *)(CMU_MIF3_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_BUS_PLL_USER_MIF3 ((void *)(CMU_MIF3_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_ACLK_MIF3_PLL ((void *)(CMU_MIF3_BASE + 0x0608 + NSL)) |
| #define CLK_STAT_MUX_PCLK_MIF3 ((void *)(CMU_MIF3_BASE + 0x0610 + NSL)) |
| #define CLK_STAT_MUX_SCLK_HPM_MIF3 ((void *)(CMU_MIF3_BASE + 0x0614 + NSL)) |
| #define CLK_STAT_MUX_PCLK_SMC_MIF3 ((void *)(CMU_MIF3_BASE + 0x0618 + NSL)) |
| #define CLK_ENABLE_ACLK_MIF3 ((void *)(CMU_MIF3_BASE + 0x0800)) |
| #define CLK_ENABLE_PCLK_MIF3 ((void *)(CMU_MIF3_BASE + 0x0900)) |
| #define CLK_ENABLE_ACLK_MIF3_SECURE_DREX_TZ ((void *)(CMU_MIF3_BASE + 0x0904)) |
| #define CLK_ENABLE_SCLK_HPM_MIF3 ((void *)(CMU_MIF3_BASE + 0x0A00)) |
| #define CLK_ENABLE_SCLK_RCLK_DREX_MIF3 ((void *)(CMU_MIF3_BASE + 0x0A04)) |
| #define CG_CTRL_VAL_PCLK_MIF3 ((void *)(CMU_MIF3_BASE + 0x0900)) |
| #define CG_CTRL_VAL_SCLK_HPM_MIF3 ((void *)(CMU_MIF3_BASE + 0x0A00)) |
| #define CG_CTRL_VAL_SCLK_RCLK_DREX3 ((void *)(CMU_MIF3_BASE + 0x0A04)) |
| #define CG_CTRL_VAL_DDRPHY3 ((void *)(CMU_MIF3_BASE + 0x0A08)) |
| #define CLKOUT_CMU_MIF3 ((void *)(CMU_MIF3_BASE + 0x0C00)) |
| #define CLKOUT_CMU_MIF3_DIV_STAT ((void *)(CMU_MIF3_BASE + 0x0C04)) |
| #define CLK_ENABLE_PDN_MIF3 ((void *)(CMU_MIF3_BASE + 0x0E00)) |
| #define MIF3_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_MIF3_BASE + 0x0F28)) |
| #define PSCDC_CTRL_MIF3 ((void *)(CMU_MIF3_BASE + 0x1000)) |
| #define CLK_STOPCTRL_MIF3 ((void *)(CMU_MIF3_BASE + 0x1004)) |
| #define CMU_MIF3_SPARE0 ((void *)(CMU_MIF3_BASE + 0x1100)) |
| #define CMU_MIF3_SPARE1 ((void *)(CMU_MIF3_BASE + 0x1104)) |
| #define CG_CTRL_MAN_PCLK_MIF3 ((void *)(CMU_MIF3_BASE + 0x1900)) |
| #define CG_CTRL_MAN_SCLK_HPM_MIF3 ((void *)(CMU_MIF3_BASE + 0x1A00)) |
| #define CG_CTRL_MAN_SCLK_RCLK_DREX3 ((void *)(CMU_MIF3_BASE + 0x1A04)) |
| #define CG_CTRL_MAN_DDRPHY3 ((void *)(CMU_MIF3_BASE + 0x1A08)) |
| #define CG_CTRL_STAT_PCLK_MIF3_0 ((void *)(CMU_MIF3_BASE + 0x1D00)) |
| #define CG_CTRL_STAT_PCLK_MIF3_1 ((void *)(CMU_MIF3_BASE + 0x1D04)) |
| #define CG_CTRL_STAT_SCLK_HPM_MIF3 ((void *)(CMU_MIF3_BASE + 0x1E00)) |
| #define CG_CTRL_STAT_SCLK_RCLK_DREX3 ((void *)(CMU_MIF3_BASE + 0x1E04)) |
| #define CG_CTRL_STAT_DDRPHY3 ((void *)(CMU_MIF3_BASE + 0x1E08)) |
| #define QCH_CTRL_LH_AXI_P_MIF3 ((void *)(CMU_MIF3_BASE + 0x2000)) |
| #define QCH_CTRL_PMU_MIF3 ((void *)(CMU_MIF3_BASE + 0x2004)) |
| #define QCH_CTRL_SYSREG_MIF3 ((void *)(CMU_MIF3_BASE + 0x2008)) |
| #define QCH_CTRL_CMU_MIF3 ((void *)(CMU_MIF3_BASE + 0x200C)) |
| #define QCH_CTRL_SMC_MIF3 ((void *)(CMU_MIF3_BASE + 0x2010)) |
| #define QSTATE_CTRL_PROMISE_MIF3 ((void *)(CMU_MIF3_BASE + 0x2400)) |
| #define QSTATE_CTRL_RCLK_DREX3 ((void *)(CMU_MIF3_BASE + 0x2404)) |
| #define MNGS_PLL_LOCK ((void *)(CMU_MNGS_BASE + 0x0000 + NSL)) |
| #define MNGS_PLL_CON0 ((void *)(CMU_MNGS_BASE + 0x0100 + NSL)) |
| #define MNGS_PLL_CON1 ((void *)(CMU_MNGS_BASE + 0x0104 + NSL)) |
| #define MNGS_PLL_FREQ_DET ((void *)(CMU_MNGS_BASE + 0x010C + NSL)) |
| #define CLK_CON_MUX_MNGS_PLL ((void *)(CMU_MNGS_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_BUS_PLL_MNGS_USER ((void *)(CMU_MNGS_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_MNGS ((void *)(CMU_MNGS_BASE + 0x0208 + NSL)) |
| #define CLK_CON_DIV_MNGS ((void *)(CMU_MNGS_BASE + 0x0400 + NSL)) |
| #define CLK_CON_DIV_ACLK_MNGS ((void *)(CMU_MNGS_BASE + 0x0404 + NSL)) |
| #define CLK_CON_DIV_ATCLK_MNGS_CORE ((void *)(CMU_MNGS_BASE + 0x0408 + NSL)) |
| #define CLK_CON_DIV_ATCLK_MNGS_SOC ((void *)(CMU_MNGS_BASE + 0x040C + NSL)) |
| #define CLK_CON_DIV_ATCLK_MNGS_CSSYS_TRACECLK ((void *)(CMU_MNGS_BASE + 0x0410 + NSL)) |
| #define CLK_CON_DIV_ATCLK_MNGS_ASYNCATB_CAM1 ((void *)(CMU_MNGS_BASE + 0x0414 + NSL)) |
| #define CLK_CON_DIV_ATCLK_MNGS_ASYNCATB_AUD ((void *)(CMU_MNGS_BASE + 0x0418 + NSL)) |
| #define CLK_CON_DIV_PCLK_DBG_MNGS ((void *)(CMU_MNGS_BASE + 0x041C + NSL)) |
| #define CLK_CON_DIV_PCLK_RUN_MONITOR ((void *)(CMU_MNGS_BASE + 0x0420 + NSL)) |
| #define CLK_CON_DIV_PCLK_MNGS ((void *)(CMU_MNGS_BASE + 0x0424 + NSL)) |
| #define CLK_CON_DIV_CNTCLK_MNGS ((void *)(CMU_MNGS_BASE + 0x0428 + NSL)) |
| #define CLK_CON_DIV_MNGS_RUN_MONITOR ((void *)(CMU_MNGS_BASE + 0x042C + NSL)) |
| #define CLK_CON_DIV_SCLK_PROMISE_MNGS ((void *)(CMU_MNGS_BASE + 0x0430 + NSL)) |
| #define CLK_CON_DIV_MNGS_PLL ((void *)(CMU_MNGS_BASE + 0x0434 + NSL)) |
| #define CLK_STAT_MUX_MNGS_PLL ((void *)(CMU_MNGS_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_BUS_PLL_MNGS_USER ((void *)(CMU_MNGS_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_MNGS ((void *)(CMU_MNGS_BASE + 0x0608 + NSL)) |
| #define CLK_ENABLE_ACLK_MNGS ((void *)(CMU_MNGS_BASE + 0x0800)) |
| #define CLK_ENABLE_ATCLK_MNGS_CORE ((void *)(CMU_MNGS_BASE + 0x0804)) |
| #define CLK_ENABLE_ATCLK_MNGS_SOC ((void *)(CMU_MNGS_BASE + 0x0808)) |
| #define CLK_ENABLE_ATCLK_MNGS_CSSYS_TRACECLK ((void *)(CMU_MNGS_BASE + 0x080C)) |
| #define CLK_ENABLE_ATCLK_MNGS_ASYNCATB_CAM1 ((void *)(CMU_MNGS_BASE + 0x0810)) |
| #define CLK_ENABLE_ATCLK_MNGS_ASYNCATB_AUD ((void *)(CMU_MNGS_BASE + 0x0814)) |
| #define CLK_ENABLE_PCLK_DBG_MNGS ((void *)(CMU_MNGS_BASE + 0x0900)) |
| #define CLK_ENABLE_PCLK_MNGS ((void *)(CMU_MNGS_BASE + 0x0904)) |
| #define CLK_ENABLE_PCLK_HPM_MNGS ((void *)(CMU_MNGS_BASE + 0x0908)) |
| #define CLK_ENABLE_SCLK_MNGS ((void *)(CMU_MNGS_BASE + 0x0A00)) |
| #define CLK_ENABLE_SCLK_PROMISE_MNGS ((void *)(CMU_MNGS_BASE + 0x0A04)) |
| #define CLKOUT_CMU_MNGS ((void *)(CMU_MNGS_BASE + 0x0C00)) |
| #define CLKOUT_CMU_MNGS_DIV_STAT ((void *)(CMU_MNGS_BASE + 0x0C04)) |
| #define CLK_ENABLE_PDN_MNGS ((void *)(CMU_MNGS_BASE + 0x0D00)) |
| #define MNGS_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_MNGS_BASE + 0x0D04)) |
| #define CMU_MNGS_SPARE0 ((void *)(CMU_MNGS_BASE + 0x0D08)) |
| #define CMU_MNGS_SPARE1 ((void *)(CMU_MNGS_BASE + 0x0D0C)) |
| #define ARMCLK_STOPCTRL_MNGS ((void *)(CMU_MNGS_BASE + 0x1000)) |
| #define PWR_CTRL_MNGS ((void *)(CMU_MNGS_BASE + 0x1020)) |
| #define PWR_CTRL2_MNGS ((void *)(CMU_MNGS_BASE + 0x1024)) |
| #define PWR_CTRL3_MNGS ((void *)(CMU_MNGS_BASE + 0x1028)) |
| #define PWR_CTRL4_MNGS ((void *)(CMU_MNGS_BASE + 0x102C)) |
| #define INTR_SPREAD_ENABLE_MNGS ((void *)(CMU_MNGS_BASE + 0x1080)) |
| #define INTR_SPREAD_USE_STANDBYWFI_MNGS ((void *)(CMU_MNGS_BASE + 0x1084)) |
| #define INTR_SPREAD_BLOCKING_DURATION_MNGS ((void *)(CMU_MNGS_BASE + 0x1088)) |
| #define CLK_CON_MUX_ACLK_MSCL0_528_USER ((void *)(CMU_MSCL_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_ACLK_MSCL1_528_USER ((void *)(CMU_MSCL_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_ACLK_MSCL1_528_MSCL ((void *)(CMU_MSCL_BASE + 0x0210 + NSL)) |
| #define CLK_CON_DIV_PCLK_MSCL ((void *)(CMU_MSCL_BASE + 0x0400 + NSL)) |
| #define CLK_STAT_MUX_ACLK_MSCL0_528_USER ((void *)(CMU_MSCL_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_ACLK_MSCL1_528_USER ((void *)(CMU_MSCL_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_ACLK_MSCL1_528_MSCL ((void *)(CMU_MSCL_BASE + 0x0610 + NSL)) |
| #define CG_CTRL_VAL_ACLK_MSCL0_528 ((void *)(CMU_MSCL_BASE + 0x0800)) |
| #define CG_CTRL_VAL_ACLK_MSCL0_528_SECURE_SFW_MSCL_0 ((void *)(CMU_MSCL_BASE + 0x0804)) |
| #define CG_CTRL_VAL_ACLK_MSCL1_528 ((void *)(CMU_MSCL_BASE + 0x0808)) |
| #define CG_CTRL_VAL_ACLK_MSCL1_528_SECURE_SFW_MSCL_1 ((void *)(CMU_MSCL_BASE + 0x080C)) |
| #define CG_CTRL_VAL_PCLK_MSCL ((void *)(CMU_MSCL_BASE + 0x0820)) |
| #define CG_CTRL_VAL_PCLK_MSCL_SECURE_SFW_MSCL_0 ((void *)(CMU_MSCL_BASE + 0x0824)) |
| #define CG_CTRL_VAL_PCLK_MSCL_SECURE_SFW_MSCL_1 ((void *)(CMU_MSCL_BASE + 0x0828)) |
| #define CLKOUT_CMU_MSCL ((void *)(CMU_MSCL_BASE + 0x0C00)) |
| #define CLKOUT_CMU_MSCL_DIV_STAT ((void *)(CMU_MSCL_BASE + 0x0C04)) |
| #define MSCL_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_MSCL_BASE + 0x0D04)) |
| #define CMU_MSCL_SPARE0 ((void *)(CMU_MSCL_BASE + 0x0D08)) |
| #define CMU_MSCL_SPARE1 ((void *)(CMU_MSCL_BASE + 0x0D0C)) |
| #define CG_CTRL_MAN_ACLK_MSCL0_528 ((void *)(CMU_MSCL_BASE + 0x1800)) |
| #define CG_CTRL_MAN_ACLK_MSCL0_528_SECURE_SFW_MSCL_0 ((void *)(CMU_MSCL_BASE + 0x1804)) |
| #define CG_CTRL_MAN_ACLK_MSCL1_528 ((void *)(CMU_MSCL_BASE + 0x1808)) |
| #define CG_CTRL_MAN_ACLK_MSCL1_528_SECURE_SFW_MSCL_1 ((void *)(CMU_MSCL_BASE + 0x180C)) |
| #define CG_CTRL_MAN_PCLK_MSCL ((void *)(CMU_MSCL_BASE + 0x1820)) |
| #define CG_CTRL_MAN_PCLK_MSCL_SECURE_SFW_MSCL_0 ((void *)(CMU_MSCL_BASE + 0x1824)) |
| #define CG_CTRL_MAN_PCLK_MSCL_SECURE_SFW_MSCL_1 ((void *)(CMU_MSCL_BASE + 0x1828)) |
| #define CG_CTRL_STAT_ACLK_MSCL0_528_0 ((void *)(CMU_MSCL_BASE + 0x1C00)) |
| #define CG_CTRL_STAT_ACLK_MSCL0_528_1 ((void *)(CMU_MSCL_BASE + 0x1C04)) |
| #define CG_CTRL_STAT_ACLK_MSCL0_528_SECURE_SFW_MSCL_0 ((void *)(CMU_MSCL_BASE + 0x1C08)) |
| #define CG_CTRL_STAT_ACLK_MSCL1_528_0 ((void *)(CMU_MSCL_BASE + 0x1C0C)) |
| #define CG_CTRL_STAT_ACLK_MSCL1_528_1 ((void *)(CMU_MSCL_BASE + 0x1C10)) |
| #define CG_CTRL_STAT_ACLK_MSCL1_528_SECURE_SFW_MSCL_1 ((void *)(CMU_MSCL_BASE + 0x1C14)) |
| #define CG_CTRL_STAT_PCLK_MSCL_0 ((void *)(CMU_MSCL_BASE + 0x1C20)) |
| #define CG_CTRL_STAT_PCLK_MSCL_1 ((void *)(CMU_MSCL_BASE + 0x1C24)) |
| #define CG_CTRL_STAT_PCLK_MSCL_2 ((void *)(CMU_MSCL_BASE + 0x1C28)) |
| #define CG_CTRL_STAT_PCLK_MSCL_SECURE_SFW_MSCL_0 ((void *)(CMU_MSCL_BASE + 0x1C2C)) |
| #define CG_CTRL_STAT_PCLK_MSCL_SECURE_SFW_MSCL_1 ((void *)(CMU_MSCL_BASE + 0x1C30)) |
| #define QCH_CTRL_LH_ASYNC_MI_MSCLSFR ((void *)(CMU_MSCL_BASE + 0x2000)) |
| #define QCH_CTRL_CMU_MSCL ((void *)(CMU_MSCL_BASE + 0x2004)) |
| #define QCH_CTRL_PMU_MSCL ((void *)(CMU_MSCL_BASE + 0x2008)) |
| #define QCH_CTRL_SYSREG_MSCL ((void *)(CMU_MSCL_BASE + 0x200C)) |
| #define QCH_CTRL_MSCL_0 ((void *)(CMU_MSCL_BASE + 0x2010)) |
| #define QCH_CTRL_MSCL_1 ((void *)(CMU_MSCL_BASE + 0x2014)) |
| #define QCH_CTRL_JPEG ((void *)(CMU_MSCL_BASE + 0x2018)) |
| #define QCH_CTRL_G2D ((void *)(CMU_MSCL_BASE + 0x201C)) |
| #define QCH_CTRL_SMMU_MSCL_0 ((void *)(CMU_MSCL_BASE + 0x2020)) |
| #define QCH_CTRL_SMMU_MSCL_1 ((void *)(CMU_MSCL_BASE + 0x2024)) |
| #define QCH_CTRL_SMMU_JPEG ((void *)(CMU_MSCL_BASE + 0x2028)) |
| #define QCH_CTRL_SMMU_G2D ((void *)(CMU_MSCL_BASE + 0x202C)) |
| #define QCH_CTRL_PPMU_MSCL_0 ((void *)(CMU_MSCL_BASE + 0x2030)) |
| #define QCH_CTRL_PPMU_MSCL_1 ((void *)(CMU_MSCL_BASE + 0x2034)) |
| #define QCH_CTRL_SFW_MSCL_0 ((void *)(CMU_MSCL_BASE + 0x2038)) |
| #define QCH_CTRL_SFW_MSCL_1 ((void *)(CMU_MSCL_BASE + 0x203C)) |
| #define QCH_CTRL_LH_ASYNC_SI_MSCL_0 ((void *)(CMU_MSCL_BASE + 0x2040)) |
| #define QCH_CTRL_LH_ASYNC_SI_MSCL_1 ((void *)(CMU_MSCL_BASE + 0x2044)) |
| #define CLK_CON_MUX_ACLK_PERIC0_66_USER ((void *)(CMU_PERIC0_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_SCLK_UART0_USER ((void *)(CMU_PERIC0_BASE + 0x0204 + NSL)) |
| #define CLK_STAT_MUX_ACLK_PERIC0_66_USER ((void *)(CMU_PERIC0_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_SCLK_UART0_USER ((void *)(CMU_PERIC0_BASE + 0x0604 + NSL)) |
| #define CG_CTRL_VAL_ACLK_PERIC0_66 ((void *)(CMU_PERIC0_BASE + 0x0800)) |
| #define CG_CTRL_VAL_SCLK_UART0 ((void *)(CMU_PERIC0_BASE + 0x0840)) |
| #define CG_CTRL_VAL_SCLK_PWM ((void *)(CMU_PERIC0_BASE + 0x0844)) |
| #define CLKOUT_CMU_PERIC0 ((void *)(CMU_PERIC0_BASE + 0x0C00)) |
| #define CLKOUT_CMU_PERIC0_DIV_STAT ((void *)(CMU_PERIC0_BASE + 0x0C04)) |
| #define PERIC0_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_PERIC0_BASE + 0x0D04)) |
| #define CMU_PERIC0_SPARE0 ((void *)(CMU_PERIC0_BASE + 0x0D08)) |
| #define CMU_PERIC0_SPARE1 ((void *)(CMU_PERIC0_BASE + 0x0D0C)) |
| #define CG_CTRL_MAN_ACLK_PERIC0_66 ((void *)(CMU_PERIC0_BASE + 0x1800)) |
| #define CG_CTRL_MAN_SCLK_UART0 ((void *)(CMU_PERIC0_BASE + 0x1840)) |
| #define CG_CTRL_MAN_SCLK_PWM ((void *)(CMU_PERIC0_BASE + 0x1844)) |
| #define CG_CTRL_STAT_ACLK_PERIC0_66_0 ((void *)(CMU_PERIC0_BASE + 0x1C00)) |
| #define CG_CTRL_STAT_ACLK_PERIC0_66_1 ((void *)(CMU_PERIC0_BASE + 0x1C04)) |
| #define CG_CTRL_STAT_SCLK_UART0 ((void *)(CMU_PERIC0_BASE + 0x1C40)) |
| #define CG_CTRL_STAT_SCLK_PWM ((void *)(CMU_PERIC0_BASE + 0x1C44)) |
| #define QCH_CTRL_AXILHASYNCM_PERIC0 ((void *)(CMU_PERIC0_BASE + 0x2000)) |
| #define QCH_CTRL_CMU_PERIC0 ((void *)(CMU_PERIC0_BASE + 0x2004)) |
| #define QCH_CTRL_PMU_PERIC0 ((void *)(CMU_PERIC0_BASE + 0x2008)) |
| #define QCH_CTRL_SYSREG_PERIC0 ((void *)(CMU_PERIC0_BASE + 0x200C)) |
| #define QSTATE_CTRL_GPIO_BUS0 ((void *)(CMU_PERIC0_BASE + 0x2404)) |
| #define QSTATE_CTRL_UART0 ((void *)(CMU_PERIC0_BASE + 0x2408)) |
| #define QSTATE_CTRL_ADCIF ((void *)(CMU_PERIC0_BASE + 0x240C)) |
| #define QSTATE_CTRL_PWM ((void *)(CMU_PERIC0_BASE + 0x2410)) |
| #define QSTATE_CTRL_HSI2C0 ((void *)(CMU_PERIC0_BASE + 0x2414)) |
| #define QSTATE_CTRL_HSI2C1 ((void *)(CMU_PERIC0_BASE + 0x2418)) |
| #define QSTATE_CTRL_HSI2C4 ((void *)(CMU_PERIC0_BASE + 0x241C)) |
| #define QSTATE_CTRL_HSI2C5 ((void *)(CMU_PERIC0_BASE + 0x2420)) |
| #define QSTATE_CTRL_HSI2C9 ((void *)(CMU_PERIC0_BASE + 0x2424)) |
| #define QSTATE_CTRL_HSI2C10 ((void *)(CMU_PERIC0_BASE + 0x2428)) |
| #define QSTATE_CTRL_HSI2C11 ((void *)(CMU_PERIC0_BASE + 0x242C)) |
| #define CLK_CON_MUX_ACLK_PERIC1_66_USER ((void *)(CMU_PERIC1_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_SCLK_SPI0_USER ((void *)(CMU_PERIC1_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_SCLK_SPI1_USER ((void *)(CMU_PERIC1_BASE + 0x0208 + NSL)) |
| #define CLK_CON_MUX_SCLK_SPI2_USER ((void *)(CMU_PERIC1_BASE + 0x020C + NSL)) |
| #define CLK_CON_MUX_SCLK_SPI3_USER ((void *)(CMU_PERIC1_BASE + 0x0210 + NSL)) |
| #define CLK_CON_MUX_SCLK_SPI4_USER ((void *)(CMU_PERIC1_BASE + 0x0214 + NSL)) |
| #define CLK_CON_MUX_SCLK_SPI5_USER ((void *)(CMU_PERIC1_BASE + 0x0218 + NSL)) |
| #define CLK_CON_MUX_SCLK_SPI6_USER ((void *)(CMU_PERIC1_BASE + 0x021C + NSL)) |
| #define CLK_CON_MUX_SCLK_SPI7_USER ((void *)(CMU_PERIC1_BASE + 0x0220 + NSL)) |
| #define CLK_CON_MUX_SCLK_UART1_USER ((void *)(CMU_PERIC1_BASE + 0x0224 + NSL)) |
| #define CLK_CON_MUX_SCLK_UART2_USER ((void *)(CMU_PERIC1_BASE + 0x0228 + NSL)) |
| #define CLK_CON_MUX_SCLK_UART3_USER ((void *)(CMU_PERIC1_BASE + 0x022C + NSL)) |
| #define CLK_CON_MUX_SCLK_UART4_USER ((void *)(CMU_PERIC1_BASE + 0x0230 + NSL)) |
| #define CLK_CON_MUX_SCLK_UART5_USER ((void *)(CMU_PERIC1_BASE + 0x0234 + NSL)) |
| #define CLK_STAT_MUX_ACLK_PERIC1_66_USER ((void *)(CMU_PERIC1_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_SCLK_SPI0_USER ((void *)(CMU_PERIC1_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_SCLK_SPI1_USER ((void *)(CMU_PERIC1_BASE + 0x0608 + NSL)) |
| #define CLK_STAT_MUX_SCLK_SPI2_USER ((void *)(CMU_PERIC1_BASE + 0x060C + NSL)) |
| #define CLK_STAT_MUX_SCLK_SPI3_USER ((void *)(CMU_PERIC1_BASE + 0x0610 + NSL)) |
| #define CLK_STAT_MUX_SCLK_SPI4_USER ((void *)(CMU_PERIC1_BASE + 0x0614 + NSL)) |
| #define CLK_STAT_MUX_SCLK_SPI5_USER ((void *)(CMU_PERIC1_BASE + 0x0618 + NSL)) |
| #define CLK_STAT_MUX_SCLK_SPI6_USER ((void *)(CMU_PERIC1_BASE + 0x061C + NSL)) |
| #define CLK_STAT_MUX_SCLK_SPI7_USER ((void *)(CMU_PERIC1_BASE + 0x0620 + NSL)) |
| #define CLK_STAT_MUX_SCLK_UART1_USER ((void *)(CMU_PERIC1_BASE + 0x0624 + NSL)) |
| #define CLK_STAT_MUX_SCLK_UART2_USER ((void *)(CMU_PERIC1_BASE + 0x0628 + NSL)) |
| #define CLK_STAT_MUX_SCLK_UART3_USER ((void *)(CMU_PERIC1_BASE + 0x062C + NSL)) |
| #define CLK_STAT_MUX_SCLK_UART4_USER ((void *)(CMU_PERIC1_BASE + 0x0630 + NSL)) |
| #define CLK_STAT_MUX_SCLK_UART5_USER ((void *)(CMU_PERIC1_BASE + 0x0634 + NSL)) |
| #define CG_CTRL_VAL_ACLK_PERIC1_66 ((void *)(CMU_PERIC1_BASE + 0x0800)) |
| #define CG_CTRL_VAL_ACLK_PERIC1_66_HSI2C ((void *)(CMU_PERIC1_BASE + 0x0804)) |
| #define CG_CTRL_VAL_SCLK_SPI0 ((void *)(CMU_PERIC1_BASE + 0x0840)) |
| #define CG_CTRL_VAL_SCLK_SPI1 ((void *)(CMU_PERIC1_BASE + 0x0844)) |
| #define CG_CTRL_VAL_SCLK_SPI2 ((void *)(CMU_PERIC1_BASE + 0x0848)) |
| #define CG_CTRL_VAL_SCLK_SPI3 ((void *)(CMU_PERIC1_BASE + 0x084C)) |
| #define CG_CTRL_VAL_SCLK_SPI4 ((void *)(CMU_PERIC1_BASE + 0x0850)) |
| #define CG_CTRL_VAL_SCLK_SPI5 ((void *)(CMU_PERIC1_BASE + 0x0854)) |
| #define CG_CTRL_VAL_SCLK_SPI6 ((void *)(CMU_PERIC1_BASE + 0x0858)) |
| #define CG_CTRL_VAL_SCLK_SPI7 ((void *)(CMU_PERIC1_BASE + 0x085C)) |
| #define CG_CTRL_VAL_SCLK_UART1 ((void *)(CMU_PERIC1_BASE + 0x0860)) |
| #define CG_CTRL_VAL_SCLK_UART2 ((void *)(CMU_PERIC1_BASE + 0x0864)) |
| #define CG_CTRL_VAL_SCLK_UART3 ((void *)(CMU_PERIC1_BASE + 0x0868)) |
| #define CG_CTRL_VAL_SCLK_UART4 ((void *)(CMU_PERIC1_BASE + 0x086C)) |
| #define CG_CTRL_VAL_SCLK_UART5 ((void *)(CMU_PERIC1_BASE + 0x0870)) |
| #define CLKOUT_CMU_PERIC1 ((void *)(CMU_PERIC1_BASE + 0x0C00)) |
| #define CLKOUT_CMU_PERIC1_DIV_STAT ((void *)(CMU_PERIC1_BASE + 0x0C04)) |
| #define PERIC1_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_PERIC1_BASE + 0x0D04)) |
| #define CMU_PERIC1_SPARE0 ((void *)(CMU_PERIC1_BASE + 0x0D08)) |
| #define CMU_PERIC1_SPARE1 ((void *)(CMU_PERIC1_BASE + 0x0D0C)) |
| #define CG_CTRL_MAN_ACLK_PERIC1_66 ((void *)(CMU_PERIC1_BASE + 0x1800)) |
| #define CG_CTRL_MAN_ACLK_PERIC1_66_HSI2C ((void *)(CMU_PERIC1_BASE + 0x1804)) |
| #define CG_CTRL_MAN_SCLK_SPI0 ((void *)(CMU_PERIC1_BASE + 0x1840)) |
| #define CG_CTRL_MAN_SCLK_SPI1 ((void *)(CMU_PERIC1_BASE + 0x1844)) |
| #define CG_CTRL_MAN_SCLK_SPI2 ((void *)(CMU_PERIC1_BASE + 0x1848)) |
| #define CG_CTRL_MAN_SCLK_SPI3 ((void *)(CMU_PERIC1_BASE + 0x184C)) |
| #define CG_CTRL_MAN_SCLK_SPI4 ((void *)(CMU_PERIC1_BASE + 0x1850)) |
| #define CG_CTRL_MAN_SCLK_SPI5 ((void *)(CMU_PERIC1_BASE + 0x1854)) |
| #define CG_CTRL_MAN_SCLK_SPI6 ((void *)(CMU_PERIC1_BASE + 0x1858)) |
| #define CG_CTRL_MAN_SCLK_SPI7 ((void *)(CMU_PERIC1_BASE + 0x185C)) |
| #define CG_CTRL_MAN_SCLK_UART1 ((void *)(CMU_PERIC1_BASE + 0x1860)) |
| #define CG_CTRL_MAN_SCLK_UART2 ((void *)(CMU_PERIC1_BASE + 0x1864)) |
| #define CG_CTRL_MAN_SCLK_UART3 ((void *)(CMU_PERIC1_BASE + 0x1868)) |
| #define CG_CTRL_MAN_SCLK_UART4 ((void *)(CMU_PERIC1_BASE + 0x186C)) |
| #define CG_CTRL_MAN_SCLK_UART5 ((void *)(CMU_PERIC1_BASE + 0x1870)) |
| #define CG_CTRL_STAT_ACLK_PERIC1_66_0 ((void *)(CMU_PERIC1_BASE + 0x1C00)) |
| #define CG_CTRL_STAT_ACLK_PERIC1_66_1 ((void *)(CMU_PERIC1_BASE + 0x1C04)) |
| #define CG_CTRL_STAT_ACLK_PERIC1_66_2 ((void *)(CMU_PERIC1_BASE + 0x1C08)) |
| #define CG_CTRL_STAT_ACLK_PERIC1_66_3 ((void *)(CMU_PERIC1_BASE + 0x1C0C)) |
| #define CG_CTRL_STAT_ACLK_PERIC1_66_HSI2C ((void *)(CMU_PERIC1_BASE + 0x1C10)) |
| #define CG_CTRL_STAT_SCLK_SPI0 ((void *)(CMU_PERIC1_BASE + 0x1C40)) |
| #define CG_CTRL_STAT_SCLK_SPI1 ((void *)(CMU_PERIC1_BASE + 0x1C44)) |
| #define CG_CTRL_STAT_SCLK_SPI2 ((void *)(CMU_PERIC1_BASE + 0x1C48)) |
| #define CG_CTRL_STAT_SCLK_SPI3 ((void *)(CMU_PERIC1_BASE + 0x1C4C)) |
| #define CG_CTRL_STAT_SCLK_SPI4 ((void *)(CMU_PERIC1_BASE + 0x1C50)) |
| #define CG_CTRL_STAT_SCLK_SPI5 ((void *)(CMU_PERIC1_BASE + 0x1C54)) |
| #define CG_CTRL_STAT_SCLK_SPI6 ((void *)(CMU_PERIC1_BASE + 0x1C58)) |
| #define CG_CTRL_STAT_SCLK_SPI7 ((void *)(CMU_PERIC1_BASE + 0x1C5C)) |
| #define CG_CTRL_STAT_SCLK_UART1 ((void *)(CMU_PERIC1_BASE + 0x1C60)) |
| #define CG_CTRL_STAT_SCLK_UART2 ((void *)(CMU_PERIC1_BASE + 0x1C64)) |
| #define CG_CTRL_STAT_SCLK_UART3 ((void *)(CMU_PERIC1_BASE + 0x1C68)) |
| #define CG_CTRL_STAT_SCLK_UART4 ((void *)(CMU_PERIC1_BASE + 0x1C6C)) |
| #define CG_CTRL_STAT_SCLK_UART5 ((void *)(CMU_PERIC1_BASE + 0x1C70)) |
| #define QCH_CTRL_AXILHASYNCM_PERIC1 ((void *)(CMU_PERIC1_BASE + 0x2000)) |
| #define QCH_CTRL_CMU_PERIC1 ((void *)(CMU_PERIC1_BASE + 0x2004)) |
| #define QCH_CTRL_PMU_PERIC1 ((void *)(CMU_PERIC1_BASE + 0x2008)) |
| #define QCH_CTRL_SYSREG_PERIC1 ((void *)(CMU_PERIC1_BASE + 0x200C)) |
| #define QSTATE_CTRL_GPIO_PERIC1 ((void *)(CMU_PERIC1_BASE + 0x2410)) |
| #define QSTATE_CTRL_GPIO_NFC ((void *)(CMU_PERIC1_BASE + 0x2414)) |
| #define QSTATE_CTRL_GPIO_TOUCH ((void *)(CMU_PERIC1_BASE + 0x2418)) |
| #define QSTATE_CTRL_GPIO_FF ((void *)(CMU_PERIC1_BASE + 0x241C)) |
| #define QSTATE_CTRL_GPIO_ESE ((void *)(CMU_PERIC1_BASE + 0x2420)) |
| #define QSTATE_CTRL_UART1 ((void *)(CMU_PERIC1_BASE + 0x2424)) |
| #define QSTATE_CTRL_UART2 ((void *)(CMU_PERIC1_BASE + 0x2428)) |
| #define QSTATE_CTRL_UART3 ((void *)(CMU_PERIC1_BASE + 0x242C)) |
| #define QSTATE_CTRL_UART4 ((void *)(CMU_PERIC1_BASE + 0x2430)) |
| #define QSTATE_CTRL_UART5 ((void *)(CMU_PERIC1_BASE + 0x2434)) |
| #define QSTATE_CTRL_SPI0 ((void *)(CMU_PERIC1_BASE + 0x2438)) |
| #define QSTATE_CTRL_SPI1 ((void *)(CMU_PERIC1_BASE + 0x243C)) |
| #define QSTATE_CTRL_SPI2 ((void *)(CMU_PERIC1_BASE + 0x2440)) |
| #define QSTATE_CTRL_SPI3 ((void *)(CMU_PERIC1_BASE + 0x2444)) |
| #define QSTATE_CTRL_SPI4 ((void *)(CMU_PERIC1_BASE + 0x2448)) |
| #define QSTATE_CTRL_SPI5 ((void *)(CMU_PERIC1_BASE + 0x244C)) |
| #define QSTATE_CTRL_SPI6 ((void *)(CMU_PERIC1_BASE + 0x2450)) |
| #define QSTATE_CTRL_SPI7 ((void *)(CMU_PERIC1_BASE + 0x2454)) |
| #define QSTATE_CTRL_HSI2C2 ((void *)(CMU_PERIC1_BASE + 0x2458)) |
| #define QSTATE_CTRL_HSI2C3 ((void *)(CMU_PERIC1_BASE + 0x245C)) |
| #define QSTATE_CTRL_HSI2C6 ((void *)(CMU_PERIC1_BASE + 0x2460)) |
| #define QSTATE_CTRL_HSI2C7 ((void *)(CMU_PERIC1_BASE + 0x2464)) |
| #define QSTATE_CTRL_HSI2C8 ((void *)(CMU_PERIC1_BASE + 0x2468)) |
| #define QSTATE_CTRL_HSI2C12 ((void *)(CMU_PERIC1_BASE + 0x246C)) |
| #define QSTATE_CTRL_HSI2C13 ((void *)(CMU_PERIC1_BASE + 0x2470)) |
| #define QSTATE_CTRL_HSI2C14 ((void *)(CMU_PERIC1_BASE + 0x2474)) |
| #define CLK_CON_MUX_ACLK_PERIS_66_USER ((void *)(CMU_PERIS_BASE + 0x0200 + NSL)) |
| #define CLK_STAT_MUX_ACLK_PERIS_66_USER ((void *)(CMU_PERIS_BASE + 0x0600 + NSL)) |
| #define CG_CTRL_VAL_ACLK_PERIS ((void *)(CMU_PERIS_BASE + 0x0800)) |
| #define CG_CTRL_VAL_ACLK_PERIS_HPM_APBIF_PERIS ((void *)(CMU_PERIS_BASE + 0x0804)) |
| #define CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC ((void *)(CMU_PERIS_BASE + 0x0808)) |
| #define CG_CTRL_VAL_ACLK_PERIS_SECURE_RTC ((void *)(CMU_PERIS_BASE + 0x080C)) |
| #define CG_CTRL_VAL_ACLK_PERIS_SECURE_OTP ((void *)(CMU_PERIS_BASE + 0x0810)) |
| #define CG_CTRL_VAL_ACLK_PERIS_SECURE_CHIPID ((void *)(CMU_PERIS_BASE + 0x0814)) |
| #define CG_CTRL_VAL_SCLK_PERIS_SECURE_OTP ((void *)(CMU_PERIS_BASE + 0x0844)) |
| #define CG_CTRL_VAL_SCLK_PERIS_SECURE_CHIPID ((void *)(CMU_PERIS_BASE + 0x0848)) |
| #define CG_CTRL_VAL_SCLK_PERIS ((void *)(CMU_PERIS_BASE + 0x084C)) |
| #define CG_CTRL_VAL_SCLK_PERIS_PROMISE ((void *)(CMU_PERIS_BASE + 0x0850)) |
| #define CLKOUT_CMU_PERIS ((void *)(CMU_PERIS_BASE + 0x0C00)) |
| #define CLKOUT_CMU_PERIS_DIV_STAT ((void *)(CMU_PERIS_BASE + 0x0C04)) |
| #define PERIS_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_PERIS_BASE + 0x0D04)) |
| #define CMU_PERIS_SPARE0 ((void *)(CMU_PERIS_BASE + 0x0D08)) |
| #define CMU_PERIS_SPARE1 ((void *)(CMU_PERIS_BASE + 0x0D0C)) |
| #define CG_CTRL_MAN_ACLK_PERIS ((void *)(CMU_PERIS_BASE + 0x1800)) |
| #define CG_CTRL_MAN_ACLK_PERIS_HPM_APBIF_PERIS ((void *)(CMU_PERIS_BASE + 0x1804)) |
| #define CG_CTRL_MAN_ACLK_PERIS_SECURE_TZPC ((void *)(CMU_PERIS_BASE + 0x1808)) |
| #define CG_CTRL_MAN_ACLK_PERIS_SECURE_RTC ((void *)(CMU_PERIS_BASE + 0x180C)) |
| #define CG_CTRL_MAN_ACLK_PERIS_SECURE_OTP ((void *)(CMU_PERIS_BASE + 0x1810)) |
| #define CG_CTRL_MAN_ACLK_PERIS_SECURE_CHIPID ((void *)(CMU_PERIS_BASE + 0x1814)) |
| #define CG_CTRL_MAN_SCLK_PERIS_SECURE_OTP ((void *)(CMU_PERIS_BASE + 0x1844)) |
| #define CG_CTRL_MAN_SCLK_PERIS_SECURE_CHIPID ((void *)(CMU_PERIS_BASE + 0x1848)) |
| #define CG_CTRL_MAN_SCLK_PERIS ((void *)(CMU_PERIS_BASE + 0x184C)) |
| #define CG_CTRL_MAN_SCLK_PERIS_PROMISE ((void *)(CMU_PERIS_BASE + 0x1850)) |
| #define CG_CTRL_STAT_ACLK_PERIS_0 ((void *)(CMU_PERIS_BASE + 0x1C00)) |
| #define CG_CTRL_STAT_ACLK_PERIS_1 ((void *)(CMU_PERIS_BASE + 0x1C04)) |
| #define CG_CTRL_STAT_ACLK_PERIS_HPM_APBIF_PERIS ((void *)(CMU_PERIS_BASE + 0x1C08)) |
| #define CG_CTRL_STAT_ACLK_PERIS_SECURE_TZPC_0 ((void *)(CMU_PERIS_BASE + 0x1C0C)) |
| #define CG_CTRL_STAT_ACLK_PERIS_SECURE_TZPC_1 ((void *)(CMU_PERIS_BASE + 0x1C10)) |
| #define CG_CTRL_STAT_ACLK_PERIS_SECURE_RTC ((void *)(CMU_PERIS_BASE + 0x1C14)) |
| #define CG_CTRL_STAT_ACLK_PERIS_SECURE_OTP ((void *)(CMU_PERIS_BASE + 0x1C18)) |
| #define CG_CTRL_STAT_ACLK_PERIS_SECURE_CHIPID ((void *)(CMU_PERIS_BASE + 0x1C1C)) |
| #define CG_CTRL_STAT_SCLK_PERIS_SECURE_OTP ((void *)(CMU_PERIS_BASE + 0x1C44)) |
| #define CG_CTRL_STAT_SCLK_PERIS_SECURE_CHIPID ((void *)(CMU_PERIS_BASE + 0x1C48)) |
| #define CG_CTRL_STAT_SCLK_PERIS ((void *)(CMU_PERIS_BASE + 0x1C4C)) |
| #define CG_CTRL_STAT_SCLK_PERIS_PROMISE ((void *)(CMU_PERIS_BASE + 0x1C50)) |
| #define QCH_CTRL_AXILHASYNCM_PERIS ((void *)(CMU_PERIS_BASE + 0x2000)) |
| #define QCH_CTRL_CMU_PERIS ((void *)(CMU_PERIS_BASE + 0x2004)) |
| #define QCH_CTRL_PMU_PERIS ((void *)(CMU_PERIS_BASE + 0x2008)) |
| #define QCH_CTRL_SYSREG_PERIS ((void *)(CMU_PERIS_BASE + 0x200C)) |
| #define QCH_CTRL_MONOCNT_APBIF ((void *)(CMU_PERIS_BASE + 0x2010)) |
| #define QSTATE_CTRL_MCT ((void *)(CMU_PERIS_BASE + 0x240C)) |
| #define QSTATE_CTRL_WDT_MNGS ((void *)(CMU_PERIS_BASE + 0x2410)) |
| #define QSTATE_CTRL_WDT_APOLLO ((void *)(CMU_PERIS_BASE + 0x2414)) |
| #define QSTATE_CTRL_RTC_APBIF ((void *)(CMU_PERIS_BASE + 0x2418)) |
| #define QSTATE_CTRL_SFR_APBIF_TMU ((void *)(CMU_PERIS_BASE + 0x241C)) |
| #define QSTATE_CTRL_SFR_APBIF_HDMI_CEC ((void *)(CMU_PERIS_BASE + 0x2420)) |
| #define QSTATE_CTRL_HPM_APBIF_PERIS ((void *)(CMU_PERIS_BASE + 0x2424)) |
| #define QSTATE_CTRL_TZPC_0 ((void *)(CMU_PERIS_BASE + 0x2428)) |
| #define QSTATE_CTRL_TZPC_1 ((void *)(CMU_PERIS_BASE + 0x242C)) |
| #define QSTATE_CTRL_TZPC_2 ((void *)(CMU_PERIS_BASE + 0x2430)) |
| #define QSTATE_CTRL_TZPC_3 ((void *)(CMU_PERIS_BASE + 0x2434)) |
| #define QSTATE_CTRL_TZPC_4 ((void *)(CMU_PERIS_BASE + 0x2438)) |
| #define QSTATE_CTRL_TZPC_5 ((void *)(CMU_PERIS_BASE + 0x243C)) |
| #define QSTATE_CTRL_TZPC_6 ((void *)(CMU_PERIS_BASE + 0x2440)) |
| #define QSTATE_CTRL_TZPC_7 ((void *)(CMU_PERIS_BASE + 0x2444)) |
| #define QSTATE_CTRL_TZPC_8 ((void *)(CMU_PERIS_BASE + 0x2448)) |
| #define QSTATE_CTRL_TZPC_9 ((void *)(CMU_PERIS_BASE + 0x244C)) |
| #define QSTATE_CTRL_TZPC_10 ((void *)(CMU_PERIS_BASE + 0x2450)) |
| #define QSTATE_CTRL_TZPC_11 ((void *)(CMU_PERIS_BASE + 0x2454)) |
| #define QSTATE_CTRL_TZPC_12 ((void *)(CMU_PERIS_BASE + 0x2458)) |
| #define QSTATE_CTRL_TZPC_13 ((void *)(CMU_PERIS_BASE + 0x245C)) |
| #define QSTATE_CTRL_TZPC_14 ((void *)(CMU_PERIS_BASE + 0x2460)) |
| #define QSTATE_CTRL_TZPC_15 ((void *)(CMU_PERIS_BASE + 0x2464)) |
| #define QSTATE_CTRL_TOP_RTC ((void *)(CMU_PERIS_BASE + 0x2468)) |
| #define QSTATE_CTRL_OTP_CON_TOP ((void *)(CMU_PERIS_BASE + 0x246C)) |
| #define QSTATE_CTRL_SFR_APBIF_CHIPID ((void *)(CMU_PERIS_BASE + 0x2470)) |
| #define QSTATE_CTRL_TMU ((void *)(CMU_PERIS_BASE + 0x2474)) |
| #define QSTATE_CTRL_CHIPID ((void *)(CMU_PERIS_BASE + 0x2484)) |
| #define QSTATE_CTRL_PROMISE_PERIS ((void *)(CMU_PERIS_BASE + 0x2488)) |
| #define BUS0_PLL_LOCK ((void *)(CMU_TOP_BASE + 0x0000 + NSL)) |
| #define BUS1_PLL_LOCK ((void *)(CMU_TOP_BASE + 0x0020 + NSL)) |
| #define BUS2_PLL_LOCK ((void *)(CMU_TOP_BASE + 0x0040 + NSL)) |
| #define BUS3_PLL_LOCK ((void *)(CMU_TOP_BASE + 0x0060 + NSL)) |
| #define MFC_PLL_LOCK ((void *)(CMU_TOP_BASE + 0x0080 + NSL)) |
| #define ISP_PLL_LOCK ((void *)(CMU_TOP_BASE + 0x00A0 + NSL)) |
| #define AUD_PLL_LOCK ((void *)(CMU_TOP_BASE + 0x00C0 + NSL)) |
| #define G3D_PLL_LOCK ((void *)(CMU_TOP_BASE + 0x00E0 + NSL)) |
| #define BUS0_PLL_CON0 ((void *)(CMU_TOP_BASE + 0x0100 + NSL)) |
| #define BUS0_PLL_CON1 ((void *)(CMU_TOP_BASE + 0x0104 + NSL)) |
| #define BUS0_PLL_FREQ_DET ((void *)(CMU_TOP_BASE + 0x010C + NSL)) |
| #define BUS1_PLL_CON0 ((void *)(CMU_TOP_BASE + 0x0120 + NSL)) |
| #define BUS1_PLL_CON1 ((void *)(CMU_TOP_BASE + 0x0124 + NSL)) |
| #define BUS1_PLL_FREQ_DET ((void *)(CMU_TOP_BASE + 0x012C + NSL)) |
| #define BUS2_PLL_CON0 ((void *)(CMU_TOP_BASE + 0x0140 + NSL)) |
| #define BUS2_PLL_CON1 ((void *)(CMU_TOP_BASE + 0x0144 + NSL)) |
| #define BUS2_PLL_FREQ_DET ((void *)(CMU_TOP_BASE + 0x014C + NSL)) |
| #define BUS3_PLL_CON0 ((void *)(CMU_TOP_BASE + 0x0160 + NSL)) |
| #define BUS3_PLL_CON1 ((void *)(CMU_TOP_BASE + 0x0164 + NSL)) |
| #define BUS3_PLL_FREQ_DET ((void *)(CMU_TOP_BASE + 0x016C + NSL)) |
| #define MFC_PLL_CON0 ((void *)(CMU_TOP_BASE + 0x0180 + NSL)) |
| #define MFC_PLL_CON1 ((void *)(CMU_TOP_BASE + 0x0184 + NSL)) |
| #define MFC_PLL_FREQ_DET ((void *)(CMU_TOP_BASE + 0x018C + NSL)) |
| #define ISP_PLL_CON0 ((void *)(CMU_TOP_BASE + 0x01A0 + NSL)) |
| #define ISP_PLL_CON1 ((void *)(CMU_TOP_BASE + 0x01A4 + NSL)) |
| #define ISP_PLL_FREQ_DET ((void *)(CMU_TOP_BASE + 0x01AC + NSL)) |
| #define AUD_PLL_CON0 ((void *)(CMU_TOP_BASE + 0x01C0 + NSL)) |
| #define AUD_PLL_CON1 ((void *)(CMU_TOP_BASE + 0x01C4 + NSL)) |
| #define AUD_PLL_CON2 ((void *)(CMU_TOP_BASE + 0x01C8 + NSL)) |
| #define AUD_PLL_FREQ_DET ((void *)(CMU_TOP_BASE + 0x01D0 + NSL)) |
| #define G3D_PLL_CON0 ((void *)(CMU_TOP_BASE + 0x01E0 + NSL)) |
| #define G3D_PLL_CON1 ((void *)(CMU_TOP_BASE + 0x01E4 + NSL)) |
| #define G3D_PLL_FREQ_DET ((void *)(CMU_TOP_BASE + 0x01EC + NSL)) |
| #define CLK_CON_MUX_BUS0_PLL ((void *)(CMU_TOP_BASE + 0x0200 + NSL)) |
| #define CLK_CON_MUX_BUS1_PLL ((void *)(CMU_TOP_BASE + 0x0204 + NSL)) |
| #define CLK_CON_MUX_BUS2_PLL ((void *)(CMU_TOP_BASE + 0x0208 + NSL)) |
| #define CLK_CON_MUX_BUS3_PLL ((void *)(CMU_TOP_BASE + 0x020C + NSL)) |
| #define CLK_CON_MUX_MFC_PLL ((void *)(CMU_TOP_BASE + 0x0210 + NSL)) |
| #define CLK_CON_MUX_ISP_PLL ((void *)(CMU_TOP_BASE + 0x0214 + NSL)) |
| #define CLK_CON_MUX_AUD_PLL ((void *)(CMU_TOP_BASE + 0x0218 + NSL)) |
| #define CLK_CON_MUX_G3D_PLL ((void *)(CMU_TOP_BASE + 0x021C + NSL)) |
| #define CLK_CON_MUX_SCLK_BUS0_PLL ((void *)(CMU_TOP_BASE + 0x0220 + NSL)) |
| #define CLK_CON_MUX_SCLK_BUS1_PLL ((void *)(CMU_TOP_BASE + 0x0224 + NSL)) |
| #define CLK_CON_MUX_SCLK_BUS2_PLL ((void *)(CMU_TOP_BASE + 0x0228 + NSL)) |
| #define CLK_CON_MUX_SCLK_BUS3_PLL ((void *)(CMU_TOP_BASE + 0x022C + NSL)) |
| #define CLK_CON_MUX_SCLK_MFC_PLL ((void *)(CMU_TOP_BASE + 0x0230 + NSL)) |
| #define CLK_CON_MUX_SCLK_ISP_PLL ((void *)(CMU_TOP_BASE + 0x0234 + NSL)) |
| #define CLK_CON_MUX_ACLK_CCORE_800 ((void *)(CMU_TOP_BASE + 0x0240 + NSL)) |
| #define CLK_CON_MUX_ACLK_CCORE_264 ((void *)(CMU_TOP_BASE + 0x0244 + NSL)) |
| #define CLK_CON_MUX_ACLK_CCORE_G3D_800 ((void *)(CMU_TOP_BASE + 0x0248 + NSL)) |
| #define CLK_CON_MUX_ACLK_CCORE_528 ((void *)(CMU_TOP_BASE + 0x024C + NSL)) |
| #define CLK_CON_MUX_ACLK_CCORE_132 ((void *)(CMU_TOP_BASE + 0x0250 + NSL)) |
| #define CLK_CON_MUX_PCLK_CCORE_66 ((void *)(CMU_TOP_BASE + 0x0254 + NSL)) |
| #define CLK_CON_MUX_ACLK_BUS0_528 ((void *)(CMU_TOP_BASE + 0x0258 + NSL)) |
| #define CLK_CON_MUX_ACLK_BUS0_200 ((void *)(CMU_TOP_BASE + 0x025C + NSL)) |
| #define CLK_CON_MUX_PCLK_BUS0_132 ((void *)(CMU_TOP_BASE + 0x0260 + NSL)) |
| #define CLK_CON_MUX_ACLK_BUS1_528 ((void *)(CMU_TOP_BASE + 0x0264 + NSL)) |
| #define CLK_CON_MUX_PCLK_BUS1_132 ((void *)(CMU_TOP_BASE + 0x0268 + NSL)) |
| #define CLK_CON_MUX_ACLK_DISP0_0_400 ((void *)(CMU_TOP_BASE + 0x026C + NSL)) |
| #define CLK_CON_MUX_ACLK_DISP0_1_400_TOP ((void *)(CMU_TOP_BASE + 0x0270 + NSL)) |
| #define CLK_CON_MUX_ACLK_DISP1_0_400 ((void *)(CMU_TOP_BASE + 0x0274 + NSL)) |
| #define CLK_CON_MUX_ACLK_DISP1_1_400_TOP ((void *)(CMU_TOP_BASE + 0x0278 + NSL)) |
| #define CLK_CON_MUX_ACLK_MFC_600 ((void *)(CMU_TOP_BASE + 0x027C + NSL)) |
| #define CLK_CON_MUX_ACLK_MSCL0_528 ((void *)(CMU_TOP_BASE + 0x0280 + NSL)) |
| #define CLK_CON_MUX_ACLK_MSCL1_528_TOP ((void *)(CMU_TOP_BASE + 0x0284 + NSL)) |
| #define CLK_CON_MUX_ACLK_IMEM_266 ((void *)(CMU_TOP_BASE + 0x0288 + NSL)) |
| #define CLK_CON_MUX_ACLK_IMEM_200 ((void *)(CMU_TOP_BASE + 0x028C + NSL)) |
| #define CLK_CON_MUX_ACLK_IMEM_100 ((void *)(CMU_TOP_BASE + 0x0290 + NSL)) |
| #define CLK_CON_MUX_ACLK_FSYS0_200 ((void *)(CMU_TOP_BASE + 0x0294 + NSL)) |
| #define CLK_CON_MUX_ACLK_FSYS1_200 ((void *)(CMU_TOP_BASE + 0x0298 + NSL)) |
| #define CLK_CON_MUX_ACLK_PERIS_66 ((void *)(CMU_TOP_BASE + 0x029C + NSL)) |
| #define CLK_CON_MUX_ACLK_PERIC0_66 ((void *)(CMU_TOP_BASE + 0x02A0 + NSL)) |
| #define CLK_CON_MUX_ACLK_PERIC1_66 ((void *)(CMU_TOP_BASE + 0x02A4 + NSL)) |
| #define CLK_CON_MUX_ACLK_ISP0_ISP0_528 ((void *)(CMU_TOP_BASE + 0x02A8 + NSL)) |
| #define CLK_CON_MUX_ACLK_ISP0_TPU_400 ((void *)(CMU_TOP_BASE + 0x02AC + NSL)) |
| #define CLK_CON_MUX_ACLK_ISP0_TREX_528 ((void *)(CMU_TOP_BASE + 0x02B0 + NSL)) |
| #define CLK_CON_MUX_ACLK_ISP1_ISP1_468 ((void *)(CMU_TOP_BASE + 0x02B4 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM0_CSIS0_414 ((void *)(CMU_TOP_BASE + 0x02B8 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM0_CSIS1_168 ((void *)(CMU_TOP_BASE + 0x02BC + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM0_CSIS2_234 ((void *)(CMU_TOP_BASE + 0x02C0 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM0_3AA0_414 ((void *)(CMU_TOP_BASE + 0x02C4 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM0_3AA1_414 ((void *)(CMU_TOP_BASE + 0x02C8 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM0_CSIS3_132 ((void *)(CMU_TOP_BASE + 0x02CC + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM0_TREX_528 ((void *)(CMU_TOP_BASE + 0x02D0 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM1_ARM_672 ((void *)(CMU_TOP_BASE + 0x02D4 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM1_TREX_VRA_528 ((void *)(CMU_TOP_BASE + 0x02D8 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM1_TREX_B_528 ((void *)(CMU_TOP_BASE + 0x02DC + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM1_BUS_264 ((void *)(CMU_TOP_BASE + 0x02E0 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM1_PERI_84 ((void *)(CMU_TOP_BASE + 0x02E4 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM1_CSIS2_414 ((void *)(CMU_TOP_BASE + 0x02E8 + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM1_CSIS3_132 ((void *)(CMU_TOP_BASE + 0x02EC + NSL)) |
| #define CLK_CON_MUX_ACLK_CAM1_SCL_566 ((void *)(CMU_TOP_BASE + 0x02F0 + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP0_DECON0_ECLK0_TOP ((void *)(CMU_TOP_BASE + 0x02F4 + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK0_TOP ((void *)(CMU_TOP_BASE + 0x02F8 + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK1_TOP ((void *)(CMU_TOP_BASE + 0x02FC + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP0_HDMI_AUDIO_TOP ((void *)(CMU_TOP_BASE + 0x0300 + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK0_TOP ((void *)(CMU_TOP_BASE + 0x0304 + NSL)) |
| #define CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK1_TOP ((void *)(CMU_TOP_BASE + 0x0308 + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS0_USBDRD30 ((void *)(CMU_TOP_BASE + 0x030C + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS0_MMC0 ((void *)(CMU_TOP_BASE + 0x0310 + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS0_UFSUNIPRO20 ((void *)(CMU_TOP_BASE + 0x0314 + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS0_PHY_24M ((void *)(CMU_TOP_BASE + 0x0318 + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS0_UFSUNIPRO_CFG ((void *)(CMU_TOP_BASE + 0x031C + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS1_MMC2 ((void *)(CMU_TOP_BASE + 0x0320 + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS1_UFSUNIPRO20 ((void *)(CMU_TOP_BASE + 0x0324 + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS1_PCIE_PHY ((void *)(CMU_TOP_BASE + 0x0328 + NSL)) |
| #define CLK_CON_MUX_SCLK_FSYS1_UFSUNIPRO_CFG ((void *)(CMU_TOP_BASE + 0x032C + NSL)) |
| #define CLK_CON_MUX_SCLK_PERIC0_UART0 ((void *)(CMU_TOP_BASE + 0x0330 + NSL)) |
| #define CLK_CON_MUX_SCLK_PERIC1_SPI0 ((void *)(CMU_TOP_BASE + 0x0334 + NSL)) |
| #define CLK_CON_MUX_SCLK_PERIC1_SPI1 ((void *)(CMU_TOP_BASE + 0x0338 + NSL)) |
| #define CLK_CON_MUX_SCLK_PERIC1_SPI2 ((void *)(CMU_TOP_BASE + 0x033C + NSL)) |
| #define CLK_CON_MUX_SCLK_PERIC1_SPI3 ((void *)(CMU_TOP_BASE + 0x0340 + NSL)) |
| #define CLK_CON_MUX_SCLK_PERIC1_SPI4 ((void *)(CMU_TOP_BASE + 0x0344 + NSL)) |
| #define CLK_CON_MUX_SCLK_PERIC1_SPI5 ((void *)(CMU_TOP_BASE + 0x0348 + NSL)) |
| #define CLK_CON_MUX_SCLK_PERIC1_SPI6 ((void *)(CMU_TOP_BASE + 0x034C + NSL)) |
| #define CLK_CON_MUX_SCLK_PERIC1_SPI7 ((void *)(CMU_TOP_BASE + 0x0350 + NSL)) |
| #define CLK_CON_MUX_SCLK_PERIC1_UART1 ((void *)(CMU_TOP_BASE + 0x0354 + NSL)) |
| #define CLK_CON_MUX_SCLK_PERIC1_UART2 ((void *)(CMU_TOP_BASE + 0x0358 + NSL)) |
| #define CLK_CON_MUX_SCLK_PERIC1_UART3 ((void *)(CMU_TOP_BASE + 0x035C + NSL)) |
| #define CLK_CON_MUX_SCLK_PERIC1_UART4 ((void *)(CMU_TOP_BASE + 0x0360 + NSL)) |
| #define CLK_CON_MUX_SCLK_PERIC1_UART5 ((void *)(CMU_TOP_BASE + 0x0364 + NSL)) |
| #define CLK_CON_MUX_SCLK_CAM1_ISP_SPI0 ((void *)(CMU_TOP_BASE + 0x0368 + NSL)) |
| #define CLK_CON_MUX_SCLK_CAM1_ISP_SPI1 ((void *)(CMU_TOP_BASE + 0x036C + NSL)) |
| #define CLK_CON_MUX_SCLK_CAM1_ISP_UART ((void *)(CMU_TOP_BASE + 0x0370 + NSL)) |
| #define CLK_CON_MUX_SCLK_AP2CP_MIF_PLL_OUT ((void *)(CMU_TOP_BASE + 0x0374 + NSL)) |
| #define CLK_CON_MUX_ACLK_PSCDC_400 ((void *)(CMU_TOP_BASE + 0x0378 + NSL)) |
| #define CLK_CON_MUX_SCLK_BUS_PLL_MNGS ((void *)(CMU_TOP_BASE + 0x0380 + NSL)) |
| #define CLK_CON_MUX_SCLK_BUS_PLL_APOLLO ((void *)(CMU_TOP_BASE + 0x0384 + NSL)) |
| #define CLK_CON_MUX_SCLK_BUS_PLL_MIF ((void *)(CMU_TOP_BASE + 0x0388 + NSL)) |
| #define CLK_CON_MUX_SCLK_BUS_PLL_G3D ((void *)(CMU_TOP_BASE + 0x038C + NSL)) |
| #define CLK_CON_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_TOP ((void *)(CMU_TOP_BASE + 0x0390 + NSL)) |
| #define CLK_CON_DIV_ACLK_CCORE_800 ((void *)(CMU_TOP_BASE + 0x03A0 + NSL)) |
| #define CLK_CON_DIV_ACLK_CCORE_264 ((void *)(CMU_TOP_BASE + 0x03A4 + NSL)) |
| #define CLK_CON_DIV_ACLK_CCORE_G3D_800 ((void *)(CMU_TOP_BASE + 0x03A8 + NSL)) |
| #define CLK_CON_DIV_ACLK_CCORE_528 ((void *)(CMU_TOP_BASE + 0x03AC + NSL)) |
| #define CLK_CON_DIV_ACLK_CCORE_132 ((void *)(CMU_TOP_BASE + 0x03B0 + NSL)) |
| #define CLK_CON_DIV_PCLK_CCORE_66 ((void *)(CMU_TOP_BASE + 0x03B4 + NSL)) |
| #define CLK_CON_DIV_ACLK_BUS0_528 ((void *)(CMU_TOP_BASE + 0x03B8 + NSL)) |
| #define CLK_CON_DIV_ACLK_BUS0_200 ((void *)(CMU_TOP_BASE + 0x03BC + NSL)) |
| #define CLK_CON_DIV_PCLK_BUS0_132 ((void *)(CMU_TOP_BASE + 0x03C0 + NSL)) |
| #define CLK_CON_DIV_ACLK_BUS1_528 ((void *)(CMU_TOP_BASE + 0x03C4 + NSL)) |
| #define CLK_CON_DIV_PCLK_BUS1_132 ((void *)(CMU_TOP_BASE + 0x03C8 + NSL)) |
| #define CLK_CON_DIV_ACLK_DISP0_0_400 ((void *)(CMU_TOP_BASE + 0x03CC + NSL)) |
| #define CLK_CON_DIV_ACLK_DISP0_1_400 ((void *)(CMU_TOP_BASE + 0x03D0 + NSL)) |
| #define CLK_CON_DIV_ACLK_DISP1_0_400 ((void *)(CMU_TOP_BASE + 0x03D4 + NSL)) |
| #define CLK_CON_DIV_ACLK_DISP1_1_400 ((void *)(CMU_TOP_BASE + 0x03D8 + NSL)) |
| #define CLK_CON_DIV_ACLK_MFC_600 ((void *)(CMU_TOP_BASE + 0x03DC + NSL)) |
| #define CLK_CON_DIV_ACLK_MSCL0_528 ((void *)(CMU_TOP_BASE + 0x03E0 + NSL)) |
| #define CLK_CON_DIV_ACLK_MSCL1_528 ((void *)(CMU_TOP_BASE + 0x03E4 + NSL)) |
| #define CLK_CON_DIV_ACLK_IMEM_266 ((void *)(CMU_TOP_BASE + 0x03E8 + NSL)) |
| #define CLK_CON_DIV_ACLK_IMEM_200 ((void *)(CMU_TOP_BASE + 0x03EC + NSL)) |
| #define CLK_CON_DIV_ACLK_IMEM_100 ((void *)(CMU_TOP_BASE + 0x03F0 + NSL)) |
| #define CLK_CON_DIV_ACLK_FSYS0_200 ((void *)(CMU_TOP_BASE + 0x03F4 + NSL)) |
| #define CLK_CON_DIV_ACLK_FSYS1_200 ((void *)(CMU_TOP_BASE + 0x03F8 + NSL)) |
| #define CLK_CON_DIV_ACLK_PERIS_66 ((void *)(CMU_TOP_BASE + 0x03FC + NSL)) |
| #define CLK_CON_DIV_ACLK_PERIC0_66 ((void *)(CMU_TOP_BASE + 0x0400 + NSL)) |
| #define CLK_CON_DIV_ACLK_PERIC1_66 ((void *)(CMU_TOP_BASE + 0x0404 + NSL)) |
| #define CLK_CON_DIV_ACLK_ISP0_ISP0_528 ((void *)(CMU_TOP_BASE + 0x0408 + NSL)) |
| #define CLK_CON_DIV_ACLK_ISP0_TPU_400 ((void *)(CMU_TOP_BASE + 0x040C + NSL)) |
| #define CLK_CON_DIV_ACLK_ISP0_TREX_528 ((void *)(CMU_TOP_BASE + 0x0410 + NSL)) |
| #define CLK_CON_DIV_ACLK_ISP1_ISP1_468 ((void *)(CMU_TOP_BASE + 0x0414 + NSL)) |
| #define CLK_CON_DIV_ACLK_CAM0_CSIS0_414 ((void *)(CMU_TOP_BASE + 0x0418 + NSL)) |
| #define CLK_CON_DIV_ACLK_CAM0_CSIS1_168 ((void *)(CMU_TOP_BASE + 0x041C + NSL)) |
| #define CLK_CON_DIV_ACLK_CAM0_CSIS2_234 ((void *)(CMU_TOP_BASE + 0x0420 + NSL)) |
| #define CLK_CON_DIV_ACLK_CAM0_3AA0_414 ((void *)(CMU_TOP_BASE + 0x0424 + NSL)) |
| #define CLK_CON_DIV_ACLK_CAM0_3AA1_414 ((void *)(CMU_TOP_BASE + 0x0428 + NSL)) |
| #define CLK_CON_DIV_ACLK_CAM0_CSIS3_132 ((void *)(CMU_TOP_BASE + 0x042C + NSL)) |
| #define CLK_CON_DIV_ACLK_CAM0_TREX_528 ((void *)(CMU_TOP_BASE + 0x0430 + NSL)) |
| #define CLK_CON_DIV_ACLK_CAM1_ARM_672 ((void *)(CMU_TOP_BASE + 0x0434 + NSL)) |
| #define CLK_CON_DIV_ACLK_CAM1_TREX_VRA_528 ((void *)(CMU_TOP_BASE + 0x0438 + NSL)) |
| #define CLK_CON_DIV_ACLK_CAM1_TREX_B_528 ((void *)(CMU_TOP_BASE + 0x043C + NSL)) |
| #define CLK_CON_DIV_ACLK_CAM1_BUS_264 ((void *)(CMU_TOP_BASE + 0x0440 + NSL)) |
| #define CLK_CON_DIV_ACLK_CAM1_PERI_84 ((void *)(CMU_TOP_BASE + 0x0444 + NSL)) |
| #define CLK_CON_DIV_ACLK_CAM1_CSIS2_414 ((void *)(CMU_TOP_BASE + 0x0448 + NSL)) |
| #define CLK_CON_DIV_ACLK_CAM1_CSIS3_132 ((void *)(CMU_TOP_BASE + 0x044C + NSL)) |
| #define CLK_CON_DIV_ACLK_CAM1_SCL_566 ((void *)(CMU_TOP_BASE + 0x0450 + NSL)) |
| #define CLK_CON_DIV_SCLK_DISP0_DECON0_ECLK0 ((void *)(CMU_TOP_BASE + 0x0454 + NSL)) |
| #define CLK_CON_DIV_SCLK_DISP0_DECON0_VCLK0 ((void *)(CMU_TOP_BASE + 0x0458 + NSL)) |
| #define CLK_CON_DIV_SCLK_DISP0_DECON0_VCLK1 ((void *)(CMU_TOP_BASE + 0x045C + NSL)) |
| #define CLK_CON_DIV_SCLK_DISP0_HDMI_AUDIO ((void *)(CMU_TOP_BASE + 0x0460 + NSL)) |
| #define CLK_CON_DIV_SCLK_DISP1_DECON1_ECLK0 ((void *)(CMU_TOP_BASE + 0x0464 + NSL)) |
| #define CLK_CON_DIV_SCLK_DISP1_DECON1_ECLK1 ((void *)(CMU_TOP_BASE + 0x0468 + NSL)) |
| #define CLK_CON_DIV_SCLK_FSYS0_USBDRD30 ((void *)(CMU_TOP_BASE + 0x046C + NSL)) |
| #define CLK_CON_DIV_SCLK_FSYS0_MMC0 ((void *)(CMU_TOP_BASE + 0x0470 + NSL)) |
| #define CLK_CON_DIV_SCLK_FSYS0_UFSUNIPRO20 ((void *)(CMU_TOP_BASE + 0x0474 + NSL)) |
| #define CLK_CON_DIV_SCLK_FSYS0_PHY_24M ((void *)(CMU_TOP_BASE + 0x0478 + NSL)) |
| #define CLK_CON_DIV_SCLK_FSYS0_UFSUNIPRO_CFG ((void *)(CMU_TOP_BASE + 0x047C + NSL)) |
| #define CLK_CON_DIV_SCLK_FSYS1_MMC2 ((void *)(CMU_TOP_BASE + 0x0480 + NSL)) |
| #define CLK_CON_DIV_SCLK_FSYS1_UFSUNIPRO20 ((void *)(CMU_TOP_BASE + 0x0484 + NSL)) |
| #define CLK_CON_DIV_SCLK_FSYS1_PCIE_PHY ((void *)(CMU_TOP_BASE + 0x0488 + NSL)) |
| #define CLK_CON_DIV_SCLK_FSYS1_UFSUNIPRO_CFG ((void *)(CMU_TOP_BASE + 0x048C + NSL)) |
| #define CLK_CON_DIV_SCLK_PERIC0_UART0 ((void *)(CMU_TOP_BASE + 0x0490 + NSL)) |
| #define CLK_CON_DIV_SCLK_PERIC1_SPI0 ((void *)(CMU_TOP_BASE + 0x0494 + NSL)) |
| #define CLK_CON_DIV_SCLK_PERIC1_SPI1 ((void *)(CMU_TOP_BASE + 0x0498 + NSL)) |
| #define CLK_CON_DIV_SCLK_PERIC1_SPI2 ((void *)(CMU_TOP_BASE + 0x049C + NSL)) |
| #define CLK_CON_DIV_SCLK_PERIC1_SPI3 ((void *)(CMU_TOP_BASE + 0x04A0 + NSL)) |
| #define CLK_CON_DIV_SCLK_PERIC1_SPI4 ((void *)(CMU_TOP_BASE + 0x04A4 + NSL)) |
| #define CLK_CON_DIV_SCLK_PERIC1_SPI5 ((void *)(CMU_TOP_BASE + 0x04A8 + NSL)) |
| #define CLK_CON_DIV_SCLK_PERIC1_SPI6 ((void *)(CMU_TOP_BASE + 0x04AC + NSL)) |
| #define CLK_CON_DIV_SCLK_PERIC1_SPI7 ((void *)(CMU_TOP_BASE + 0x04B0 + NSL)) |
| #define CLK_CON_DIV_SCLK_PERIC1_UART1 ((void *)(CMU_TOP_BASE + 0x04B4 + NSL)) |
| #define CLK_CON_DIV_SCLK_PERIC1_UART2 ((void *)(CMU_TOP_BASE + 0x04B8 + NSL)) |
| #define CLK_CON_DIV_SCLK_PERIC1_UART3 ((void *)(CMU_TOP_BASE + 0x04BC + NSL)) |
| #define CLK_CON_DIV_SCLK_PERIC1_UART4 ((void *)(CMU_TOP_BASE + 0x04C0 + NSL)) |
| #define CLK_CON_DIV_SCLK_PERIC1_UART5 ((void *)(CMU_TOP_BASE + 0x04C4 + NSL)) |
| #define CLK_CON_DIV_SCLK_CAM1_ISP_SPI0 ((void *)(CMU_TOP_BASE + 0x04C8 + NSL)) |
| #define CLK_CON_DIV_SCLK_CAM1_ISP_SPI1 ((void *)(CMU_TOP_BASE + 0x04CC + NSL)) |
| #define CLK_CON_DIV_SCLK_CAM1_ISP_UART ((void *)(CMU_TOP_BASE + 0x04D0 + NSL)) |
| #define CLK_CON_DIV_SCLK_AP2CP_MIF_PLL_OUT ((void *)(CMU_TOP_BASE + 0x04D4 + NSL)) |
| #define CLK_CON_DIV_ACLK_PSCDC_400 ((void *)(CMU_TOP_BASE + 0x04D8 + NSL)) |
| #define CLK_CON_DIV_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_TOP ((void *)(CMU_TOP_BASE + 0x04DC + NSL)) |
| #define CLK_CON_DIV_SCLK_BUS_PLL_MNGS ((void *)(CMU_TOP_BASE + 0x04F0 + NSL)) |
| #define CLK_CON_DIV_SCLK_BUS_PLL_APOLLO ((void *)(CMU_TOP_BASE + 0x04F4 + NSL)) |
| #define CLK_CON_DIV_SCLK_BUS_PLL_MIF ((void *)(CMU_TOP_BASE + 0x04F8 + NSL)) |
| #define CLK_CON_DIV_SCLK_BUS_PLL_G3D ((void *)(CMU_TOP_BASE + 0x04FC + NSL)) |
| #define CLK_STAT_MUX_BUS0_PLL ((void *)(CMU_TOP_BASE + 0x0500 + NSL)) |
| #define CLK_STAT_MUX_BUS1_PLL ((void *)(CMU_TOP_BASE + 0x0504 + NSL)) |
| #define CLK_STAT_MUX_BUS2_PLL ((void *)(CMU_TOP_BASE + 0x0508 + NSL)) |
| #define CLK_STAT_MUX_BUS3_PLL ((void *)(CMU_TOP_BASE + 0x050C + NSL)) |
| #define CLK_STAT_MUX_MFC_PLL ((void *)(CMU_TOP_BASE + 0x0510 + NSL)) |
| #define CLK_STAT_MUX_ISP_PLL ((void *)(CMU_TOP_BASE + 0x0514 + NSL)) |
| #define CLK_STAT_MUX_AUD_PLL ((void *)(CMU_TOP_BASE + 0x0518 + NSL)) |
| #define CLK_STAT_MUX_G3D_PLL ((void *)(CMU_TOP_BASE + 0x051C + NSL)) |
| #define CLK_STAT_MUX_SCLK_BUS0_PLL ((void *)(CMU_TOP_BASE + 0x0520 + NSL)) |
| #define CLK_STAT_MUX_SCLK_BUS1_PLL ((void *)(CMU_TOP_BASE + 0x0524 + NSL)) |
| #define CLK_STAT_MUX_SCLK_BUS2_PLL ((void *)(CMU_TOP_BASE + 0x0528 + NSL)) |
| #define CLK_STAT_MUX_SCLK_BUS3_PLL ((void *)(CMU_TOP_BASE + 0x052C + NSL)) |
| #define CLK_STAT_MUX_SCLK_MFC_PLL ((void *)(CMU_TOP_BASE + 0x0530 + NSL)) |
| #define CLK_STAT_MUX_SCLK_ISP_PLL ((void *)(CMU_TOP_BASE + 0x0534 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CCORE_800 ((void *)(CMU_TOP_BASE + 0x0540 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CCORE_264 ((void *)(CMU_TOP_BASE + 0x0544 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CCORE_G3D_800 ((void *)(CMU_TOP_BASE + 0x0548 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CCORE_528 ((void *)(CMU_TOP_BASE + 0x054C + NSL)) |
| #define CLK_STAT_MUX_ACLK_CCORE_132 ((void *)(CMU_TOP_BASE + 0x0550 + NSL)) |
| #define CLK_STAT_MUX_PCLK_CCORE_66 ((void *)(CMU_TOP_BASE + 0x0554 + NSL)) |
| #define CLK_STAT_MUX_ACLK_BUS0_528 ((void *)(CMU_TOP_BASE + 0x0558 + NSL)) |
| #define CLK_STAT_MUX_ACLK_BUS0_200 ((void *)(CMU_TOP_BASE + 0x055C + NSL)) |
| #define CLK_STAT_MUX_PCLK_BUS0_132 ((void *)(CMU_TOP_BASE + 0x0560 + NSL)) |
| #define CLK_STAT_MUX_ACLK_BUS1_528 ((void *)(CMU_TOP_BASE + 0x0564 + NSL)) |
| #define CLK_STAT_MUX_PCLK_BUS1_132 ((void *)(CMU_TOP_BASE + 0x0568 + NSL)) |
| #define CLK_STAT_MUX_ACLK_DISP0_0_400 ((void *)(CMU_TOP_BASE + 0x056C + NSL)) |
| #define CLK_STAT_MUX_ACLK_DISP0_1_400_TOP ((void *)(CMU_TOP_BASE + 0x0570 + NSL)) |
| #define CLK_STAT_MUX_ACLK_DISP1_0_400 ((void *)(CMU_TOP_BASE + 0x0574 + NSL)) |
| #define CLK_STAT_MUX_ACLK_DISP1_1_400_TOP ((void *)(CMU_TOP_BASE + 0x0578 + NSL)) |
| #define CLK_STAT_MUX_ACLK_MFC_600 ((void *)(CMU_TOP_BASE + 0x057C + NSL)) |
| #define CLK_STAT_MUX_ACLK_MSCL0_528 ((void *)(CMU_TOP_BASE + 0x0580 + NSL)) |
| #define CLK_STAT_MUX_ACLK_MSCL1_528_TOP ((void *)(CMU_TOP_BASE + 0x0584 + NSL)) |
| #define CLK_STAT_MUX_ACLK_IMEM_266 ((void *)(CMU_TOP_BASE + 0x0588 + NSL)) |
| #define CLK_STAT_MUX_ACLK_IMEM_200 ((void *)(CMU_TOP_BASE + 0x058C + NSL)) |
| #define CLK_STAT_MUX_ACLK_IMEM_100 ((void *)(CMU_TOP_BASE + 0x0590 + NSL)) |
| #define CLK_STAT_MUX_ACLK_FSYS0_200 ((void *)(CMU_TOP_BASE + 0x0594 + NSL)) |
| #define CLK_STAT_MUX_ACLK_FSYS1_200 ((void *)(CMU_TOP_BASE + 0x0598 + NSL)) |
| #define CLK_STAT_MUX_ACLK_PERIS_66 ((void *)(CMU_TOP_BASE + 0x059C + NSL)) |
| #define CLK_STAT_MUX_ACLK_PERIC0_66 ((void *)(CMU_TOP_BASE + 0x05A0 + NSL)) |
| #define CLK_STAT_MUX_ACLK_PERIC1_66 ((void *)(CMU_TOP_BASE + 0x05A4 + NSL)) |
| #define CLK_STAT_MUX_ACLK_ISP0_ISP0_528 ((void *)(CMU_TOP_BASE + 0x05A8 + NSL)) |
| #define CLK_STAT_MUX_ACLK_ISP0_TPU_400 ((void *)(CMU_TOP_BASE + 0x05AC + NSL)) |
| #define CLK_STAT_MUX_ACLK_ISP0_TREX_528 ((void *)(CMU_TOP_BASE + 0x05B0 + NSL)) |
| #define CLK_STAT_MUX_ACLK_ISP1_ISP1_468 ((void *)(CMU_TOP_BASE + 0x05B4 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM0_CSIS0_414 ((void *)(CMU_TOP_BASE + 0x05B8 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM0_CSIS1_168 ((void *)(CMU_TOP_BASE + 0x05BC + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM0_CSIS2_234 ((void *)(CMU_TOP_BASE + 0x05C0 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM0_3AA0_414 ((void *)(CMU_TOP_BASE + 0x05C4 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM0_3AA1_414 ((void *)(CMU_TOP_BASE + 0x05C8 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM0_CSIS3_132 ((void *)(CMU_TOP_BASE + 0x05CC + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM0_TREX_528 ((void *)(CMU_TOP_BASE + 0x05D0 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM1_ARM_672 ((void *)(CMU_TOP_BASE + 0x05D4 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM1_TREX_VRA_528 ((void *)(CMU_TOP_BASE + 0x05D8 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM1_TREX_B_528 ((void *)(CMU_TOP_BASE + 0x05DC + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM1_BUS_264 ((void *)(CMU_TOP_BASE + 0x05E0 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM1_PERI_84 ((void *)(CMU_TOP_BASE + 0x05E4 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM1_CSIS2_414 ((void *)(CMU_TOP_BASE + 0x05E8 + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM1_CSIS3_132 ((void *)(CMU_TOP_BASE + 0x05EC + NSL)) |
| #define CLK_STAT_MUX_ACLK_CAM1_SCL_566 ((void *)(CMU_TOP_BASE + 0x05F0 + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP0_DECON0_ECLK0_TOP ((void *)(CMU_TOP_BASE + 0x05F4 + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP0_DECON0_VCLK0_TOP ((void *)(CMU_TOP_BASE + 0x05F8 + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP0_DECON0_VCLK1_TOP ((void *)(CMU_TOP_BASE + 0x05FC + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP0_HDMI_AUDIO_TOP ((void *)(CMU_TOP_BASE + 0x0600 + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP1_DECON1_ECLK0_TOP ((void *)(CMU_TOP_BASE + 0x0604 + NSL)) |
| #define CLK_STAT_MUX_SCLK_DISP1_DECON1_ECLK1_TOP ((void *)(CMU_TOP_BASE + 0x0608 + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS0_USBDRD30 ((void *)(CMU_TOP_BASE + 0x060C + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS0_MMC0 ((void *)(CMU_TOP_BASE + 0x0610 + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS0_UFSUNIPRO20 ((void *)(CMU_TOP_BASE + 0x0614 + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS0_PHY_24M ((void *)(CMU_TOP_BASE + 0x0618 + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS0_UFSUNIPRO_CFG ((void *)(CMU_TOP_BASE + 0x061C + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS1_MMC2 ((void *)(CMU_TOP_BASE + 0x0620 + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS1_UFSUNIPRO20 ((void *)(CMU_TOP_BASE + 0x0624 + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS1_PCIE_PHY ((void *)(CMU_TOP_BASE + 0x0628 + NSL)) |
| #define CLK_STAT_MUX_SCLK_FSYS1_UFSUNIPRO_CFG ((void *)(CMU_TOP_BASE + 0x062C + NSL)) |
| #define CLK_STAT_MUX_SCLK_PERIC0_UART0 ((void *)(CMU_TOP_BASE + 0x0630 + NSL)) |
| #define CLK_STAT_MUX_SCLK_PERIC1_SPI0 ((void *)(CMU_TOP_BASE + 0x0634 + NSL)) |
| #define CLK_STAT_MUX_SCLK_PERIC1_SPI1 ((void *)(CMU_TOP_BASE + 0x0638 + NSL)) |
| #define CLK_STAT_MUX_SCLK_PERIC1_SPI2 ((void *)(CMU_TOP_BASE + 0x063C + NSL)) |
| #define CLK_STAT_MUX_SCLK_PERIC1_SPI3 ((void *)(CMU_TOP_BASE + 0x0640 + NSL)) |
| #define CLK_STAT_MUX_SCLK_PERIC1_SPI4 ((void *)(CMU_TOP_BASE + 0x0644 + NSL)) |
| #define CLK_STAT_MUX_SCLK_PERIC1_SPI5 ((void *)(CMU_TOP_BASE + 0x0648 + NSL)) |
| #define CLK_STAT_MUX_SCLK_PERIC1_SPI6 ((void *)(CMU_TOP_BASE + 0x064C + NSL)) |
| #define CLK_STAT_MUX_SCLK_PERIC1_SPI7 ((void *)(CMU_TOP_BASE + 0x0650 + NSL)) |
| #define CLK_STAT_MUX_SCLK_PERIC1_UART1 ((void *)(CMU_TOP_BASE + 0x0654 + NSL)) |
| #define CLK_STAT_MUX_SCLK_PERIC1_UART2 ((void *)(CMU_TOP_BASE + 0x0658 + NSL)) |
| #define CLK_STAT_MUX_SCLK_PERIC1_UART3 ((void *)(CMU_TOP_BASE + 0x065C + NSL)) |
| #define CLK_STAT_MUX_SCLK_PERIC1_UART4 ((void *)(CMU_TOP_BASE + 0x0660 + NSL)) |
| #define CLK_STAT_MUX_SCLK_PERIC1_UART5 ((void *)(CMU_TOP_BASE + 0x0664 + NSL)) |
| #define CLK_STAT_MUX_SCLK_CAM1_ISP_SPI0 ((void *)(CMU_TOP_BASE + 0x0668 + NSL)) |
| #define CLK_STAT_MUX_SCLK_CAM1_ISP_SPI1 ((void *)(CMU_TOP_BASE + 0x066C + NSL)) |
| #define CLK_STAT_MUX_SCLK_CAM1_ISP_UART ((void *)(CMU_TOP_BASE + 0x0670 + NSL)) |
| #define CLK_STAT_MUX_SCLK_AP2CP_MIF_PLL_OUT ((void *)(CMU_TOP_BASE + 0x0674 + NSL)) |
| #define CLK_STAT_MUX_ACLK_PSCDC_400 ((void *)(CMU_TOP_BASE + 0x0678 + NSL)) |
| #define CLK_STAT_MUX_SCLK_BUS_PLL_MNGS ((void *)(CMU_TOP_BASE + 0x0680 + NSL)) |
| #define CLK_STAT_MUX_SCLK_BUS_PLL_APOLLO ((void *)(CMU_TOP_BASE + 0x0684 + NSL)) |
| #define CLK_STAT_MUX_SCLK_BUS_PLL_MIF ((void *)(CMU_TOP_BASE + 0x0688 + NSL)) |
| #define CLK_STAT_MUX_SCLK_BUS_PLL_G3D ((void *)(CMU_TOP_BASE + 0x068C + NSL)) |
| #define CLK_STAT_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_TOP ((void *)(CMU_TOP_BASE + 0x0690 + NSL)) |
| #define CLK_ENABLE_ACLK_CCORE_800 ((void *)(CMU_TOP_BASE + 0x0800)) |
| #define CLK_ENABLE_ACLK_CCORE_264 ((void *)(CMU_TOP_BASE + 0x0804)) |
| #define CLK_ENABLE_ACLK_CCORE_G3D_800 ((void *)(CMU_TOP_BASE + 0x0808)) |
| #define CLK_ENABLE_ACLK_CCORE_528 ((void *)(CMU_TOP_BASE + 0x080C)) |
| #define CLK_ENABLE_ACLK_CCORE_132 ((void *)(CMU_TOP_BASE + 0x0810)) |
| #define CLK_ENABLE_PCLK_CCORE_66 ((void *)(CMU_TOP_BASE + 0x0814)) |
| #define CLK_ENABLE_ACLK_BUS0_528_TOP ((void *)(CMU_TOP_BASE + 0x0818)) |
| #define CLK_ENABLE_ACLK_BUS0_200_TOP ((void *)(CMU_TOP_BASE + 0x081C)) |
| #define CLK_ENABLE_PCLK_BUS0_132_TOP ((void *)(CMU_TOP_BASE + 0x0820)) |
| #define CLK_ENABLE_ACLK_BUS1_528_TOP ((void *)(CMU_TOP_BASE + 0x0824)) |
| #define CLK_ENABLE_PCLK_BUS1_132_TOP ((void *)(CMU_TOP_BASE + 0x0828)) |
| #define CLK_ENABLE_ACLK_DISP0_0_400 ((void *)(CMU_TOP_BASE + 0x082C)) |
| #define CLK_ENABLE_ACLK_DISP0_1_400 ((void *)(CMU_TOP_BASE + 0x0830)) |
| #define CLK_ENABLE_ACLK_DISP1_0_400 ((void *)(CMU_TOP_BASE + 0x0834)) |
| #define CLK_ENABLE_ACLK_DISP1_1_400 ((void *)(CMU_TOP_BASE + 0x0838)) |
| #define CLK_ENABLE_ACLK_MFC_600 ((void *)(CMU_TOP_BASE + 0x083C)) |
| #define CLK_ENABLE_ACLK_MSCL0_528 ((void *)(CMU_TOP_BASE + 0x0840)) |
| #define CLK_ENABLE_ACLK_MSCL1_528 ((void *)(CMU_TOP_BASE + 0x0844)) |
| #define CLK_ENABLE_ACLK_IMEM_266 ((void *)(CMU_TOP_BASE + 0x0848)) |
| #define CLK_ENABLE_ACLK_IMEM_200 ((void *)(CMU_TOP_BASE + 0x084C)) |
| #define CLK_ENABLE_ACLK_IMEM_100 ((void *)(CMU_TOP_BASE + 0x0850)) |
| #define CLK_ENABLE_ACLK_FSYS0_200 ((void *)(CMU_TOP_BASE + 0x0854)) |
| #define CLK_ENABLE_ACLK_FSYS1_200 ((void *)(CMU_TOP_BASE + 0x0858)) |
| #define CLK_ENABLE_ACLK_PERIS_66 ((void *)(CMU_TOP_BASE + 0x085C)) |
| #define CLK_ENABLE_ACLK_PERIC0_66 ((void *)(CMU_TOP_BASE + 0x0860)) |
| #define CLK_ENABLE_ACLK_PERIC1_66 ((void *)(CMU_TOP_BASE + 0x0864)) |
| #define CLK_ENABLE_ACLK_ISP0_ISP0_528 ((void *)(CMU_TOP_BASE + 0x0868)) |
| #define CLK_ENABLE_ACLK_ISP0_TPU_400 ((void *)(CMU_TOP_BASE + 0x086C)) |
| #define CLK_ENABLE_ACLK_ISP0_TREX_528 ((void *)(CMU_TOP_BASE + 0x0870)) |
| #define CLK_ENABLE_ACLK_ISP1_ISP1_468 ((void *)(CMU_TOP_BASE + 0x0874)) |
| #define CLK_ENABLE_ACLK_CAM0_CSIS1_414 ((void *)(CMU_TOP_BASE + 0x0878)) |
| #define CLK_ENABLE_ACLK_CAM0_CSIS1_168_TOP ((void *)(CMU_TOP_BASE + 0x087C)) |
| #define CLK_ENABLE_ACLK_CAM0_CSIS2_234_TOP ((void *)(CMU_TOP_BASE + 0x0880)) |
| #define CLK_ENABLE_ACLK_CAM0_3AA0_414_TOP ((void *)(CMU_TOP_BASE + 0x0884)) |
| #define CLK_ENABLE_ACLK_CAM0_3AA1_414_TOP ((void *)(CMU_TOP_BASE + 0x0888)) |
| #define CLK_ENABLE_ACLK_CAM0_CSIS3_132_TOP ((void *)(CMU_TOP_BASE + 0x088C)) |
| #define CLK_ENABLE_ACLK_CAM0_TREX_528_TOP ((void *)(CMU_TOP_BASE + 0x0890)) |
| #define CLK_ENABLE_ACLK_CAM1_ARM_672_TOP ((void *)(CMU_TOP_BASE + 0x0894)) |
| #define CLK_ENABLE_ACLK_CAM1_TREX_VRA_528_TOP ((void *)(CMU_TOP_BASE + 0x0898)) |
| #define CLK_ENABLE_ACLK_CAM1_TREX_B_528_TOP ((void *)(CMU_TOP_BASE + 0x089C)) |
| #define CLK_ENABLE_ACLK_CAM1_BUS_264_TOP ((void *)(CMU_TOP_BASE + 0x08A0)) |
| #define CLK_ENABLE_ACLK_CAM1_PERI_84 ((void *)(CMU_TOP_BASE + 0x08A4)) |
| #define CLK_ENABLE_ACLK_CAM1_CSIS2_414_TOP ((void *)(CMU_TOP_BASE + 0x08A8)) |
| #define CLK_ENABLE_ACLK_CAM1_CSIS3_132_TOP ((void *)(CMU_TOP_BASE + 0x08AC)) |
| #define CLK_ENABLE_ACLK_CAM1_SCL_566_TOP ((void *)(CMU_TOP_BASE + 0x08B0)) |
| #define CLK_ENABLE_SCLK_DISP0_DECON0_ECLK0 ((void *)(CMU_TOP_BASE + 0x0900)) |
| #define CLK_ENABLE_SCLK_DISP0_DECON0_VCLK0 ((void *)(CMU_TOP_BASE + 0x0904)) |
| #define CLK_ENABLE_SCLK_DISP0_DECON0_VCLK1 ((void *)(CMU_TOP_BASE + 0x0908)) |
| #define CLK_ENABLE_SCLK_DISP0_HDMI_ADUIO ((void *)(CMU_TOP_BASE + 0x090C)) |
| #define CLK_ENABLE_SCLK_DISP1_DECON1_ECLK0 ((void *)(CMU_TOP_BASE + 0x0910)) |
| #define CLK_ENABLE_SCLK_DISP1_DECON1_ECLK1 ((void *)(CMU_TOP_BASE + 0x0914)) |
| #define CLK_ENABLE_SCLK_FSYS0_USBDRD30 ((void *)(CMU_TOP_BASE + 0x0918)) |
| #define CLK_ENABLE_SCLK_FSYS0_MMC0 ((void *)(CMU_TOP_BASE + 0x091C)) |
| #define CLK_ENABLE_SCLK_FSYS0_UFSUNIPRO20 ((void *)(CMU_TOP_BASE + 0x0920)) |
| #define CLK_ENABLE_SCLK_FSYS0_PHY_24M ((void *)(CMU_TOP_BASE + 0x0924)) |
| #define CLK_ENABLE_SCLK_FSYS0_UFSUNIPRO_CFG ((void *)(CMU_TOP_BASE + 0x0928)) |
| #define CLK_ENABLE_SCLK_FSYS1_MMC2 ((void *)(CMU_TOP_BASE + 0x092C)) |
| #define CLK_ENABLE_SCLK_FSYS1_UFSUNIPRO20 ((void *)(CMU_TOP_BASE + 0x0930)) |
| #define CLK_ENABLE_SCLK_FSYS1_PCIE_PHY ((void *)(CMU_TOP_BASE + 0x0934)) |
| #define CLK_ENABLE_SCLK_FSYS1_UFSUNIPRO_CFG ((void *)(CMU_TOP_BASE + 0x0938)) |
| #define CLK_ENABLE_SCLK_PERIC0_UART0 ((void *)(CMU_TOP_BASE + 0x093C)) |
| #define CLK_ENABLE_SCLK_PERIC1_SPI0 ((void *)(CMU_TOP_BASE + 0x0940)) |
| #define CLK_ENABLE_SCLK_PERIC1_SPI1 ((void *)(CMU_TOP_BASE + 0x0944)) |
| #define CLK_ENABLE_SCLK_PERIC1_SPI2 ((void *)(CMU_TOP_BASE + 0x0948)) |
| #define CLK_ENABLE_SCLK_PERIC1_SPI3 ((void *)(CMU_TOP_BASE + 0x094C)) |
| #define CLK_ENABLE_SCLK_PERIC1_SPI4 ((void *)(CMU_TOP_BASE + 0x0950)) |
| #define CLK_ENABLE_SCLK_PERIC1_SPI5 ((void *)(CMU_TOP_BASE + 0x0954)) |
| #define CLK_ENABLE_SCLK_PERIC1_SPI6 ((void *)(CMU_TOP_BASE + 0x0958)) |
| #define CLK_ENABLE_SCLK_PERIC1_SPI7 ((void *)(CMU_TOP_BASE + 0x095C)) |
| #define CLK_ENABLE_SCLK_PERIC1_UART1 ((void *)(CMU_TOP_BASE + 0x0960)) |
| #define CLK_ENABLE_SCLK_PERIC1_UART2 ((void *)(CMU_TOP_BASE + 0x0964)) |
| #define CLK_ENABLE_SCLK_PERIC1_UART3 ((void *)(CMU_TOP_BASE + 0x0968)) |
| #define CLK_ENABLE_SCLK_PERIC1_UART4 ((void *)(CMU_TOP_BASE + 0x096C)) |
| #define CLK_ENABLE_SCLK_PERIC1_UART5 ((void *)(CMU_TOP_BASE + 0x0970)) |
| #define CLK_ENABLE_SCLK_CAM1_ISP_SPI0_TOP ((void *)(CMU_TOP_BASE + 0x0974)) |
| #define CLK_ENABLE_SCLK_CAM1_ISP_SPI1_TOP ((void *)(CMU_TOP_BASE + 0x0978)) |
| #define CLK_ENABLE_SCLK_CAM1_ISP_UART_TOP ((void *)(CMU_TOP_BASE + 0x097C)) |
| #define CLK_ENABLE_SCLK_AP2CP_MIF_PLL_OUT ((void *)(CMU_TOP_BASE + 0x0980)) |
| #define CLK_ENABLE_ACLK_PSCDC_400 ((void *)(CMU_TOP_BASE + 0x0984)) |
| #define CLK_ENABLE_SCLK_BUS_PLL_MNGS ((void *)(CMU_TOP_BASE + 0x0990)) |
| #define CLK_ENABLE_SCLK_BUS_PLL_APOLLO ((void *)(CMU_TOP_BASE + 0x0994)) |
| #define CLK_ENABLE_SCLK_BUS_PLL_MIF ((void *)(CMU_TOP_BASE + 0x0998)) |
| #define CLK_ENABLE_SCLK_BUS_PLL_G3D ((void *)(CMU_TOP_BASE + 0x099C)) |
| #define CLK_ENABLE_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_TOP ((void *)(CMU_TOP_BASE + 0x09A0)) |
| #define CLK_CON_MUX_SCLK_ISP_SENSOR0 ((void *)(CMU_TOP_BASE + 0x0B00 + NSL)) |
| #define CLK_CON_DIV_SCLK_ISP_SENSOR0 ((void *)(CMU_TOP_BASE + 0x0B04 + NSL)) |
| #define CLK_STAT_MUX_SCLK_ISP_SENSOR0 ((void *)(CMU_TOP_BASE + 0x0B08 + NSL)) |
| #define CLK_ENABLE_SCLK_ISP_SENSOR0 ((void *)(CMU_TOP_BASE + 0x0B0C)) |
| #define CLK_CON_MUX_SCLK_ISP_SENSOR1 ((void *)(CMU_TOP_BASE + 0x0B10 + NSL)) |
| #define CLK_CON_DIV_SCLK_ISP_SENSOR1 ((void *)(CMU_TOP_BASE + 0x0B14 + NSL)) |
| #define CLK_STAT_MUX_SCLK_ISP_SENSOR1 ((void *)(CMU_TOP_BASE + 0x0B18 + NSL)) |
| #define CLK_ENABLE_SCLK_ISP_SENSOR1 ((void *)(CMU_TOP_BASE + 0x0B1C)) |
| #define CLK_CON_MUX_SCLK_ISP_SENSOR2 ((void *)(CMU_TOP_BASE + 0x0B20 + NSL)) |
| #define CLK_CON_DIV_SCLK_ISP_SENSOR2 ((void *)(CMU_TOP_BASE + 0x0B24 + NSL)) |
| #define CLK_STAT_MUX_SCLK_ISP_SENSOR2 ((void *)(CMU_TOP_BASE + 0x0B28 + NSL)) |
| #define CLK_ENABLE_SCLK_ISP_SENSOR2 ((void *)(CMU_TOP_BASE + 0x0B2C)) |
| #define CLK_CON_MUX_SCLK_ISP_SENSOR3 ((void *)(CMU_TOP_BASE + 0x0B30 + NSL)) |
| #define CLK_CON_DIV_SCLK_ISP_SENSOR3 ((void *)(CMU_TOP_BASE + 0x0B34 + NSL)) |
| #define CLK_STAT_MUX_SCLK_ISP_SENSOR3 ((void *)(CMU_TOP_BASE + 0x0B38 + NSL)) |
| #define CLK_ENABLE_SCLK_ISP_SENSOR3 ((void *)(CMU_TOP_BASE + 0x0B3C)) |
| #define CLK_CON_MUX_SCLK_PROMISE_INT ((void *)(CMU_TOP_BASE + 0x0B40 + NSL)) |
| #define CLK_CON_DIV_SCLK_PROMISE_INT ((void *)(CMU_TOP_BASE + 0x0B44 + NSL)) |
| #define CLK_STAT_MUX_SCLK_PROMISE_INT ((void *)(CMU_TOP_BASE + 0x0B48 + NSL)) |
| #define CLK_ENABLE_SCLK_PROMISE_INT ((void *)(CMU_TOP_BASE + 0x0B4C)) |
| #define CLK_CON_MUX_SCLK_PROMISE_DISP ((void *)(CMU_TOP_BASE + 0x0B50 + NSL)) |
| #define CLK_CON_DIV_SCLK_PROMISE_DISP ((void *)(CMU_TOP_BASE + 0x0B54 + NSL)) |
| #define CLK_STAT_MUX_SCLK_PROMISE_DISP ((void *)(CMU_TOP_BASE + 0x0B58 + NSL)) |
| #define CLK_ENABLE_SCLK_PROMISE_DISP ((void *)(CMU_TOP_BASE + 0x0B5C)) |
| #define CLKOUT_CMU_TOP0 ((void *)(CMU_TOP_BASE + 0x0C00)) |
| #define CLKOUT_CMU_TOP0_DIV_STAT ((void *)(CMU_TOP_BASE + 0x0C04)) |
| #define CLKOUT_CMU_TOP1 ((void *)(CMU_TOP_BASE + 0x0C10)) |
| #define CLKOUT_CMU_TOP1_DIV_STAT ((void *)(CMU_TOP_BASE + 0x0C14)) |
| #define CLKOUT_CMU_TOP2 ((void *)(CMU_TOP_BASE + 0x0C20)) |
| #define CLKOUT_CMU_TOP2_DIV_STAT ((void *)(CMU_TOP_BASE + 0x0C24)) |
| #define CMU_TOP__CLKOUT0 ((void *)(CMU_TOP_BASE + 0x0C30)) |
| #define CMU_TOP__CLKOUT1 ((void *)(CMU_TOP_BASE + 0x0C34)) |
| #define CMU_TOP__CLKOUT2 ((void *)(CMU_TOP_BASE + 0x0C38)) |
| #define CMU_TOP__CLKOUT3 ((void *)(CMU_TOP_BASE + 0x0C3C)) |
| #define CLK_CON_MUX_CP2AP_MIF_CLK_USER ((void *)(CMU_TOP_BASE + 0x0D00)) |
| #define CLK_STAT_MUX_CP2AP_MIF_CLK_USER ((void *)(CMU_TOP_BASE + 0x0D0C)) |
| #define AP2CP_CLK_CTRL ((void *)(CMU_TOP_BASE + 0x0D10)) |
| #define CLK_ENABLE_PDN_TOP ((void *)(CMU_TOP_BASE + 0x0E00)) |
| #define TOP_ROOTCLKEN ((void *)(CMU_TOP_BASE + 0x0F04 + NSL)) |
| #define TOP0_ROOTCLKEN_ON_GATE ((void *)(CMU_TOP_BASE + 0x0F10 + NSL)) |
| #define TOP1_ROOTCLKEN_ON_GATE ((void *)(CMU_TOP_BASE + 0x0F14 + NSL)) |
| #define TOP2_ROOTCLKEN_ON_GATE ((void *)(CMU_TOP_BASE + 0x0F18 + NSL)) |
| #define TOP3_ROOTCLKEN_ON_GATE ((void *)(CMU_TOP_BASE + 0x0F1C + NSL)) |
| #define TOP0_ROOTCLKEN_ON_MUX ((void *)(CMU_TOP_BASE + 0x0F20 + NSL)) |
| #define TOP1_ROOTCLKEN_ON_MUX ((void *)(CMU_TOP_BASE + 0x0F24 + NSL)) |
| #define TOP2_ROOTCLKEN_ON_MUX ((void *)(CMU_TOP_BASE + 0x0F28 + NSL)) |
| #define TOP3_ROOTCLKEN_ON_MUX ((void *)(CMU_TOP_BASE + 0x0F2C + NSL)) |
| #define TOP_ROOTCLKEN_AFTER_PLL_MUX ((void *)(CMU_TOP_BASE + 0x0F30 + NSL)) |
| #define TOP0_ROOTCLKEN_ON_GATE_STATUS ((void *)(CMU_TOP_BASE + 0x0F40 + NSL)) |
| #define TOP1_ROOTCLKEN_ON_GATE_STATUS ((void *)(CMU_TOP_BASE + 0x0F44 + NSL)) |
| #define TOP2_ROOTCLKEN_ON_GATE_STATUS ((void *)(CMU_TOP_BASE + 0x0F48 + NSL)) |
| #define TOP3_ROOTCLKEN_ON_GATE_STATUS ((void *)(CMU_TOP_BASE + 0x0F4C + NSL)) |
| #define TOP0_ROOTCLKEN_ON_MUX_STATUS ((void *)(CMU_TOP_BASE + 0x0F50 + NSL)) |
| #define TOP1_ROOTCLKEN_ON_MUX_STATUS ((void *)(CMU_TOP_BASE + 0x0F54 + NSL)) |
| #define TOP2_ROOTCLKEN_ON_MUX_STATUS ((void *)(CMU_TOP_BASE + 0x0F58 + NSL)) |
| #define TOP3_ROOTCLKEN_ON_MUX_STATUS ((void *)(CMU_TOP_BASE + 0x0F5C + NSL)) |
| #define TOP_ROOTCLKEN_AFTER_PLL_MUX_STATUS ((void *)(CMU_TOP_BASE + 0x0F60 + NSL)) |
| #define TOP_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_TOP_BASE + 0x0F80 + NSL)) |
| #define PSCDC_CTRL0 ((void *)(CMU_TOP_BASE + 0x1000 + NSL + NSL)) |
| #define PSCDC_CTRL1 ((void *)(CMU_TOP_BASE + 0x1004 + NSL + NSL)) |
| #define PSCDC_CTRL2 ((void *)(CMU_TOP_BASE + 0x1008 + NSL + NSL)) |
| #define PSCDC_CTRL3 ((void *)(CMU_TOP_BASE + 0x100C + NSL + NSL)) |
| #define PSCDC_SCI_FIFO_CLK_CON0 ((void *)(CMU_TOP_BASE + 0x1010 + NSL)) |
| #define PSCDC_SCI_FIFO_CLK_CON1 ((void *)(CMU_TOP_BASE + 0x1014 + NSL)) |
| #define PSCDC_SCI_FIFO_CLK_CON2 ((void *)(CMU_TOP_BASE + 0x1018 + NSL)) |
| #define PSCDC_SCI_FIFO_CLK_CON3 ((void *)(CMU_TOP_BASE + 0x101C + NSL)) |
| #define PSCDC_SMC_FIFO_CLK_CON0 ((void *)(CMU_TOP_BASE + 0x1020 + NSL)) |
| #define PSCDC_SMC_FIFO_CLK_CON1 ((void *)(CMU_TOP_BASE + 0x1024 + NSL)) |
| #define PSCDC_SMC_FIFO_CLK_CON2 ((void *)(CMU_TOP_BASE + 0x1028 + NSL)) |
| #define PSCDC_SMC_FIFO_CLK_CON3 ((void *)(CMU_TOP_BASE + 0x102C + NSL)) |
| #define PSCDC_SMC_FIFO_CLK_CON4 ((void *)(CMU_TOP_BASE + 0x1030 + NSL)) |
| #define PSCDC_SMC_FIFO_CLK_CON5 ((void *)(CMU_TOP_BASE + 0x1034 + NSL)) |
| #define CCORE_CLK_CTRL0 ((void *)(CMU_TOP_BASE + 0x1060 + NSL)) |
| #define MIF_CLK_CTRL0 ((void *)(CMU_TOP_BASE + 0x1080 + NSL)) |
| #define MIF_CLK_CTRL1 ((void *)(CMU_TOP_BASE + 0x1084 + NSL)) |
| #define MIF_CLK_CTRL2 ((void *)(CMU_TOP_BASE + 0x1088 + NSL)) |
| #define MIF_CLK_CTRL3 ((void *)(CMU_TOP_BASE + 0x108C + NSL)) |
| #define MIF_CLK_CTRL4 ((void *)(CMU_TOP_BASE + 0x1090 + NSL)) |
| #define ACD_PSCDC_CTRL_0 ((void *)(CMU_TOP_BASE + 0x1094 + NSL)) |
| #define ACD_PSCDC_CTRL_1 ((void *)(CMU_TOP_BASE + 0x1098 + NSL)) |
| #define ACD_PSCDC_STAT ((void *)(CMU_TOP_BASE + 0x109C + NSL)) |
| #define CMU_TOP__SPARE0 ((void *)(CMU_TOP_BASE + 0x1100)) |
| #define CMU_TOP__SPARE1 ((void *)(CMU_TOP_BASE + 0x1104)) |
| #define CMU_TOP__SPARE2 ((void *)(CMU_TOP_BASE + 0x1108)) |
| #define CMU_TOP__SPARE3 ((void *)(CMU_TOP_BASE + 0x110C)) |
| |
| |
| |
| #define MNGS_EMA_CON ((void *)(SYSREG_MNGS_BASE + 0x0314)) |
| #define MNGS_ASSIST_CON ((void *)(SYSREG_MNGS_BASE + 0x1040)) |
| |
| #define APOLLO_EMA_CON ((void *)(SYSREG_APOLLO_BASE + 0x0320)) |
| |
| #define EMA_RF2_UHD_CON ((void *)(SYSREG_G3D_BASE + 0x0314)) |
| |
| #define APOLLO_DRCG_EN ((void *)(SYSREG_APOLLO_BASE + 0x0200)) |
| #define AUD_DRCG_EN ((void *)(SYSREG_AUD_BASE + 0x0200)) |
| #define BUS0_DRCG_EN ((void *)(SYSREG_BUS0_BASE + 0x0200)) |
| #define BUS1_DRCG_EN ((void *)(SYSREG_BUS1_BASE + 0x0200)) |
| #define CAM0_DRCG_EN ((void *)(SYSREG_CAM0_BASE + 0x0200)) |
| #define CAM0_CG_OVERRIDE ((void *)(SYSREG_CAM0_BASE + 0x0500)) |
| #define CAM1_DRCG_EN ((void *)(SYSREG_CAM1_BASE + 0x0200)) |
| #define CAM1_CG_OVERRIDE ((void *)(SYSREG_CAM1_BASE + 0x0500)) |
| #define CCORE_DRCG_EN ((void *)(SYSREG_CCORE_BASE + 0x0200)) |
| #define DISP0_DRCG_EN ((void *)(SYSREG_DISP0_BASE + 0x0200)) |
| #define DISP1_DRCG_EN ((void *)(SYSREG_DISP1_BASE + 0x0200)) |
| #define FSYS0_DRCG_EN ((void *)(SYSREG_FSYS0_BASE + 0x0200)) |
| #define FSYS1_DRCG_EN ((void *)(SYSREG_FSYS1_BASE + 0x0200)) |
| #define G3D_DRCG_EN ((void *)(SYSREG_G3D_BASE + 0x0200)) |
| #define IMEM_DRCG_EN ((void *)(SYSREG_IMEM_BASE + 0x0200)) |
| #define ISP0_DRCG_EN ((void *)(SYSREG_ISP0_BASE + 0x0200)) |
| #define ISP0_CG_OVERRIDE ((void *)(SYSREG_ISP0_BASE + 0x0500)) |
| #define ISP1_DRCG_EN ((void *)(SYSREG_ISP1_BASE + 0x0200)) |
| #define ISP1_CG_OVERRIDE ((void *)(SYSREG_ISP1_BASE + 0x0500)) |
| #define MFC_DRCG_EN ((void *)(SYSREG_MFC_BASE + 0x0200)) |
| #define MIF0_DRCG_EN ((void *)(SYSREG_MIF0_BASE + 0x0200)) |
| #define MIF1_DRCG_EN ((void *)(SYSREG_MIF1_BASE + 0x0200)) |
| #define MIF2_DRCG_EN ((void *)(SYSREG_MIF2_BASE + 0x0200)) |
| #define MIF3_DRCG_EN ((void *)(SYSREG_MIF3_BASE + 0x0200)) |
| #define MNGS_DRCG_EN ((void *)(SYSREG_MNGS_BASE + 0x0200)) |
| #define MSCL_DRCG_EN ((void *)(SYSREG_MSCL_BASE + 0x0200)) |
| #define PERIC0_DRCG_EN ((void *)(SYSREG_PERIC0_BASE + 0x0200)) |
| #define PERIC1_DRCG_EN ((void *)(SYSREG_PERIC1_BASE + 0x0200)) |
| #define PERIS_DRCG_EN ((void *)(SYSREG_PERIS_BASE + 0x0200)) |
| |
| #define AP_TURN 0 |
| #define CP_TURN 1 |
| #define AP_FLAG ((void *)(MAILBOX_BASE + 0x0180)) |
| #define CP_FLAG ((void *)(MAILBOX_BASE + 0x0184)) |
| #define INIT_TURN ((void *)(MAILBOX_BASE + 0x0188)) |
| #define MIF_INIT_DONE ((void *)(MAILBOX_BASE + 0x004C)) |
| #define MIF_MUX_DONE ((void *)(MAILBOX_BASE + 0x018C)) |
| #define MIF_USE_BUS1_PLL ((void *)(MAILBOX_BASE + 0x0194)) |
| #define MIF_INIT_FLAG 0x4 |
| |
| #define MAILBOX_EVS_MODE ((void *)(MAILBOX_BASE + 0x00C0)) |
| |
| #endif |