| #ifndef __CMUCAL_QCH_H__ |
| #define __CMUCAL_QCH_H__ |
| |
| #include "../cmucal.h" |
| |
| /*=================CMUCAL version: S5E8895================================*/ |
| |
| enum qch_id { |
| ABOX_CMU_ABOX_QCH = QCH_TYPE, |
| ABOX_TOP_QCH, |
| BTM_ABOX_QCH, |
| DMIC_QCH, |
| GPIO_ABOX_QCH, |
| LHM_AXI_P_ABOX_QCH, |
| LHS_ATB_ABOX_QCH, |
| LHS_AXI_D_ABOX_QCH, |
| PMU_ABOX_QCH, |
| BCM_ABOX_QCH, |
| SMMU_ABOX_QCH, |
| SYSREG_ABOX_QCH, |
| TREX_ABOX_QCH, |
| WDT_ABOXCPU_QCH, |
| APM_QCH_SYS, |
| APM_QCH_CPU, |
| APM_QCH_OSCCLK, |
| APM_CMU_APM_QCH, |
| LHM_AXI_P_ALIVE_QCH, |
| LHS_AXI_D_ALIVE_QCH, |
| MAILBOX_APM2AP_QCH, |
| MAILBOX_APM2CP_QCH, |
| MAILBOX_APM2GNSS_QCH, |
| SCAN2AXI_QCH, |
| SYSREG_APM_QCH, |
| WDT_APM_QCH, |
| BUS1_CMU_BUS1_QCH, |
| LHM_ACEL_D_FSYS1_QCH, |
| LHM_AXI_D_ALIVE_QCH, |
| LHM_AXI_D_GNSS_QCH, |
| LHS_AXI_P_ALIVE_QCH, |
| LHS_AXI_P_FSYS1_QCH, |
| PMU_BUS1_QCH, |
| SYSREG_BUS1_QCH, |
| TREX_D_BUS1_QCH, |
| TREX_P_BUS1_QCH, |
| ADCIF_BUSC_QCH_S0, |
| ADCIF_BUSC_QCH_S1, |
| BUSC_CMU_BUSC_QCH, |
| BUSIF_CMUTOPC_QCH, |
| GNSSMBOX_QCH, |
| GPIO_BUSC_QCH, |
| HSI2CDF_QCH, |
| LHM_ACEL_D0_G2D_QCH, |
| LHM_ACEL_D1_G2D_QCH, |
| LHM_ACEL_D2_G2D_QCH, |
| LHM_ACEL_D_DSP_QCH, |
| LHM_ACEL_D_FSYS0_QCH, |
| LHM_ACEL_D_IVA_QCH, |
| LHM_ACEL_D_VPU_QCH, |
| LHM_AXI_D0_CAM_QCH, |
| LHM_AXI_D0_DPU_QCH, |
| LHM_AXI_D0_MFC_QCH, |
| LHM_AXI_D1_CAM_QCH, |
| LHM_AXI_D1_DPU_QCH, |
| LHM_AXI_D1_MFC_QCH, |
| LHM_AXI_D2_DPU_QCH, |
| LHM_AXI_D_ABOX_QCH, |
| LHM_AXI_D_ISPLP_QCH, |
| LHM_AXI_D_SRDZ_QCH, |
| LHM_AXI_D_VTS_QCH, |
| LHM_AXI_G_CSSYS_QCH, |
| LHS_AXI_D_IVASC_QCH, |
| LHS_AXI_P0_DPU_QCH, |
| LHS_AXI_P1_DPU_QCH, |
| LHS_AXI_P_ABOX_QCH, |
| LHS_AXI_P_CAM_QCH, |
| LHS_AXI_P_DSP_QCH, |
| LHS_AXI_P_FSYS0_QCH, |
| LHS_AXI_P_G2D_QCH, |
| LHS_AXI_P_ISPHQ_QCH, |
| LHS_AXI_P_ISPLP_QCH, |
| LHS_AXI_P_IVA_QCH, |
| LHS_AXI_P_MFC_QCH, |
| LHS_AXI_P_MIF0_QCH, |
| LHS_AXI_P_MIF1_QCH, |
| LHS_AXI_P_MIF2_QCH, |
| LHS_AXI_P_MIF3_QCH, |
| LHS_AXI_P_PERIC0_QCH, |
| LHS_AXI_P_PERIC1_QCH, |
| LHS_AXI_P_PERIS_QCH, |
| LHS_AXI_P_SRDZ_QCH, |
| LHS_AXI_P_VPU_QCH, |
| LHS_AXI_P_VTS_QCH, |
| MBOX_QCH, |
| PDMA0_QCH, |
| PMU_BUSC_QCH, |
| SECMBOX_QCH, |
| SPDMA_QCH, |
| SPEEDY_QCH, |
| SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY, |
| SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP, |
| SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP, |
| SYSREG_BUSC_QCH, |
| TREX_D_BUSC_QCH, |
| TREX_P_BUSC_QCH, |
| BTM_CAMD0_QCH, |
| BTM_CAMD1_QCH, |
| CAM_CMU_CAM_QCH, |
| ISP_EWGEN_CAM_QCH, |
| IS_CAM_QCH_CSIS0, |
| IS_CAM_QCH_CSIS1, |
| IS_CAM_QCH_CSIS2, |
| IS_CAM_QCH_CSIS3, |
| IS_CAM_QCH_MC_SCALER, |
| IS_CAM_QCH_CSISX4_DMA, |
| IS_CAM_QCH_SYSMMU_CAM0, |
| IS_CAM_QCH_SYSMMU_CAM1, |
| IS_CAM_QCH_BCM_CAM0, |
| IS_CAM_QCH_BCM_CAM1, |
| IS_CAM_QCH_TPU0, |
| IS_CAM_QCH_VRA, |
| IS_CAM_QCH_QE_TPU0, |
| IS_CAM_QCH_QE_VRA, |
| IS_CAM_QCH_BNS, |
| IS_CAM_QCH_QE_CSISX4, |
| IS_CAM_QCH_QE_TPU1, |
| IS_CAM_QCH_TPU1, |
| LHM_ATB_SRDZCAM_QCH, |
| LHM_AXI_P_CAM_QCH, |
| LHS_AXI_D0_CAM_QCH, |
| LHS_AXI_D1_CAM_QCH, |
| PMU_CAM_QCH, |
| SYSREG_CAM_QCH, |
| CMU_CMU_CMUREF_QCH, |
| DFTMUX_TOP_QCH_CIS_CLK0, |
| DFTMUX_TOP_QCH_CIS_CLK1, |
| DFTMUX_TOP_QCH_CIS_CLK2, |
| DFTMUX_TOP_QCH_CIS_CLK3, |
| APBBR_CCI_QCH, |
| BDU_QCH, |
| BUSIF_HPMCORE_QCH, |
| CCI_QCH, |
| CORE_CMU_CORE_QCH, |
| LHM_ACE_D0_G3D_QCH, |
| LHM_ACE_D1_G3D_QCH, |
| LHM_ACE_D2_G3D_QCH, |
| LHM_ACE_D3_G3D_QCH, |
| LHM_ACE_D_CPUCL1_QCH, |
| LHM_AXI_D_CP_QCH, |
| LHM_AXI_P_CP_QCH, |
| LHS_ATB_T_BDU_QCH, |
| LHS_AXI_P_CPUCL0_QCH, |
| LHS_AXI_P_CPUCL1_QCH, |
| LHS_AXI_P_DBG_QCH, |
| LHS_AXI_P_G3D_QCH, |
| LHS_AXI_P_IMEM_QCH, |
| PMU_CORE_QCH, |
| PPCFW_G3D_QCH, |
| BCM_CPUCL0_QCH, |
| BCM_CPUCL1_QCH, |
| BCM_G3D0_QCH, |
| BCM_G3D1_QCH, |
| BCM_G3D2_QCH, |
| BCM_G3D3_QCH, |
| SYSREG_CORE_QCH, |
| TREX_D_CORE_QCH, |
| TREX_P0_CORE_QCH, |
| TREX_P1_CORE_QCH, |
| BUSIF_DROOPDETECTOR_CPUCL0_QCH, |
| BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP0, |
| BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP1, |
| BUSIF_HPMCPUCL0_QCH, |
| CLUSTER0_QCH, |
| CLUSTER0_QCH_LHS_ATB_T0_CLUSTER0, |
| CLUSTER0_QCH_LHS_ATB_T1_CLUSTER0, |
| CLUSTER0_QCH_LHS_ATB_T2_CLUSTER0, |
| CLUSTER0_QCH_LHS_ATB_T3_CLUSTER0, |
| CMU_CPUCL0_SHORTSTOP_QCH, |
| CPUCL0_CMU_CPUCL0_QCH, |
| LHM_AXI_P_CPUCL0_QCH, |
| PMU_CPUCL0_QCH, |
| SYSREG_CPUCL0_QCH, |
| BUSIF_HPMCPUCL1_QCH, |
| CLUSTER1_QCH_CPU, |
| CLUSTER1_QCH_DBG, |
| CLUSTER1_QCH_LHS_ACE_D_CPUCL1, |
| CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1, |
| CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1, |
| CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1, |
| CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1, |
| CMU_CPUCL1_SHORTSTOP_QCH, |
| CPUCL1_CMU_CPUCL1_QCH, |
| LHM_AXI_P_CPUCL1_QCH, |
| PMU_CPUCL1_QCH, |
| SYSREG_CPUCL1_QCH, |
| CSSYS_QCH, |
| DBG_CMU_DBG_QCH, |
| DUMPPC_CPUCL0_QCH, |
| DUMPPC_CPUCL1_QCH, |
| LHM_ATB_T0_CLUSTER0_QCH, |
| LHM_ATB_T0_CLUSTER1_QCH, |
| LHM_ATB_T1_CLUSTER0_QCH, |
| LHM_ATB_T1_CLUSTER1_QCH, |
| LHM_ATB_T2_CLUSTER0_QCH, |
| LHM_ATB_T2_CLUSTER1_QCH, |
| LHM_ATB_T3_CLUSTER0_QCH, |
| LHM_ATB_T3_CLUSTER1_QCH, |
| LHM_ATB_T_AUD_QCH, |
| LHM_ATB_T_BDU_QCH, |
| LHM_AXI_P_DBG_QCH, |
| LHS_AXI_G_CSSYS_QCH, |
| LHS_AXI_G_ETR_QCH, |
| PMU_DBG_QCH, |
| SECJTAG_QCH, |
| STM_TXACTOR_QCH, |
| SYSREG_DBG_QCH, |
| BTM_DCAM_QCH, |
| DCAM_CMU_DCAM_QCH, |
| DCP_QCH, |
| LHM_AXI_P_SRDZDCAM_QCH, |
| LHS_ATB_DCAMSRDZ_QCH, |
| LHS_AXI_D_DCAMSRDZ_QCH, |
| PMU_DCAM_QCH, |
| BCM_DCAM_QCH, |
| SYSREG_DCAM_QCH, |
| BTM_DPUD0_QCH, |
| BTM_DPUD1_QCH, |
| BTM_DPUD2_QCH, |
| DECON0_QCH, |
| DPP_QCH_DPP_G0, |
| DPP_QCH_DPP_G1, |
| DPP_QCH_DPP_VGR, |
| DPU0_CMU_DPU0_QCH, |
| DPU_DMA_QCH, |
| DPU_WB_MUX_QCH, |
| LHM_AXI_P0_DPU_QCH, |
| LHS_AXI_D0_DPU_QCH, |
| LHS_AXI_D1_DPU_QCH, |
| LHS_AXI_D2_DPU_QCH, |
| LHS_AXI_D_USBTV_QCH, |
| PMU_DPU0_QCH, |
| BCM_DPUD0_QCH, |
| BCM_DPUD1_QCH, |
| BCM_DPUD2_QCH, |
| SYSMMU_DPUD0_QCH, |
| SYSMMU_DPUD1_QCH, |
| SYSMMU_DPUD2_QCH, |
| SYSREG_DPU0_QCH, |
| DECON1_QCH, |
| DECON2_QCH_ACLK, |
| DECON2_QCH_VCLK, |
| DPU1_CMU_DPU1_QCH, |
| LHM_AXI_P_DPU1_QCH, |
| LHS_ATB_DPTX_QCH, |
| PMU_DPU1_QCH, |
| SYSREG_DPU1_QCH, |
| BTM_SCORE_QCH, |
| DSP_CMU_DSP_QCH, |
| LHM_AXI_D_IVADSP_QCH, |
| LHM_AXI_D_VPUDSP_QCH, |
| LHM_AXI_P_DSP_QCH, |
| LHM_AXI_P_IVADSP_QCH, |
| LHS_ACEL_D_DSP_QCH, |
| LHS_AXI_P_DSPIVA_QCH, |
| LHS_AXI_P_DSPVPU_QCH, |
| PMU_DSP_QCH, |
| BCM_SCORE_QCH, |
| SCORE_QCH, |
| SMMU_SCORE_QCH, |
| SYSREG_DSP_QCH, |
| BTM_FSYS0_QCH, |
| DP_LINK_QCH, |
| ETR_MIU_QCH_PCLK, |
| ETR_MIU_QCH_ACLK, |
| FSYS0_CMU_FSYS0_QCH, |
| GPIO_FSYS0_QCH, |
| LHM_AXI_D_USBTV_QCH, |
| LHM_AXI_G_ETR_QCH, |
| LHM_AXI_P_FSYS0_QCH, |
| LHS_ACEL_D_FSYS0_QCH, |
| MMC_EMBD_QCH, |
| PMU_FSYS0_QCH, |
| BCM_FSYS0_QCH, |
| SYSREG_FSYS0_QCH, |
| UFS_EMBD_QCH, |
| UFS_EMBD_QCH_FMP, |
| USBTV_QCH_USB30DRD_LINK, |
| USBTV_QCH_USBTV_HOST, |
| ADM_AHB_SSS_QCH, |
| BTM_FSYS1_QCH, |
| FSYS1_CMU_FSYS1_QCH, |
| GPIO_FSYS1_QCH, |
| LHM_AXI_P_FSYS1_QCH, |
| LHS_ACEL_D_FSYS1_QCH, |
| MMC_CARD_QCH, |
| PCIE_QCH_PCIE0_MSTR, |
| PCIE_QCH_PCIE_PCS, |
| PCIE_QCH_PCIE_PHY, |
| PCIE_QCH_PCIE0_DBI, |
| PCIE_QCH_PCIE0_APB, |
| PCIE_QCH_PCIE_SOCPLL, |
| PCIE_QCH_PCIE1_MSTR, |
| PCIE_QCH_PCIE1_DBI, |
| PCIE_QCH_PCIE1_APB, |
| PMU_FSYS1_QCH, |
| BCM_FSYS1_QCH, |
| RTIC_QCH, |
| SSS_QCH, |
| SYSREG_FSYS1_QCH, |
| TOE_WIFI0_QCH, |
| TOE_WIFI1_QCH, |
| UFS_CARD_QCH, |
| UFS_CARD_QCH_FMP, |
| BTM_G2DD0_QCH, |
| BTM_G2DD1_QCH, |
| BTM_G2DD2_QCH, |
| G2D_QCH, |
| G2D_CMU_G2D_QCH, |
| JPEG_QCH, |
| LHM_AXI_P_G2D_QCH, |
| LHS_ACEL_D0_G2D_QCH, |
| LHS_ACEL_D1_G2D_QCH, |
| LHS_ACEL_D2_G2D_QCH, |
| M2MSCALER_QCH, |
| PMU_G2D_QCH, |
| BCM_G2DD0_QCH, |
| BCM_G2DD1_QCH, |
| BCM_G2DD2_QCH, |
| QE_JPEG_QCH, |
| QE_M2MSCALER_QCH, |
| SMMU_G2DD0_QCH, |
| SMMU_G2DD1_QCH, |
| SMMU_G2DD2_QCH, |
| SYSREG_G2D_QCH, |
| AGPU_QCH_G3D, |
| AGPU_QCH_LHM_AXI_G3DSFR, |
| AGPU_QCH_LHS_ACE_D0_G3D, |
| AGPU_QCH_LHS_ACE_D1_G3D, |
| AGPU_QCH_LHS_ACE_D2_G3D, |
| AGPU_QCH_LHS_ACE_D3_G3D, |
| BUSIF_HPMG3D_QCH, |
| G3D_CMU_G3D_QCH, |
| LHM_AXI_P_G3D_QCH, |
| LHS_AXI_G3DSFR_QCH, |
| PMU_G3D_QCH, |
| SYSREG_G3D_QCH, |
| IMEM_CMU_IMEM_QCH, |
| INTMEM_QCH, |
| LHM_AXI_P_IMEM_QCH, |
| PMU_IMEM_QCH, |
| SYSREG_IMEM_QCH, |
| ISPHQ_CMU_ISPHQ_QCH, |
| ISP_EWGEN_ISPHQ_QCH, |
| IS_ISPHQ_QCH_3AA, |
| IS_ISPHQ_QCH_ISPHQ, |
| IS_ISPHQ_QCH_QE_3AA, |
| IS_ISPHQ_QCH_QE_ISPHQ, |
| LHM_AXI_P_ISPHQ_QCH, |
| LHS_AXI_LD_ISPHQ_QCH, |
| PMU_ISPHQ_QCH, |
| SYSREG_ISPHQ_QCH, |
| BTM_ISPLP_QCH, |
| ISPLP_CMU_ISPLP_QCH, |
| ISP_EWGEN_ISPLP_QCH, |
| IS_ISPLP_QCH_3AAW, |
| IS_ISPLP_QCH_ISPLP, |
| IS_ISPLP_QCH_QE_3AAW, |
| IS_ISPLP_QCH_QE_ISPLP, |
| IS_ISPLP_QCH_SMMU_ISPLP, |
| IS_ISPLP_QCH_BCM_ISPLP, |
| LHM_AXI_LD_ISPHQ_QCH, |
| LHM_AXI_P_ISPLP_QCH, |
| LHS_AXI_D_ISPLP_QCH, |
| PMU_ISPLP_QCH, |
| SYSREG_ISPLP_QCH, |
| BTM_IVA_QCH, |
| IVA_QCH, |
| IVA_CMU_IVA_QCH, |
| IVA_INTMEM_QCH, |
| LHM_AXI_D_IVASC_QCH, |
| LHM_AXI_P_DSPIVA_QCH, |
| LHM_AXI_P_IVA_QCH, |
| LHS_ACEL_D_IVA_QCH, |
| LHS_AXI_D_IVADSP_QCH, |
| LHS_AXI_P_IVADSP_QCH, |
| PMU_IVA_QCH, |
| BCM_IVA_QCH, |
| SMMU_IVA_QCH, |
| SYSREG_IVA_QCH, |
| BTM_MFCD0_QCH, |
| BTM_MFCD1_QCH, |
| LHM_AXI_P_MFC_QCH, |
| LHS_AXI_D0_MFC_QCH, |
| LHS_AXI_D1_MFC_QCH, |
| MFC_QCH, |
| MFC_CMU_MFC_QCH, |
| PMU_MFC_QCH, |
| BCM_MFCD0_QCH, |
| BCM_MFCD1_QCH, |
| SMMU_MFCD0_QCH, |
| SMMU_MFCD1_QCH, |
| SYSREG_MFC_QCH, |
| APBBR_DDRPHY_QCH, |
| APBBR_DMC_QCH, |
| APBBR_DMCTZ_QCH, |
| BUSIF_HPMMIF_QCH, |
| CMU_MIF_CMUREF_QCH, |
| DDRPHY_QCH, |
| DMC_QCH, |
| LHM_AXI_P_MIF_QCH, |
| MIF_CMU_MIF_QCH, |
| PMU_MIF_QCH, |
| BCMPPC_DEBUG_QCH, |
| BCMPPC_DVFS_QCH, |
| SYSREG_MIF_QCH, |
| APBBR_DDRPHY1_QCH, |
| APBBR_DMC1_QCH, |
| APBBR_DMCTZ1_QCH, |
| BUSIF_HPMMIF1_QCH, |
| CMU_MIF1_CMUREF_QCH, |
| DDRPHY1_QCH, |
| DMC1_QCH, |
| LHM_AXI_P_MIF1_QCH, |
| MIF1_CMU_MIF1_QCH, |
| PMU_MIF1_QCH, |
| BCMPPC_DEBUG1_QCH, |
| BCMPPC_DVFS1_QCH, |
| SYSREG_MIF1_QCH, |
| APBBR_DDRPHY2_QCH, |
| APBBR_DMC2_QCH, |
| APBBR_DMCTZ2_QCH, |
| BUSIF_HPMMIF2_QCH, |
| CMU_MIF2_CMUREF_QCH, |
| DDRPHY2_QCH, |
| DMC2_QCH, |
| LHM_AXI_P_MIF2_QCH, |
| MIF2_CMU_MIF2_QCH, |
| PMU_MIF2_QCH, |
| BCMPPC_DEBUG2_QCH, |
| BCMPPC_DVFS2_QCH, |
| SYSREG_MIF2_QCH, |
| APBBR_DDRPHY3_QCH, |
| APBBR_DMC3_QCH, |
| APBBR_DMCTZ3_QCH, |
| BUSIF_HPMMIF3_QCH, |
| CMU_MIF3_CMUREF_QCH, |
| DDRPHY3_QCH, |
| DMC3_QCH, |
| LHM_AXI_P_MIF3_QCH, |
| MIF3_CMU_MIF3_QCH, |
| PMU_MIF3_QCH, |
| BCMPPC_DEBUG3_QCH, |
| BCMPPC_DVFS3_QCH, |
| SYSREG_MIF3_QCH, |
| GPIO_PERIC0_QCH, |
| LHM_AXI_P_PERIC0_QCH, |
| PERIC0_CMU_PERIC0_QCH, |
| PMU_PERIC0_QCH, |
| PWM_QCH, |
| SPEEDY2_TSP_QCH, |
| SYSREG_PERIC0_QCH, |
| UART_DBG_QCH, |
| USI00_QCH, |
| USI01_QCH, |
| USI02_QCH, |
| USI03_QCH, |
| GPIO_PERIC1_QCH, |
| HSI2C_CAM0_QCH, |
| HSI2C_CAM1_QCH, |
| HSI2C_CAM2_QCH, |
| HSI2C_CAM3_QCH, |
| LHM_AXI_P_PERIC1_QCH, |
| PERIC1_CMU_PERIC1_QCH, |
| PMU_PERIC1_QCH, |
| SPEEDY2_DDI_QCH, |
| SPEEDY2_DDI1_QCH, |
| SPEEDY2_DDI2_QCH, |
| SPEEDY2_TSP1_QCH, |
| SPEEDY2_TSP2_QCH, |
| SPI_CAM0_QCH, |
| SPI_CAM1_QCH, |
| SYSREG_PERIC1_QCH, |
| UART_BT_QCH, |
| USI04_QCH, |
| USI05_QCH, |
| USI06_QCH, |
| USI07_QCH, |
| USI08_QCH, |
| USI09_QCH, |
| USI10_QCH, |
| USI11_QCH, |
| USI12_QCH, |
| USI13_QCH, |
| BUSIF_TMU_QCH, |
| GIC_QCH, |
| LHM_AXI_P_PERIS_QCH, |
| MCT_QCH, |
| OTP_CON_BIRA_QCH, |
| OTP_CON_TOP_QCH, |
| PERIS_CMU_PERIS_QCH, |
| PMU_PERIS_QCH, |
| SYSREG_PERIS_QCH, |
| TZPC00_QCH, |
| TZPC01_QCH, |
| TZPC02_QCH, |
| TZPC03_QCH, |
| TZPC04_QCH, |
| TZPC05_QCH, |
| TZPC06_QCH, |
| TZPC07_QCH, |
| TZPC08_QCH, |
| TZPC09_QCH, |
| TZPC10_QCH, |
| TZPC11_QCH, |
| TZPC12_QCH, |
| TZPC13_QCH, |
| TZPC14_QCH, |
| TZPC15_QCH, |
| WDT_CLUSTER0_QCH, |
| WDT_CLUSTER1_QCH, |
| BTM_SRDZ_QCH, |
| LHM_ATB_DCAMSRDZ_QCH, |
| LHM_AXI_D_DCAMSRDZ_QCH, |
| LHM_AXI_P_SRDZ_QCH, |
| LHS_ATB_SRDZCAM_QCH, |
| LHS_AXI_D_SRDZ_QCH, |
| LHS_AXI_P_SRDZDCAM_QCH, |
| PMU_SRDZ_QCH, |
| BCM_SRDZ_QCH, |
| SMMU_SRDZ_QCH, |
| SRDZ_QCH, |
| SRDZ_CMU_SRDZ_QCH, |
| SYSREG_SRDZ_QCH, |
| BTM_VPU_QCH, |
| LHM_AXI_P_DSPVPU_QCH, |
| LHM_AXI_P_VPU_QCH, |
| LHS_ACEL_D_VPU_QCH, |
| LHS_AXI_D_VPUDSP_QCH, |
| PMU_VPU_QCH, |
| BCM_VPU_QCH, |
| SMMU_VPU_QCH, |
| SYSREG_VPU_QCH, |
| VPU_QCH, |
| VPU_CMU_VPU_QCH, |
| CMU_VTS_CMUREF_QCH, |
| DMIC_AHB_QCH_PCLK, |
| DMIC_AHB_QCH_HCLK, |
| DMIC_IF_QCH_PCLK, |
| DMIC_IF_QCH_DMIC_CLK, |
| GPIO_VTS_QCH, |
| LHM_AXI_P_VTS_QCH, |
| LHS_AXI_D_VTS_QCH, |
| MAILBOX_VTS2AP_QCH, |
| SYSREG_VTS_QCH, |
| VTS_QCH_CPU, |
| VTS_QCH_SYS, |
| VTS_QCH_SYS_DMIC, |
| VTS_CMU_VTS_QCH, |
| WDT_VTS_QCH, |
| end_of_qch, |
| num_of_qch = end_of_qch - QCH_TYPE, |
| }; |
| |
| /*=================Controller Option information================================*/ |
| |
| enum option_id { |
| CTRL_OPTION_BLK_ABOX = OPTION_TYPE, |
| CTRL_OPTION_BLK_APM, |
| CTRL_OPTION_BLK_BUS1, |
| CTRL_OPTION_BLK_BUSC, |
| CTRL_OPTION_BLK_CAM, |
| CTRL_OPTION_BLK_CMU, |
| CTRL_OPTION_BLK_CORE, |
| CTRL_OPTION_BLK_CPUCL0, |
| CTRL_OPTION_BLK_CPUCL1, |
| CTRL_OPTION_BLK_DBG, |
| CTRL_OPTION_BLK_DCAM, |
| CTRL_OPTION_BLK_DPU0, |
| CTRL_OPTION_BLK_DPU1, |
| CTRL_OPTION_BLK_DSP, |
| CTRL_OPTION_BLK_FSYS0, |
| CTRL_OPTION_BLK_FSYS1, |
| CTRL_OPTION_BLK_G2D, |
| CTRL_OPTION_BLK_G3D, |
| CTRL_OPTION_BLK_IMEM, |
| CTRL_OPTION_BLK_ISPHQ, |
| CTRL_OPTION_BLK_ISPLP, |
| CTRL_OPTION_BLK_IVA, |
| CTRL_OPTION_BLK_MFC, |
| CTRL_OPTION_BLK_MIF, |
| CTRL_OPTION_BLK_MIF1, |
| CTRL_OPTION_BLK_MIF2, |
| CTRL_OPTION_BLK_MIF3, |
| CTRL_OPTION_BLK_PERIC0, |
| CTRL_OPTION_BLK_PERIC1, |
| CTRL_OPTION_BLK_PERIS, |
| CTRL_OPTION_BLK_SRDZ, |
| CTRL_OPTION_BLK_VPU, |
| CTRL_OPTION_BLK_VTS, |
| end_of_option, |
| num_of_option = end_of_option - OPTION_TYPE, |
| }; |
| |
| #endif |