| #include "../cmucal.h" |
| #include "cmucal-sfr.h" |
| |
| /*=================CMUCAL version: S5E7872================================*/ |
| |
| /*====================The section of SFR Block instance===================*/ |
| struct sfr_block cmucal_sfr_block_list[] __initdata = { |
| SFR_BLOCK(APM, 0x11c00000, 0x8000), |
| SFR_BLOCK(CMU, 0x10560000, 0x8000), |
| SFR_BLOCK(CPUCL0, 0x10900000, 0x8000), |
| SFR_BLOCK(CPUCL1, 0x10800000, 0x8000), |
| SFR_BLOCK(DISPAUD, 0x14800000, 0x8000), |
| SFR_BLOCK(FSYS, 0x13400000, 0x8000), |
| SFR_BLOCK(G3D, 0x11400000, 0x8000), |
| SFR_BLOCK(IS, 0x144b0000, 0x8000), |
| SFR_BLOCK(MFCMSCL, 0x12cb0000, 0x8000), |
| SFR_BLOCK(MIF, 0x10500000, 0x8000), |
| SFR_BLOCK(MODEM, 0x00000000, 0x7000), |
| SFR_BLOCK(PERI, 0x10010000, 0x8000), |
| }; |
| |
| unsigned int cmucal_sfr_block_size = 12; |
| |
| /*====================The section of SFR instance===================*/ |
| struct sfr cmucal_sfr_list[] __initdata = { |
| SFR(PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 0x0100, APM), |
| SFR(PLL_CON2_MUX_CLKCMU_APM_BUS_USER, 0x0108, APM), |
| SFR(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 0x2004, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS, 0x2020, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_INTMEM, 0x201c, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 0x2070, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK, 0x2038, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK, 0x203c, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK, 0x2040, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK, 0x2044, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK, 0x2048, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK, 0x204c, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 0x2068, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, 0x2054, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_NORET_IPCLKPORT_CLK, 0x2058, APM), |
| SFR(CLKOUT_CON_BLK_APM_CMU_CLKOUT0, 0x0810, APM), |
| SFR(CLKOUT_CON_BLK_APM_CMU_CLKOUT1, 0x0814, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_AP_IPCLKPORT_I_PCLK, 0x2030, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_CP_IPCLKPORT_I_PCLK, 0x2034, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MP_APBSEMA_HWACG_2CH_IPCLKPORT_PCLK, 0x2050, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_IPCLKPORT_PCLK, 0x2064, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 0x2014, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 0x2010, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU, 0x2018, APM), |
| SFR(CLK_CON_DIV_DIV_CLK_APM_I2C, 0x1800, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_I2C_APM_IPCLKPORT_PCLK, 0x202c, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKM, 0x2024, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKS, 0x2028, APM), |
| SFR(QCH_CON_APBIF_GPIO_ALIVE_QCH, 0x300c, APM), |
| SFR(QCH_CON_APBIF_PMU_ALIVE_QCH, 0x3010, APM), |
| SFR(QCH_CON_APM_QCH_CPU, 0x3018, APM), |
| SFR(QCH_CON_APM_QCH_INTMEM, 0x3020, APM), |
| SFR(DMYQCH_CON_APM_QCH_OSCCLK, 0x3000, APM), |
| SFR(QCH_CON_APM_QCH_DBG, 0x301c, APM), |
| SFR(QCH_CON_APM_QCH_SYS, 0x3024, APM), |
| SFR(QCH_CON_APM_CMU_APM_QCH, 0x3014, APM), |
| SFR(QCH_CON_I2C_APM_QCH, 0x3028, APM), |
| SFR(QCH_CON_IP_BATCHER_AP_QCH, 0x302c, APM), |
| SFR(QCH_CON_IP_BATCHER_CP_QCH, 0x3030, APM), |
| SFR(QCH_CON_LHM_AXI_P_ALIVE_QCH, 0x3034, APM), |
| SFR(QCH_CON_LHS_AXI_D_ALIVE_QCH, 0x3038, APM), |
| SFR(QCH_CON_MAILBOX_APM2AP_QCH, 0x303c, APM), |
| SFR(QCH_CON_MAILBOX_APM2CP_QCH, 0x3040, APM), |
| SFR(QCH_CON_MAILBOX_APM2GNSS_QCH, 0x3044, APM), |
| SFR(QCH_CON_MAILBOX_APM2WLBT_QCH, 0x3048, APM), |
| SFR(QCH_CON_MP_APBSEMA_HWACG_2CH_QCH, 0x304c, APM), |
| SFR(QCH_CON_SPEEDY_QCH, 0x3050, APM), |
| SFR(DMYQCH_CON_SPEEDY_QCH_OSCCLK, 0x3004, APM), |
| SFR(QCH_CON_SYSREG_APM_QCH, 0x3054, APM), |
| SFR(QCH_CON_WDT_APM_QCH, 0x3058, APM), |
| SFR(DMYQCH_CON_WDT_APM_QCH_OSCCLK, 0x3008, APM), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MSCL, 0x103c, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MSCL, 0x2054, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0x1038, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 0x2050, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 0x2018, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0x1820, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 0x201c, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 0x203c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0x183c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_IS_3AA, 0x1840, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_IS_3AA, 0x2040, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0x1034, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 0x204c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_IS_VRA, 0x184c, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_IS_3AA, 0x1028, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_IS_ISP, 0x102c, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_IS_ISP, 0x2044, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_DISPAUD_BUS, 0x1010, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_BUS, 0x2020, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_DISPAUD_BUS, 0x1824, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, 0x1014, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, 0x101c, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, 0x2030, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, 0x2028, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_FSYS_BUS, 0x182c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0x181c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL, 0x1854, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0x1850, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_IS_ISP, 0x1844, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0, 0x2064, CMU), |
| SFR(CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK, 0x1800, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0x104c, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 0x206c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERI_BUS, 0x1864, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERI_UART_0, 0x1058, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERI_UART_0, 0x2078, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERI_UART_0, 0x1870, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERI_UART_1, 0x1874, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERI_UART_1, 0x105c, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMUC_PERI_UART_1, 0x2000, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0x106c, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 0x2088, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERI_USI2, 0x1884, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_0, 0x1050, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_0, 0x2070, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERI_SPI_0, 0x1868, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_1, 0x1054, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_1, 0x2074, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERI_SPI_1, 0x186c, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 0x2004, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_APM_BUS, 0x1808, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, 0x1018, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, 0x202c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, 0x1830, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CIS_CLK0, 0x180c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CIS_CLK1, 0x1810, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CIS_CLK2, 0x1814, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 0x2008, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 0x200c, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 0x2010, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0x1004, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0x1008, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0x100c, CMU), |
| SFR(CLKOUT_CON_BLK_CMU_CMU_CLKOUT0, 0x0810, CMU), |
| SFR(CLKOUT_CON_BLK_CMU_CMU_CLKOUT1, 0x0814, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, 0x1834, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERI_USI0, 0x1064, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERI_USI0, 0x2080, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERI_USI0, 0x187c, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0x1068, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 0x2084, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERI_USI1, 0x1880, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1, 0x2068, CMU), |
| SFR(CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK, 0x1804, CMU), |
| SFR(CLK_CON_MUX_MUX_CMU_CMUREF, 0x1074, CMU), |
| SFR(CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0x1070, CMU), |
| SFR(CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0x1888, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0x1000, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_DISPAUD_CPU, 0x1828, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_VCLK, 0x2024, CMU), |
| SFR(PLL_CON0_PLL_SHARED0, 0x0100, CMU), |
| SFR(PLL_LOCKTIME_PLL_SHARED0, 0x0000, CMU), |
| SFR(PLL_CON0_PLL_SHARED1, 0x0120, CMU), |
| SFR(PLL_LOCKTIME_PLL_SHARED1, 0x0004, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0x1048, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_MIF_BUS, 0x1040, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_MIF_CCI, 0x205c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_MIF_CCI, 0x185c, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_MIF_CCI, 0x1044, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_IS_TPU, 0x1848, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_IS_TPU, 0x2048, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_IS_TPU, 0x1030, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH, 0x2060, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_MIF_SWITCH, 0x1860, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO, 0x1020, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO, 0x2034, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO, 0x1838, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_MIF_BUS, 0x2058, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_MIF_BUS, 0x1858, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERI_UART_2, 0x1060, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERI_UART_2, 0x207c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERI_UART_2, 0x1878, CMU), |
| SFR(CLK_CON_DIV_PLL_SHARED0_DIV3, 0x1890, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CPUCL0_SECJTAG, 0x1818, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SECJTAG, 0x2014, CMU), |
| SFR(CLK_CON_DIV_PLL_SHARED0_DIV2, 0x188c, CMU), |
| SFR(CLK_CON_DIV_PLL_SHARED0_DIV4, 0x1894, CMU), |
| SFR(CLK_CON_DIV_PLL_SHARED1_DIV2, 0x1898, CMU), |
| SFR(CLK_CON_DIV_PLL_SHARED1_DIV4, 0x189c, CMU), |
| SFR(DMYQCH_CON_CMU_CMU_CMUREF_QCH, 0x3000, CMU), |
| SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0, 0x3004, CMU), |
| SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1, 0x3008, CMU), |
| SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2, 0x300c, CMU), |
| SFR(PLL_CON0_PLL_CPUCL0, 0x0140, CPUCL0), |
| SFR(PLL_LOCKTIME_PLL_CPUCL0, 0x0000, CPUCL0), |
| SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x0120, CPUCL0), |
| SFR(PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x0128, CPUCL0), |
| SFR(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0x1000, CPUCL0), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, 0x1814, CPUCL0), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, 0x1808, CPUCL0), |
| SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, 0x2000, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK, 0x202c, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, 0x2058, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK, 0x204c, CPUCL0), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_ACLK, 0x1800, CPUCL0), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_ATCLK, 0x1804, CPUCL0), |
| SFR(CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0, 0x0810, CPUCL0), |
| SFR(CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1, 0x0814, CPUCL0), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_CNTCLK, 0x180c, CPUCL0), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG, 0x181c, CPUCL0), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0x1810, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK, 0x2038, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CPUCL0_IPCLKPORT_I_CLK, 0x203c, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_P_CSSYS_DBG_IPCLKPORT_PCLKM, 0x2010, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG, 0x2030, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_T_CSSYS_DBG_IPCLKPORT_I_CLK, 0x2040, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLKDBG_IPCLKPORT_CLK, 0x2048, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_DBG_IPCLKPORT_PCLKS, 0x2018, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM, 0x201c, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKS, 0x2020, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_ACLK_IPCLKPORT_CLK, 0x2044, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK, 0x2034, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLK, 0x2014, CPUCL0), |
| SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_SECJTAG_USER, 0x0100, CPUCL0), |
| SFR(PLL_CON2_MUX_CLKCMU_CPUCL0_SECJTAG_USER, 0x0108, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL_SECJTAG_IPCLKPORT_CLK, 0x2050, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKM, 0x2024, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKS, 0x2028, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK, 0x2054, CPUCL0), |
| SFR(DMYQCH_CON_CLUSTER0_QCH_CPU, 0x3000, CPUCL0), |
| SFR(DMYQCH_CON_CLUSTER0_QCH_DBG, 0x3004, CPUCL0), |
| SFR(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH, 0x3010, CPUCL0), |
| SFR(QCH_CON_CPUCL0_CMU_CPUCL0_QCH, 0x3014, CPUCL0), |
| SFR(DMYQCH_CON_CSSYS_DBG_QCH, 0x3008, CPUCL0), |
| SFR(QCH_CON_DUMP_PC_CPUCL0_QCH, 0x3018, CPUCL0), |
| SFR(QCH_CON_LHM_AXI_P_CPUCL0_QCH, 0x301c, CPUCL0), |
| SFR(QCH_CON_LHS_ACE_D_CPUCL0_QCH, 0x3020, CPUCL0), |
| SFR(QCH_CON_LHS_AXI_T_CSSYS_DBG_QCH, 0x3024, CPUCL0), |
| SFR(QCH_CON_SECJTAG_QCH, 0x3028, CPUCL0), |
| SFR(QCH_CON_SYSREG_CPUCL0_QCH, 0x302c, CPUCL0), |
| SFR(PLL_CON0_PLL_CPUCL1, 0x0120, CPUCL1), |
| SFR(PLL_LOCKTIME_PLL_CPUCL1, 0x0000, CPUCL1), |
| SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, 0x1000, CPUCL1), |
| SFR(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x0100, CPUCL1), |
| SFR(PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x0108, CPUCL1), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, 0x1814, CPUCL1), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, 0x1808, CPUCL1), |
| SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, 0x2014, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK, 0x2040, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK, 0x2054, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK, 0x2050, CPUCL1), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_ACLK, 0x1800, CPUCL1), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_ATCLK, 0x1804, CPUCL1), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG, 0x1818, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK, 0x2044, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK, 0x2030, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK, 0x2048, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK, 0x204c, CPUCL1), |
| SFR(CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1, 0x0814, CPUCL1), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, 0x1810, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CPUCL1_IPCLKPORT_PCLKM, 0x2024, CPUCL1), |
| SFR(CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0, 0x0810, CPUCL1), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_CNTCLK, 0x180c, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM, 0x2028, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKS, 0x202c, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK, 0x203c, CPUCL1), |
| SFR(DMYQCH_CON_CLUSTER1_QCH_CPU, 0x3000, CPUCL1), |
| SFR(DMYQCH_CON_CLUSTER1_QCH_DBG, 0x3004, CPUCL1), |
| SFR(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH, 0x300c, CPUCL1), |
| SFR(QCH_CON_CPUCL1_CMU_CPUCL1_QCH, 0x3010, CPUCL1), |
| SFR(QCH_CON_DUMP_PC_CPUCL1_QCH, 0x3014, CPUCL1), |
| SFR(QCH_CON_LHM_AXI_P_CPUCL1_QCH, 0x3018, CPUCL1), |
| SFR(QCH_CON_LHS_ACE_D_CPUCL1_QCH, 0x301c, CPUCL1), |
| SFR(QCH_CON_SYSREG_CPUCL1_QCH, 0x3020, CPUCL1), |
| SFR(CLK_CON_DIV_DIV_CLK_AUD_BUS, 0x1804, DISPAUD), |
| SFR(CLK_CON_DIV_DIV_CLK_AUD_PLL, 0x1814, DISPAUD), |
| SFR(CLK_CON_MUX_MUX_CLK_AUD_CPU, 0x1000, DISPAUD), |
| SFR(PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 0x0100, DISPAUD), |
| SFR(PLL_CON2_MUX_CLKCMU_AUD_CPU_USER, 0x0108, DISPAUD), |
| SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0x180c, DISPAUD), |
| SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0x1808, DISPAUD), |
| SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0x1818, DISPAUD), |
| SFR(CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0x1800, DISPAUD), |
| SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0x181c, DISPAUD), |
| SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0x1820, DISPAUD), |
| SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0x1008, DISPAUD), |
| SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0x100c, DISPAUD), |
| SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0x1010, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0, 0x2014, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3, 0x201c, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7, 0x2024, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB, 0x2020, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK, 0x200c, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK, 0x2068, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK, 0x20b8, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK, 0x20bc, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK, 0x20c0, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK, 0x20b0, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_PCLKDBG_IPCLKPORT_CLK, 0x20b4, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_BUS_IPCLKPORT_CLK, 0x20a8, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM, 0x208c, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK, 0x2094, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_ABOXCPU_IPCLKPORT_PCLK, 0x20dc, DISPAUD), |
| SFR(CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT0, 0x0810, DISPAUD), |
| SFR(CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT1, 0x0814, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2, 0x2018, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK, 0x206c, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_ACLK, 0x2098, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_PCLK, 0x209c, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK, 0x20cc, DISPAUD), |
| SFR(CLK_CON_DIV_DIV_CLK_AUD_FM, 0x1810, DISPAUD), |
| SFR(PLL_CON0_MUX_CLKCMU_DISPAUD_BUS_USER, 0x0120, DISPAUD), |
| SFR(PLL_CON2_MUX_CLKCMU_DISPAUD_BUS_USER, 0x0168, DISPAUD), |
| SFR(CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP, 0x1824, DISPAUD), |
| SFR(PLL_CON0_PLL_AUD, 0x01e0, DISPAUD), |
| SFR(PLL_CON3_PLL_AUD, 0x024c, DISPAUD), |
| SFR(PLL_LOCKTIME_PLL_AUD, 0x0000, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKS, 0x202c, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKM, 0x2028, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS, 0x2034, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM, 0x2030, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKS, 0x203c, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKM, 0x2038, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS, 0x2044, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM, 0x2040, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS, 0x204c, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM, 0x2048, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DSIM0_IPCLKPORT_PCLKS, 0x2050, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI2APB_DISPAUD_IPCLKPORT_ACLK, 0x2064, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP, 0x2078, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA, 0x2074, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON0, 0x2070, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_DPU_IPCLKPORT_I_CLK, 0x2088, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS, 0x2090, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSD_IPCLKPORT_CLK, 0x20c4, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK, 0x20c8, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_ACLK, 0x20a0, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_PCLK, 0x20a4, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK, 0x20d0, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK, 0x20d8, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_XIU_P_DISPAUD_IPCLKPORT_ACLK, 0x20e0, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK, 0x2080, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK, 0x2084, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK, 0x20ac, DISPAUD), |
| SFR(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK, 0x2000, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK, 0x2008, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY, 0x2010, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKM, 0x2054, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKS, 0x2058, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKM, 0x205c, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKS, 0x2060, DISPAUD), |
| SFR(CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0x1004, DISPAUD), |
| SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK, 0x207c, DISPAUD), |
| SFR(DMYQCH_CON_ABOX_QCH_ABOX, 0x3000, DISPAUD), |
| SFR(DMYQCH_CON_ABOX_QCH_CPU, 0x3004, DISPAUD), |
| SFR(QCH_CON_ABOX_QCH_BUS, 0x300c, DISPAUD), |
| SFR(QCH_CON_ABOX_QCH_UAIF0, 0x3010, DISPAUD), |
| SFR(QCH_CON_ABOX_QCH_UAIF2, 0x3014, DISPAUD), |
| SFR(QCH_CON_ABOX_QCH_UAIF3, 0x3018, DISPAUD), |
| SFR(DMYQCH_CON_ABOX_QCH_FM, 0x3008, DISPAUD), |
| SFR(QCH_CON_DISPAUD_CMU_DISPAUD_QCH, 0x301c, DISPAUD), |
| SFR(QCH_CON_DPU_QCH_DPP, 0x3028, DISPAUD), |
| SFR(QCH_CON_DPU_QCH_DMA, 0x3024, DISPAUD), |
| SFR(QCH_CON_DPU_QCH_DECON0, 0x3020, DISPAUD), |
| SFR(QCH_CON_GPIO_DISPAUD_QCH, 0x302c, DISPAUD), |
| SFR(QCH_CON_LHM_AXI_P_DISPAUD_QCH, 0x3030, DISPAUD), |
| SFR(QCH_CON_LHS_AXI_D_ABOX_QCH, 0x3034, DISPAUD), |
| SFR(QCH_CON_LHS_AXI_D_DPU_QCH, 0x3038, DISPAUD), |
| SFR(QCH_CON_BCM_ABOX_QCH, 0x303c, DISPAUD), |
| SFR(QCH_CON_BCM_DPU_QCH, 0x3040, DISPAUD), |
| SFR(QCH_CON_SMMU_ABOX_QCH, 0x3044, DISPAUD), |
| SFR(QCH_CON_SMMU_DPU_QCH, 0x3048, DISPAUD), |
| SFR(QCH_CON_SYSREG_DISPAUD_QCH, 0x304c, DISPAUD), |
| SFR(QCH_CON_WDT_ABOXCPU_QCH, 0x3050, DISPAUD), |
| SFR(PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, 0x0100, FSYS), |
| SFR(PLL_CON2_MUX_CLKCMU_FSYS_BUS_USER, 0x0108, FSYS), |
| SFR(CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK, 0x2000, FSYS), |
| SFR(PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER, 0x0120, FSYS), |
| SFR(PLL_CON2_MUX_CLKCMU_FSYS_MMC_CARD_USER, 0x0128, FSYS), |
| SFR(PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER, 0x0140, FSYS), |
| SFR(PLL_CON2_MUX_CLKCMU_FSYS_MMC_EMBD_USER, 0x0148, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK, 0x205c, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK, 0x2058, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK, 0x2050, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK, 0x2054, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK, 0x202c, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN, 0x2030, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK, 0x2034, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN, 0x2038, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_BUS_CLK_EARLY, 0x2068, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_PHYCTRL, 0x2064, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK, 0x204c, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_AXI2AHB_FSYS_IPCLKPORT_ACLK, 0x201c, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_1X4_IPCLKPORT_HCLK, 0x2014, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_IPCLKPORT_HCLK, 0x2018, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK, 0x2020, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK, 0x2024, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_AXI_D_FSYS_IPCLKPORT_I_CLK, 0x2028, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_ACLK, 0x2044, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_PCLK, 0x2048, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK, 0x2060, FSYS), |
| SFR(CLKOUT_CON_BLK_FSYS_CMU_CLKOUT0, 0x0810, FSYS), |
| SFR(CLKOUT_CON_BLK_FSYS_CMU_CLKOUT1, 0x0814, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK, 0x2070, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHB2APB_FSYS_IPCLKPORT_HCLK, 0x2010, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, 0x200c, FSYS), |
| SFR(PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER, 0x0160, FSYS), |
| SFR(PLL_CON2_MUX_CLKCMU_FSYS_MMC_SDIO_USER, 0x0168, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_SDCLKIN, 0x2040, FSYS), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_I_ACLK, 0x203c, FSYS), |
| SFR(QCH_CON_ADM_AHB_SSS_QCH, 0x3000, FSYS), |
| SFR(QCH_CON_FSYS_CMU_FSYS_QCH, 0x3004, FSYS), |
| SFR(QCH_CON_GPIO_FSYS_QCH, 0x3008, FSYS), |
| SFR(QCH_CON_LHM_AXI_P_FSYS_QCH, 0x300c, FSYS), |
| SFR(QCH_CON_LHS_AXI_D_FSYS_QCH, 0x3010, FSYS), |
| SFR(QCH_CON_MMC_CARD_QCH, 0x3014, FSYS), |
| SFR(QCH_CON_MMC_EMBD_QCH, 0x3018, FSYS), |
| SFR(QCH_CON_MMC_SDIO_QCH, 0x301c, FSYS), |
| SFR(QCH_CON_BCM_FSYS_QCH, 0x3020, FSYS), |
| SFR(QCH_CON_RTIC_QCH, 0x3024, FSYS), |
| SFR(QCH_CON_SSS_QCH, 0x3028, FSYS), |
| SFR(QCH_CON_SYSREG_FSYS_QCH, 0x302c, FSYS), |
| SFR(QCH_CON_USB20DRD_QCH_HSDRD, 0x3030, FSYS), |
| SFR(QCH_CON_USB20DRD_QCH_USB, 0x3034, FSYS), |
| SFR(CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0x1800, G3D), |
| SFR(PLL_CON0_PLL_G3D, 0x0120, G3D), |
| SFR(PLL_LOCKTIME_PLL_G3D, 0x0000, G3D), |
| SFR(CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0x1004, G3D), |
| SFR(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 0x0100, G3D), |
| SFR(PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER, 0x0108, G3D), |
| SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, 0x2004, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK, 0x2024, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK, 0x201c, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, 0x2034, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK, 0x2038, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, 0x202c, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK, 0x2014, G3D), |
| SFR(CLKOUT_CON_BLK_G3D_CMU_CLKOUT0, 0x0810, G3D), |
| SFR(CLKOUT_CON_BLK_G3D_CMU_CLKOUT1, 0x0814, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_GPU_IPCLKPORT_CLK, 0x2030, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK, 0x2028, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK, 0x2020, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK, 0x2018, G3D), |
| SFR(QCH_CON_AGPU_QCH, 0x3000, G3D), |
| SFR(QCH_CON_G3D_CMU_G3D_QCH, 0x3004, G3D), |
| SFR(QCH_CON_LHM_AXI_G3DSFR_QCH, 0x3008, G3D), |
| SFR(QCH_CON_LHM_AXI_P_G3D_QCH, 0x300c, G3D), |
| SFR(QCH_CON_LHS_AXI_D_G3D_QCH, 0x3010, G3D), |
| SFR(QCH_CON_LHS_AXI_G3DSFR_QCH, 0x3014, G3D), |
| SFR(QCH_CON_SYSREG_G3D_QCH, 0x3018, G3D), |
| SFR(PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 0x01e0, IS), |
| SFR(PLL_CON2_MUX_CLKCMU_IS_VRA_USER, 0x0228, IS), |
| SFR(CLK_CON_DIV_DIV_CLK_IS_APB, 0x1804, IS), |
| SFR(CLK_CON_GAT_CLK_BLK_IS_UID_IS_CMU_IS_IPCLKPORT_PCLK, 0x2004, IS), |
| SFR(PLL_CON0_MUX_CLKCMU_IS_ISP_USER, 0x0120, IS), |
| SFR(PLL_CON2_MUX_CLKCMU_IS_ISP_USER, 0x0168, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCM_P_IS_IPCLKPORT_I_CLK, 0x2010, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_SYSREG_IS_IPCLKPORT_PCLK, 0x208c, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_VRA, 0x2058, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_VRA_IPCLKPORT_CLK, 0x2084, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_APB_IPCLKPORT_CLK, 0x2078, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_PCLK_IS, 0x2060, IS), |
| SFR(CLKOUT_CON_BLK_IS_CMU_CLKOUT0, 0x0810, IS), |
| SFR(CLKOUT_CON_BLK_IS_CMU_CLKOUT1, 0x0814, IS), |
| SFR(PLL_CON0_MUX_CLKCMU_IS_3AA_USER, 0x0100, IS), |
| SFR(PLL_CON2_MUX_CLKCMU_IS_3AA_USER, 0x0108, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D1_IS_IPCLKPORT_I_CLK, 0x2018, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D0_IS_IPCLKPORT_I_CLK, 0x2014, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_3AA_IPCLKPORT_CLK, 0x2074, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_XIU_IS_D, 0x205c, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0, 0x203c, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0_HALF, 0x2040, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1, 0x2044, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1_HALF, 0x2048, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_3AA, 0x201c, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_DMA, 0x204c, IS), |
| SFR(PLL_CON0_MUX_CLKCMU_IS_TPU_USER, 0x0180, IS), |
| SFR(PLL_CON2_MUX_CLKCMU_IS_TPU_USER, 0x01c8, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_TPU, 0x2054, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_SMMU_IS_IPCLKPORT_ACLK, 0x2088, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_ACLK, 0x206c, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_PCLK, 0x2070, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_ACLK, 0x2064, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_PCLK, 0x2068, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_TPU_IPCLKPORT_CLK, 0x2080, IS), |
| SFR(CLK_CON_GAT_CLK_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS1_ISP, 0x2000, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_3AA, 0x2020, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_CSIS, 0x2024, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_VRA, 0x2038, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_TPU, 0x2034, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_RT, 0x2030, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_NRT, 0x202c, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_MCSC, 0x2028, IS), |
| SFR(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_MCSC, 0x2050, IS), |
| SFR(CLK_CON_DIV_DIV_CLK_IS_3AA_HALF, 0x1800, IS), |
| SFR(QCH_CON_ASYNCM_P_IS_QCH, 0x3000, IS), |
| SFR(QCH_CON_ASYNCS_D0_IS_QCH, 0x3004, IS), |
| SFR(QCH_CON_ASYNCS_D1_IS_QCH, 0x3008, IS), |
| SFR(QCH_CON_IS_CMU_IS_QCH, 0x302c, IS), |
| SFR(QCH_CON_BCM_NRT_QCH, 0x3030, IS), |
| SFR(QCH_CON_BCM_RT_QCH, 0x3034, IS), |
| SFR(QCH_CON_SMMU_IS_QCH, 0x3038, IS), |
| SFR(QCH_CON_SYSREG_IS_QCH, 0x303c, IS), |
| SFR(QCH_CON_IS5P15P0_IS_QCH_ISP, 0x3018, IS), |
| SFR(QCH_CON_IS5P15P0_IS_QCH_MCSC, 0x3020, IS), |
| SFR(QCH_CON_IS5P15P0_IS_QCH_VRA, 0x3028, IS), |
| SFR(QCH_CON_IS5P15P0_IS_QCH_CSIS_0, 0x300c, IS), |
| SFR(QCH_CON_IS5P15P0_IS_QCH_CSIS_1, 0x3010, IS), |
| SFR(QCH_CON_IS5P15P0_IS_QCH_IS_3AA, 0x301c, IS), |
| SFR(QCH_CON_IS5P15P0_IS_QCH_TPU, 0x3024, IS), |
| SFR(QCH_CON_IS5P15P0_IS_QCH_CSIS_DMA, 0x3014, IS), |
| SFR(PLL_CON0_MUX_CLKCMU_MFCMSCL_MSCL_USER, 0x0120, MFCMSCL), |
| SFR(PLL_CON2_MUX_CLKCMU_MFCMSCL_MSCL_USER, 0x0128, MFCMSCL), |
| SFR(CLK_CON_DIV_DIV_CLK_MFCMSCL_APB, 0x1800, MFCMSCL), |
| SFR(CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT0, 0x0810, MFCMSCL), |
| SFR(CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT1, 0x0814, MFCMSCL), |
| SFR(CLK_CON_GAT_CLK_BLK_MFCMSCL_UID_MFCMSCL_CMU_MFCMSCL_IPCLKPORT_PCLK, 0x2000, MFCMSCL), |
| SFR(PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 0x0100, MFCMSCL), |
| SFR(PLL_CON2_MUX_CLKCMU_MFCMSCL_MFC_USER, 0x0108, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHM_AXI_P_MFCMSCL_IPCLKPORT_I_CLK, 0x2050, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKM, 0x2024, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKS, 0x2028, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKS, 0x2020, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKM, 0x202c, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKS, 0x2030, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_AXI2APB_MFCMSCL_IPCLKPORT_ACLK, 0x2044, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MFC_IPCLKPORT_CLK, 0x2058, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SYSREG_MFCMSCL_IPCLKPORT_PCLK, 0x2078, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MFC_IPCLKPORT_CLK, 0x206c, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MSCL_IPCLKPORT_CLK, 0x2070, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKS, 0x2038, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_APB_IPCLKPORT_CLK, 0x2068, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKS, 0x2018, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_G2D_IPCLKPORT_CLK, 0x2048, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_PCLK, 0x2064, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_ACLK, 0x2060, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SMMU_MFCMSCL_IPCLKPORT_CLK, 0x2074, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_XIU_D_MFCMSCL_IPCLKPORT_ACLK, 0x207c, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKM, 0x2014, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKM, 0x201c, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_JPEG_IPCLKPORT_I_FIMP_CLK, 0x204c, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHS_AXI_D_MFCMSCL_IPCLKPORT_I_CLK, 0x2054, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKM, 0x2034, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MSCL_IPCLKPORT_ACLK, 0x205c, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKM, 0x203c, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKS, 0x2040, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKM, 0x200c, MFCMSCL), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKS, 0x2010, MFCMSCL), |
| SFR(QCH_CON_G2D_QCH, 0x3000, MFCMSCL), |
| SFR(QCH_CON_JPEG_QCH, 0x3004, MFCMSCL), |
| SFR(QCH_CON_LHM_AXI_P_MFCMSCL_QCH, 0x3008, MFCMSCL), |
| SFR(QCH_CON_LHS_AXI_D_MFCMSCL_QCH, 0x300c, MFCMSCL), |
| SFR(QCH_CON_MFC_QCH, 0x3014, MFCMSCL), |
| SFR(QCH_CON_MFCMSCL_CMU_MFCMSCL_QCH, 0x3010, MFCMSCL), |
| SFR(QCH_CON_MSCL_QCH, 0x3018, MFCMSCL), |
| SFR(QCH_CON_BCM_MFCMSCL_QCH, 0x301c, MFCMSCL), |
| SFR(QCH_CON_SMMU_MFCMSCL_QCH, 0x3020, MFCMSCL), |
| SFR(QCH_CON_SYSREG_MFCMSCL_QCH, 0x3024, MFCMSCL), |
| SFR(CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X, 0x1008, MIF), |
| SFR(CLK_CON_MUX_MUX_MIF_CMUREF, 0x1010, MIF), |
| SFR(CLKOUT_CON_BLK_MIF_CMU_CLKOUT0, 0x0810, MIF), |
| SFR(PLL_CON0_PLL_MEM, 0x0160, MIF), |
| SFR(PLL_LOCKTIME_PLL_MEM, 0x0000, MIF), |
| SFR(CLK_CON_DIV_PLL_MEM_DIV2, 0x1810, MIF), |
| SFR(CLK_CON_MUX_MUX_CLK_MIF_BUS, 0x1000, MIF), |
| SFR(CLK_CON_DIV_DIV_CLK_MIF_BUS, 0x1800, MIF), |
| SFR(CLK_CON_DIV_DIV_CLK_MIF_BUSP, 0x1804, MIF), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, 0x2010, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK, 0x213c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB_BRIDGE_IPCLKPORT_HCLK, 0x2048, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_COREP0_IPCLKPORT_HCLK, 0x2040, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_COREP_IPCLKPORT_ACLK, 0x204c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_2MB_BUSCP_IPCLKPORT_ACLK, 0x2054, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_CCI_400_IPCLKPORT_ACLK, 0x206c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK, 0x209c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK, 0x20a0, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK, 0x20a8, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK, 0x20b0, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK, 0x20ac, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK, 0x20bc, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_DPU_IPCLKPORT_I_CLK, 0x20b4, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_FSYS_IPCLKPORT_I_CLK, 0x20b8, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK, 0x20c0, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPNRT_IPCLKPORT_I_CLK, 0x20c4, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPRT_IPCLKPORT_I_CLK, 0x20c8, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_MFCMSCL_IPCLKPORT_I_CLK, 0x20cc, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK, 0x20d0, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK, 0x20dc, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK, 0x20e0, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK, 0x20e4, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK, 0x20e8, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK, 0x20ec, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_IS_IPCLKPORT_I_CLK, 0x20f0, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_MFCMSCL_IPCLKPORT_I_CLK, 0x20f4, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK, 0x20f8, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_IPCLKPORT_PCLK, 0x2104, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_GNSSS_IPCLKPORT_PCLK, 0x2100, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT0_IPCLKPORT_PCLK, 0x210c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0, 0x2114, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_ACLK, 0x2118, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_PCLK, 0x211c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_ACLK, 0x2120, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_PCLK, 0x2124, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1, 0x2150, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, 0x2158, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_ACLK, 0x215c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_PCLK, 0x2164, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_ACLK, 0x2168, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_PCLK, 0x2170, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_CCLK, 0x216c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0, 0x2174, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1, 0x2178, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_HCLK_AHB2APB_BRIDGE_MIF, 0x207c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_DDR_PHY0_PCLK, 0x2078, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_DMC0, 0x2088, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_SECURE_DMC0, 0x2094, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PF_DMC0, 0x208c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PPMPU_DMC0, 0x2090, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_PCLK, 0x2108, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_CCI_IPCLKPORT_CLK, 0x2140, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK, 0x2138, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_PHY_CLK2X_IPCLKPORT_CLK, 0x2148, MIF), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_ACLK, 0x200c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_PCLK, 0x2098, MIF), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_ACLK_DMC0, 0x2004, MIF), |
| SFR(PLL_CON0_MUX_CLKCMU_MIF_SWITCH_USER, 0x0120, MIF), |
| SFR(PLL_CON2_MUX_CLKCMU_MIF_SWITCH_USER, 0x0128, MIF), |
| SFR(PLL_CON0_MUX_CLKCMU_MIF_BUS_USER, 0x0100, MIF), |
| SFR(PLL_CON2_MUX_CLKCMU_MIF_BUS_USER, 0x0108, MIF), |
| SFR(PLL_CON0_MUX_CLK_MIF_CCI_USER, 0x0140, MIF), |
| SFR(PLL_CON2_MUX_CLK_MIF_CCI_USER, 0x0148, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK, 0x20d8, MIF), |
| SFR(CLK_CON_MUX_MUX_CLK_MIF_GIC, 0x100c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_GIC400_AIHWACG_IPCLKPORT_CLK, 0x2070, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKS, 0x2058, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_I_PCLK_ASYNCSFR_WR_DMC_SECURE, 0x2080, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_APBBR_DMC_SECURE, 0x2084, MIF), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKM, 0x2000, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK, 0x20a4, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK, 0x20d4, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_PDMA_IPCLKPORT_ACLK, 0x2060, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_SDMA_IPCLKPORT_ACLK, 0x2064, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_64TO128_CSSYS_IPCLKPORT_ACLK, 0x2068, MIF), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_DDRPHY_IPCLKPORT_CLK, 0x2014, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_MCLK, 0x2160, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_XIU_D_PDMA_3X1_IPCLKPORT_ACLK, 0x217c, MIF), |
| SFR(CLK_CON_DIV_DIV_CLK_MIF_PHY_CLKM, 0x180c, MIF), |
| SFR(CLKOUT_CON_BLK_MIF_CMU_CLKOUT1, 0x0814, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_ACLK, 0x2128, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_PCLK, 0x212c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS, 0x2028, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM, 0x2024, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM, 0x202c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKS, 0x2038, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_PCLK, 0x203c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_ADS_APB_G_CSSYS_IPCLKPORT_PCLKS, 0x2020, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_CSSYS_DBG_IPCLKPORT_HCLK, 0x2044, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_PCLK, 0x205c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_PCLK, 0x2134, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_CORE_CSSYS_IPCLKPORT_ACLK, 0x2050, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_GIC_IPCLKPORT_CLK, 0x2144, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS, 0x2030, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_CLK, 0x2074, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_ACLK, 0x2130, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKM, 0x2034, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFR_APBIF_CMU_CMU_IPCLKPORT_PCLK, 0x214c, MIF), |
| SFR(CLK_CON_MUX_MUX_CLK_MIF_CCI, 0x1004, MIF), |
| SFR(CLK_CON_DIV_DIV_CLK_MIF_CCI, 0x1808, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_ABOX_IPCLKPORT_PCLK, 0x20fc, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT1_IPCLKPORT_PCLK, 0x2110, MIF), |
| SFR(CLK_CON_GAT_CLK_MIF_PHY_CLKM, 0x201c, MIF), |
| SFR(DMYQCH_CON_AXI2AHB_CORE_CSSYS_QCH, 0x3000, MIF), |
| SFR(QCH_CON_CCI_400_QCH, 0x3010, MIF), |
| SFR(DMYQCH_CON_CMU_MIF_CMUREF_QCH, 0x3004, MIF), |
| SFR(QCH_CON_GIC400_AIHWACG_QCH, 0x3014, MIF), |
| SFR(QCH_CON_LBLK_MIF_QCH_DMC, 0x301c, MIF), |
| SFR(QCH_CON_LBLK_MIF_QCH_BCM, 0x3020, MIF), |
| SFR(QCH_CON_LBLK_MIF_QCH_APBBR, 0x3018, MIF), |
| SFR(DMYQCH_CON_LBLK_MIF_QCH_ASYNCSFR, 0x3008, MIF), |
| SFR(QCH_CON_LHM_ACE_D_CPUCL0_QCH, 0x3024, MIF), |
| SFR(QCH_CON_LHM_ACE_D_CPUCL1_QCH, 0x3028, MIF), |
| SFR(QCH_CON_LHM_AXI_D_ABOX_QCH, 0x302c, MIF), |
| SFR(QCH_CON_LHM_AXI_D_APM_QCH, 0x3030, MIF), |
| SFR(QCH_CON_LHM_AXI_D_CP_QCH, 0x3034, MIF), |
| SFR(QCH_CON_LHM_AXI_D_CSSYS_QCH, 0x3038, MIF), |
| SFR(QCH_CON_LHM_AXI_D_DPU_QCH, 0x303c, MIF), |
| SFR(QCH_CON_LHM_AXI_D_FSYS_QCH, 0x3040, MIF), |
| SFR(QCH_CON_LHM_AXI_D_G3D_QCH, 0x3044, MIF), |
| SFR(QCH_CON_LHM_AXI_D_GNSS_QCH, 0x3048, MIF), |
| SFR(QCH_CON_LHM_AXI_D_ISPNRT_QCH, 0x304c, MIF), |
| SFR(QCH_CON_LHM_AXI_D_ISPRT_QCH, 0x3050, MIF), |
| SFR(QCH_CON_LHM_AXI_D_MFCMSCL_QCH, 0x3054, MIF), |
| SFR(QCH_CON_LHM_AXI_D_WLBT_QCH, 0x3058, MIF), |
| SFR(QCH_CON_LHM_AXI_P_CP_QCH, 0x305c, MIF), |
| SFR(QCH_CON_LHS_AXI_P_APM_QCH, 0x3060, MIF), |
| SFR(QCH_CON_LHS_AXI_P_CPUCL0_QCH, 0x3064, MIF), |
| SFR(QCH_CON_LHS_AXI_P_CPUCL1_QCH, 0x3068, MIF), |
| SFR(QCH_CON_LHS_AXI_P_DISPAUD_QCH, 0x306c, MIF), |
| SFR(QCH_CON_LHS_AXI_P_FSYS_QCH, 0x3070, MIF), |
| SFR(QCH_CON_LHS_AXI_P_G3D_QCH, 0x3074, MIF), |
| SFR(QCH_CON_LHS_AXI_P_IS_QCH, 0x3078, MIF), |
| SFR(QCH_CON_LHS_AXI_P_MFCMSCL_QCH, 0x307c, MIF), |
| SFR(QCH_CON_LHS_AXI_P_PERI_QCH, 0x3080, MIF), |
| SFR(QCH_CON_MAILBOX_QCH_S0, 0x308c, MIF), |
| SFR(QCH_CON_MAILBOX_ABOX_QCH_S0, 0x3084, MIF), |
| SFR(QCH_CON_MAILBOX_GNSSS_QCH_S0, 0x3088, MIF), |
| SFR(QCH_CON_MAILBOX_SECURE_QCH_S0, 0x3090, MIF), |
| SFR(QCH_CON_MAILBOX_WLBT0_QCH_S0, 0x3094, MIF), |
| SFR(QCH_CON_MAILBOX_WLBT1_QCH_S0, 0x3098, MIF), |
| SFR(QCH_CON_MIF_CMU_MIF_QCH, 0x309c, MIF), |
| SFR(QCH_CON_PDMA_CORE_QCH, 0x30a0, MIF), |
| SFR(QCH_CON_PPCFW_G3D_QCH, 0x30a4, MIF), |
| SFR(QCH_CON_BCM_ACE_CPUCL0_QCH, 0x30a8, MIF), |
| SFR(QCH_CON_BCM_ACE_CPUCL1_QCH, 0x30ac, MIF), |
| SFR(QCH_CON_QE_QCH, 0x30b0, MIF), |
| SFR(DMYQCH_CON_RSTNSYNC_CLK_MIF_CCI_QCH_OCC, 0x300c, MIF), |
| SFR(QCH_CON_SFR_APBIF_CMU_CMU_QCH, 0x30b4, MIF), |
| SFR(QCH_CON_SPDMA_CORE_QCH, 0x30b8, MIF), |
| SFR(QCH_CON_SYSREG_MIF_QCH, 0x30bc, MIF), |
| SFR(QCH_CON_TREX_D_CORE_QCH, 0x30c0, MIF), |
| SFR(QCH_CON_TREX_P_CORE_QCH, 0x30c4, MIF), |
| SFR(QCH_CON_WRAP_ADC_IF_QCH_0, 0x30c8, MIF), |
| SFR(QCH_CON_WRAP_ADC_IF_QCH_1, 0x30cc, MIF), |
| SFR(CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_IPCLKPORT_PCLK, 0x2008, MODEM), |
| SFR(QCH_CON_MODEM_CMU_QCH, 0x3000, MODEM), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 0x20b8, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 0x20c0, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK, 0x20a0, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK, 0x20b0, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK, 0x2014, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 0x20a4, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK, 0x20a8, PERI), |
| SFR(CLKOUT_CON_BLK_PERI_CMU_CLKOUT0, 0x0810, PERI), |
| SFR(CLKOUT_CON_BLK_PERI_CMU_CLKOUT1, 0x0814, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C6_PCLK, 0x2054, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C0_PCLK, 0x203c, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C1_PCLK, 0x2040, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C2_PCLK, 0x2044, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C3_PCLK, 0x2048, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C4_PCLK, 0x204c, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C5_PCLK, 0x2050, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_PWM_MOTOR_PCLK, 0x2058, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_SPI_EXT_CLK, 0x2060, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_PCLK, 0x2064, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_PCLK, 0x205c, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_SPI_EXT_CLK, 0x2068, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_PCLK, 0x2070, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_EXT_UCLK, 0x206c, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_PCLK, 0x2078, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_EXT_UCLK, 0x2074, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C3_PCLK, 0x2038, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C1_PCLK, 0x2030, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C0_PCLK, 0x202c, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_PCLK, 0x208c, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_PCLK, 0x2084, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C2_PCLK, 0x2034, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_SECUCON_IPCLKPORT_PCLK, 0x20ac, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_PERI_IPCLKPORT_ACLK, 0x2010, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP_BR_PERI_IPCLKPORT_HCLK, 0x201c, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC0_HCLK, 0x2020, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC1_HCLK, 0x2024, PERI), |
| SFR(CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK, 0x2000, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK, 0x2018, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_GPIO_TOP_PCLK, 0x2028, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK, 0x209c, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_SCLK, 0x2088, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_SCLK, 0x2090, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_SCLK, 0x2098, PERI), |
| SFR(PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 0x0100, PERI), |
| SFR(PLL_CON2_MUX_CLKCMU_PERI_BUS_USER, 0x0108, PERI), |
| SFR(PLL_CON0_MUX_CLKCMU_PERI_UART_0_USER, 0x0160, PERI), |
| SFR(PLL_CON2_MUX_CLKCMU_PERI_UART_0_USER, 0x0168, PERI), |
| SFR(PLL_CON0_MUX_CLKCMU_PERI_UART_1_USER, 0x0180, PERI), |
| SFR(PLL_CON2_MUX_CLKCMU_PERI_UART_1_USER, 0x0188, PERI), |
| SFR(PLL_CON0_MUX_CLKCMU_PERI_USI0_USER, 0x01c0, PERI), |
| SFR(PLL_CON2_MUX_CLKCMU_PERI_USI0_USER, 0x01c8, PERI), |
| SFR(PLL_CON0_MUX_CLKCMU_PERI_USI1_USER, 0x01e0, PERI), |
| SFR(PLL_CON2_MUX_CLKCMU_PERI_USI1_USER, 0x01e8, PERI), |
| SFR(PLL_CON0_MUX_CLKCMU_PERI_USI2_USER, 0x0200, PERI), |
| SFR(PLL_CON2_MUX_CLKCMU_PERI_USI2_USER, 0x0208, PERI), |
| SFR(PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER, 0x0120, PERI), |
| SFR(PLL_CON2_MUX_CLKCMU_PERI_SPI0_USER, 0x0128, PERI), |
| SFR(PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER, 0x0140, PERI), |
| SFR(PLL_CON2_MUX_CLKCMU_PERI_SPI1_USER, 0x0148, PERI), |
| SFR(PLL_CON0_MUX_CLKCMU_PERI_UART_2_USER, 0x01a0, PERI), |
| SFR(PLL_CON2_MUX_CLKCMU_PERI_UART_2_USER, 0x01a8, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_PCLK, 0x2080, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_EXT_UCLK, 0x207c, PERI), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_PCLK, 0x2094, PERI), |
| SFR(QCH_CON_BUSIF_TMU_QCH, 0x3000, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_I2C0, 0x3018, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_I2C1, 0x301c, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_I2C2, 0x3020, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_I2C3, 0x3024, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_I2C4, 0x3028, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_I2C5, 0x302c, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_I2C6, 0x3030, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_PWM_MOTOR, 0x3034, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_SPI0, 0x3038, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_SPI1, 0x303c, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_USI2, 0x3054, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_UART0, 0x3040, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_UART1, 0x3044, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_HSI2C0, 0x3008, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_HSI2C1, 0x300c, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_HSI2C2, 0x3010, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_HSI2C3, 0x3014, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_USI0, 0x304c, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_USI1, 0x3050, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_GPIO, 0x3004, PERI), |
| SFR(QCH_CON_LBLK_PERIC_QCH_UART2, 0x3048, PERI), |
| SFR(QCH_CON_LHM_AXI_P_PERI_QCH, 0x3058, PERI), |
| SFR(QCH_CON_MCT_QCH, 0x305c, PERI), |
| SFR(QCH_CON_OTP_CON_TOP_QCH, 0x3060, PERI), |
| SFR(QCH_CON_PERI_CMU_PERI_QCH, 0x3064, PERI), |
| SFR(QCH_CON_SECUCON_QCH, 0x3068, PERI), |
| SFR(QCH_CON_SYSREG_PERI_QCH, 0x306c, PERI), |
| SFR(QCH_CON_WDT_CLUSTER0_QCH, 0x3070, PERI), |
| SFR(QCH_CON_WDT_CLUSTER1_QCH, 0x3074, PERI), |
| /*====================The section of controller option SFR instance===================*/ |
| SFR(APM_CMU_CONTROLLER_OPTION, 0x0800, APM), |
| SFR(CMU_CMU_CONTROLLER_OPTION, 0x0800, CMU), |
| SFR(CPUCL0_CMU_CONTROLLER_OPTION, 0x0800, CPUCL0), |
| SFR(CPUCL1_CMU_CONTROLLER_OPTION, 0x0800, CPUCL1), |
| SFR(DISPAUD_CMU_CONTROLLER_OPTION, 0x0800, DISPAUD), |
| SFR(FSYS_CMU_CONTROLLER_OPTION, 0x0800, FSYS), |
| SFR(G3D_CMU_CONTROLLER_OPTION, 0x0800, G3D), |
| SFR(IS_CMU_CONTROLLER_OPTION, 0x0800, IS), |
| SFR(MFCMSCL_CMU_CONTROLLER_OPTION, 0x0800, MFCMSCL), |
| SFR(MIF_CMU_CONTROLLER_OPTION, 0x0800, MIF), |
| SFR(MODEM_CMU_CONTROLLER_OPTION, 0x0800, MODEM), |
| SFR(PERI_CMU_CONTROLLER_OPTION, 0x0800, PERI), |
| }; |
| |
| unsigned int cmucal_sfr_size = 802; |
| unsigned int dbg_offset = 0x4000; |
| |
| /*====================The section of SFR Access instance===================*/ |
| struct sfr_access cmucal_sfr_access_list[] __initdata = { |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_APM_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_APM_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_APM_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_APM_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_APM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_APM_BUS_USER), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_INTMEM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_INTMEM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_INTMEM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_INTMEM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_INTMEM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_INTMEM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_NORET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_NORET_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_NORET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_NORET_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_NORET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_NORET_IPCLKPORT_CLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_APM_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_APM_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_APM_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_APM_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_APM_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_APM_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_AP_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_AP_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_AP_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_AP_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_AP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_AP_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_CP_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_CP_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_CP_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_CP_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_CP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_CP_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MP_APBSEMA_HWACG_2CH_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MP_APBSEMA_HWACG_2CH_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MP_APBSEMA_HWACG_2CH_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MP_APBSEMA_HWACG_2CH_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MP_APBSEMA_HWACG_2CH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MP_APBSEMA_HWACG_2CH_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_APM_I2C), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_APM_I2C), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_I2C_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_APM_I2C), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_I2C_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_I2C_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_I2C_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_I2C_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_I2C_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_I2C_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKS), |
| SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_GPIO_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_APBIF_PMU_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_PMU_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_PMU_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_APM_QCH_CPU_ENABLE, 0, 1, QCH_CON_APM_QCH_CPU), |
| SFR_ACCESS(QCH_CON_APM_QCH_CPU_CLOCK_REQ, 1, 1, QCH_CON_APM_QCH_CPU), |
| SFR_ACCESS(QCH_CON_APM_QCH_CPU_EXPIRE_VAL, 16, 10, QCH_CON_APM_QCH_CPU), |
| SFR_ACCESS(QCH_CON_APM_QCH_INTMEM_ENABLE, 0, 1, QCH_CON_APM_QCH_INTMEM), |
| SFR_ACCESS(QCH_CON_APM_QCH_INTMEM_CLOCK_REQ, 1, 1, QCH_CON_APM_QCH_INTMEM), |
| SFR_ACCESS(QCH_CON_APM_QCH_INTMEM_EXPIRE_VAL, 16, 10, QCH_CON_APM_QCH_INTMEM), |
| SFR_ACCESS(DMYQCH_CON_APM_QCH_OSCCLK_ENABLE, 0, 1, DMYQCH_CON_APM_QCH_OSCCLK), |
| SFR_ACCESS(DMYQCH_CON_APM_QCH_OSCCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_APM_QCH_OSCCLK), |
| SFR_ACCESS(QCH_CON_APM_QCH_DBG_ENABLE, 0, 1, QCH_CON_APM_QCH_DBG), |
| SFR_ACCESS(QCH_CON_APM_QCH_DBG_CLOCK_REQ, 1, 1, QCH_CON_APM_QCH_DBG), |
| SFR_ACCESS(QCH_CON_APM_QCH_DBG_EXPIRE_VAL, 16, 10, QCH_CON_APM_QCH_DBG), |
| SFR_ACCESS(QCH_CON_APM_QCH_SYS_ENABLE, 0, 1, QCH_CON_APM_QCH_SYS), |
| SFR_ACCESS(QCH_CON_APM_QCH_SYS_CLOCK_REQ, 1, 1, QCH_CON_APM_QCH_SYS), |
| SFR_ACCESS(QCH_CON_APM_QCH_SYS_EXPIRE_VAL, 16, 10, QCH_CON_APM_QCH_SYS), |
| SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_ENABLE, 0, 1, QCH_CON_APM_CMU_APM_QCH), |
| SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_APM_CMU_APM_QCH), |
| SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APM_CMU_APM_QCH), |
| SFR_ACCESS(QCH_CON_I2C_APM_QCH_ENABLE, 0, 1, QCH_CON_I2C_APM_QCH), |
| SFR_ACCESS(QCH_CON_I2C_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_APM_QCH), |
| SFR_ACCESS(QCH_CON_I2C_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_APM_QCH), |
| SFR_ACCESS(QCH_CON_IP_BATCHER_AP_QCH_ENABLE, 0, 1, QCH_CON_IP_BATCHER_AP_QCH), |
| SFR_ACCESS(QCH_CON_IP_BATCHER_AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_IP_BATCHER_AP_QCH), |
| SFR_ACCESS(QCH_CON_IP_BATCHER_AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_IP_BATCHER_AP_QCH), |
| SFR_ACCESS(QCH_CON_IP_BATCHER_CP_QCH_ENABLE, 0, 1, QCH_CON_IP_BATCHER_CP_QCH), |
| SFR_ACCESS(QCH_CON_IP_BATCHER_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_IP_BATCHER_CP_QCH), |
| SFR_ACCESS(QCH_CON_IP_BATCHER_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_IP_BATCHER_CP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2AP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM2AP_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM2AP_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM2AP_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2CP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM2CP_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM2CP_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM2CP_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2GNSS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM2GNSS_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM2GNSS_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM2GNSS_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2WLBT_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM2WLBT_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM2WLBT_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM2WLBT_QCH), |
| SFR_ACCESS(QCH_CON_MP_APBSEMA_HWACG_2CH_QCH_ENABLE, 0, 1, QCH_CON_MP_APBSEMA_HWACG_2CH_QCH), |
| SFR_ACCESS(QCH_CON_MP_APBSEMA_HWACG_2CH_QCH_CLOCK_REQ, 1, 1, QCH_CON_MP_APBSEMA_HWACG_2CH_QCH), |
| SFR_ACCESS(QCH_CON_MP_APBSEMA_HWACG_2CH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MP_APBSEMA_HWACG_2CH_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY_QCH_ENABLE, 0, 1, QCH_CON_SPEEDY_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPEEDY_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPEEDY_QCH), |
| SFR_ACCESS(DMYQCH_CON_SPEEDY_QCH_OSCCLK_ENABLE, 0, 1, DMYQCH_CON_SPEEDY_QCH_OSCCLK), |
| SFR_ACCESS(DMYQCH_CON_SPEEDY_QCH_OSCCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_SPEEDY_QCH_OSCCLK), |
| SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_APM_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_APM_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_APM_QCH), |
| SFR_ACCESS(QCH_CON_WDT_APM_QCH_ENABLE, 0, 1, QCH_CON_WDT_APM_QCH), |
| SFR_ACCESS(QCH_CON_WDT_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_APM_QCH), |
| SFR_ACCESS(QCH_CON_WDT_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_APM_QCH), |
| SFR_ACCESS(DMYQCH_CON_WDT_APM_QCH_OSCCLK_ENABLE, 0, 1, DMYQCH_CON_WDT_APM_QCH_OSCCLK), |
| SFR_ACCESS(DMYQCH_CON_WDT_APM_QCH_OSCCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_WDT_APM_QCH_OSCCLK), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MSCL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MSCL), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MSCL), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MSCL_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MSCL), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MSCL_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MSCL), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MSCL_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MSCL), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MSCL), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G3D_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G3D_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_G3D_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IS_3AA_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_IS_3AA), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IS_3AA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_IS_3AA), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IS_3AA_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_IS_3AA), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IS_3AA_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_IS_3AA), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IS_3AA_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_IS_3AA), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IS_3AA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_IS_3AA), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IS_VRA_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_IS_VRA), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IS_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_IS_VRA), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IS_VRA_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_IS_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IS_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_IS_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IS_VRA_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_IS_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IS_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_IS_VRA), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IS_VRA_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_IS_VRA), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IS_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_IS_VRA), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IS_VRA_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_IS_VRA), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IS_3AA_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_IS_3AA), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IS_3AA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_IS_3AA), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IS_3AA_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_IS_3AA), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IS_ISP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_IS_ISP), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IS_ISP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_IS_ISP), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IS_ISP_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_IS_ISP), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IS_ISP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_IS_ISP), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IS_ISP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_IS_ISP), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IS_ISP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_IS_ISP), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DISPAUD_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DISPAUD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DISPAUD_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISPAUD_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DISPAUD_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISPAUD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DISPAUD_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISPAUD_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DISPAUD_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_FSYS_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFCMSCL_MFC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MFCMSCL_MFC), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFCMSCL_MFC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MFCMSCL_MFC), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFCMSCL_MFC_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_MFCMSCL_MFC), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IS_ISP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_IS_ISP), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IS_ISP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_IS_ISP), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IS_ISP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_IS_ISP), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0), |
| SFR_ACCESS(CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_BUSY, 16, 1, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK), |
| SFR_ACCESS(CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK), |
| SFR_ACCESS(CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_DIVRATIO, 0, 2, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERI_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERI_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERI_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_UART_0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_UART_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_UART_0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_UART_0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_UART_0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_UART_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_UART_0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERI_UART_0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_UART_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERI_UART_0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_UART_0_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERI_UART_0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_UART_1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERI_UART_1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_UART_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERI_UART_1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_UART_1_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERI_UART_1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_UART_1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_UART_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_UART_1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMUC_PERI_UART_1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMUC_PERI_UART_1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMUC_PERI_UART_1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMUC_PERI_UART_1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMUC_PERI_UART_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMUC_PERI_UART_1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_USI2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_USI2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_USI2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_USI2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_USI2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_USI2), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_USI2_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_USI2), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_USI2_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_USI2), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_USI2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_USI2), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_USI2_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERI_USI2), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_USI2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERI_USI2), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_USI2_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERI_USI2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_SPI_0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERI_SPI_0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_SPI_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERI_SPI_0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_SPI_0_DIVRATIO, 0, 6, CLK_CON_DIV_CLKCMU_PERI_SPI_0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_SPI_1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERI_SPI_1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_SPI_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERI_SPI_1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_SPI_1_DIVRATIO, 0, 6, CLK_CON_DIV_CLKCMU_PERI_SPI_1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_BUS_DIVRATIO, 0, 2, CLK_CON_DIV_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_DIVRATIO, 0, 9, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CMU_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CMU_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CMU_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CMU_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CMU_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CMU_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_DIVRATIO, 0, 9, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_USI0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_USI0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_USI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_USI0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_USI0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_USI0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_USI0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_USI0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_USI0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_USI0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_USI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_USI0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_USI0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERI_USI0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_USI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERI_USI0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_USI0_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERI_USI0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_USI1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_USI1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_USI1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_USI1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_USI1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_USI1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_USI1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_USI1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_USI1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_USI1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_USI1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_USI1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_USI1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERI_USI1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_USI1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERI_USI1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_USI1_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERI_USI1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1), |
| SFR_ACCESS(CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_BUSY, 16, 1, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK), |
| SFR_ACCESS(CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK), |
| SFR_ACCESS(CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_DIVRATIO, 0, 4, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMU_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMU_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMU_CMUREF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMU_CMUREF_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISPAUD_CPU_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DISPAUD_CPU), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISPAUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DISPAUD_CPU), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISPAUD_CPU_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_DISPAUD_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_VCLK_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_VCLK), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_VCLK_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_VCLK), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_VCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_VCLK), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED0_DIV_P, 8, 6, PLL_CON0_PLL_SHARED0), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED0_DIV_M, 16, 10, PLL_CON0_PLL_SHARED0), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED0_DIV_S, 0, 3, PLL_CON0_PLL_SHARED0), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED0_ENABLE, 31, 1, PLL_CON0_PLL_SHARED0), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED0_STABLE, 29, 1, PLL_CON0_PLL_SHARED0), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED0), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED1_DIV_P, 8, 6, PLL_CON0_PLL_SHARED1), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED1_DIV_M, 16, 10, PLL_CON0_PLL_SHARED1), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED1_DIV_S, 0, 3, PLL_CON0_PLL_SHARED1), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED1_ENABLE, 31, 1, PLL_CON0_PLL_SHARED1), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED1_STABLE, 29, 1, PLL_CON0_PLL_SHARED1), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_CCI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_CCI), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_CCI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_CCI), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_CCI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_CCI), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_CCI_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MIF_CCI), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_CCI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MIF_CCI), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_CCI_DIVRATIO, 0, 2, CLK_CON_DIV_CLKCMU_MIF_CCI), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_CCI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_CCI), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_CCI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_CCI), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_CCI_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_CCI), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IS_TPU_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_IS_TPU), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IS_TPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_IS_TPU), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IS_TPU_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_IS_TPU), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IS_TPU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_IS_TPU), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IS_TPU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_IS_TPU), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IS_TPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_IS_TPU), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IS_TPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_IS_TPU), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IS_TPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_IS_TPU), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IS_TPU_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_IS_TPU), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MIF_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MIF_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_MIF_SWITCH), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO_DIVRATIO, 0, 9, CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MIF_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MIF_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_BUS_DIVRATIO, 0, 2, CLK_CON_DIV_CLKCMU_MIF_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_UART_2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_UART_2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_UART_2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_2), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_UART_2_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_2), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_UART_2_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_2), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_UART_2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_2), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_UART_2_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERI_UART_2), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_UART_2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERI_UART_2), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_UART_2_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERI_UART_2), |
| SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV3_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED0_DIV3), |
| SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED0_DIV3), |
| SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV3_DIVRATIO, 0, 2, CLK_CON_DIV_PLL_SHARED0_DIV3), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SECJTAG_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SECJTAG), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SECJTAG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SECJTAG), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SECJTAG_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL0_SECJTAG), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SECJTAG_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SECJTAG), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SECJTAG_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SECJTAG), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SECJTAG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SECJTAG), |
| SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV2_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED0_DIV2), |
| SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED0_DIV2), |
| SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_PLL_SHARED0_DIV2), |
| SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV4_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED0_DIV4), |
| SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED0_DIV4), |
| SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV4_DIVRATIO, 0, 1, CLK_CON_DIV_PLL_SHARED0_DIV4), |
| SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV2_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED1_DIV2), |
| SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED1_DIV2), |
| SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_PLL_SHARED1_DIV2), |
| SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV4_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED1_DIV4), |
| SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED1_DIV4), |
| SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV4_DIVRATIO, 0, 1, CLK_CON_DIV_PLL_SHARED1_DIV4), |
| SFR_ACCESS(DMYQCH_CON_CMU_CMU_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CMU_CMUREF_QCH), |
| SFR_ACCESS(DMYQCH_CON_CMU_CMU_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CMU_CMUREF_QCH), |
| SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0), |
| SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0), |
| SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1), |
| SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1), |
| SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2), |
| SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL0_DIV_P, 8, 6, PLL_CON0_PLL_CPUCL0), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL0_DIV_M, 16, 10, PLL_CON0_PLL_CPUCL0), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL0_DIV_S, 0, 3, PLL_CON0_PLL_CPUCL0), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL0_ENABLE, 31, 1, PLL_CON0_PLL_CPUCL0), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL0_STABLE, 29, 1, PLL_CON0_PLL_CPUCL0), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL0), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_ACLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL0_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_ATCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_ATCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_ATCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_ATCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL0_ATCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CNTCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CNTCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CNTCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CNTCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CNTCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL0_CNTCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_DIVRATIO, 0, 12, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_P_CSSYS_DBG_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_P_CSSYS_DBG_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_P_CSSYS_DBG_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_P_CSSYS_DBG_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_P_CSSYS_DBG_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_P_CSSYS_DBG_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_T_CSSYS_DBG_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_T_CSSYS_DBG_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_T_CSSYS_DBG_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_T_CSSYS_DBG_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_T_CSSYS_DBG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_T_CSSYS_DBG_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLKDBG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLKDBG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLKDBG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_DBG_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_DBG_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_DBG_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_DBG_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_DBG_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_DBG_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_ACLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_ACLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_ACLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_ACLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_ACLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SECJTAG_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SECJTAG_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SECJTAG_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SECJTAG_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CPUCL0_SECJTAG_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CPUCL0_SECJTAG_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL_SECJTAG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL_SECJTAG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL_SECJTAG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL_SECJTAG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL_SECJTAG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL_SECJTAG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK), |
| SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_CPU_ENABLE, 0, 1, DMYQCH_CON_CLUSTER0_QCH_CPU), |
| SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_CPU_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER0_QCH_CPU), |
| SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_DBG_ENABLE, 0, 1, DMYQCH_CON_CLUSTER0_QCH_DBG), |
| SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_DBG_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER0_QCH_DBG), |
| SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH), |
| SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH), |
| SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH), |
| SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL0_CMU_CPUCL0_QCH), |
| SFR_ACCESS(DMYQCH_CON_CSSYS_DBG_QCH_ENABLE, 0, 1, DMYQCH_CON_CSSYS_DBG_QCH), |
| SFR_ACCESS(DMYQCH_CON_CSSYS_DBG_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CSSYS_DBG_QCH), |
| SFR_ACCESS(QCH_CON_DUMP_PC_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_DUMP_PC_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_DUMP_PC_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_DUMP_PC_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_DUMP_PC_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DUMP_PC_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACE_D_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACE_D_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACE_D_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACE_D_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACE_D_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACE_D_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_T_CSSYS_DBG_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_T_CSSYS_DBG_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_T_CSSYS_DBG_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_T_CSSYS_DBG_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_T_CSSYS_DBG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_T_CSSYS_DBG_QCH), |
| SFR_ACCESS(QCH_CON_SECJTAG_QCH_ENABLE, 0, 1, QCH_CON_SECJTAG_QCH), |
| SFR_ACCESS(QCH_CON_SECJTAG_QCH_CLOCK_REQ, 1, 1, QCH_CON_SECJTAG_QCH), |
| SFR_ACCESS(QCH_CON_SECJTAG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SECJTAG_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CPUCL0_QCH), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL1_DIV_P, 8, 6, PLL_CON0_PLL_CPUCL1), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL1_DIV_M, 16, 10, PLL_CON0_PLL_CPUCL1), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL1_DIV_S, 0, 3, PLL_CON0_PLL_CPUCL1), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL1_ENABLE, 31, 1, PLL_CON0_PLL_CPUCL1), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL1_STABLE, 29, 1, PLL_CON0_PLL_CPUCL1), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_ACLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL1_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_ATCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_ATCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_ATCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_ATCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL1_ATCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_DIVRATIO, 0, 12, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CPUCL1_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CPUCL1_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CPUCL1_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CPUCL1_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CPUCL1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CPUCL1_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CNTCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CNTCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CNTCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CNTCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CNTCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL1_CNTCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_CPU_ENABLE, 0, 1, DMYQCH_CON_CLUSTER1_QCH_CPU), |
| SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_CPU_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER1_QCH_CPU), |
| SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_DBG_ENABLE, 0, 1, DMYQCH_CON_CLUSTER1_QCH_DBG), |
| SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_DBG_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER1_QCH_DBG), |
| SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH), |
| SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH), |
| SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH), |
| SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL1_CMU_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_DUMP_PC_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_DUMP_PC_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_DUMP_PC_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_DUMP_PC_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_DUMP_PC_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DUMP_PC_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACE_D_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACE_D_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACE_D_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACE_D_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACE_D_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACE_D_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CPUCL1_QCH), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_BUS), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_BUS), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_BUS), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_PLL_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_PLL), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_PLL), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_PLL_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_PLL), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_AUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_AUD_CPU_USER), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF0), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF0), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLK_AUD_UAIF0), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_AUDIF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_AUDIF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_AUDIF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF2), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF2), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLK_AUD_UAIF2), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF3_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF3), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF3), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF3_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLK_AUD_UAIF3), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF3), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF3), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF3_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF3), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_PCLKDBG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_PCLKDBG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_PCLKDBG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_ABOXCPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_ABOXCPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_ABOXCPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_ABOXCPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_ABOXCPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_ABOXCPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_FM), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_FM), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_DIVRATIO, 0, 10, CLK_CON_DIV_DIV_CLK_AUD_FM), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DISPAUD_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DISPAUD_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DISPAUD_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DISPAUD_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DISPAUD_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DISPAUD_BUS_USER), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP), |
| SFR_ACCESS(PLL_CON0_PLL_AUD_DIV_P, 8, 6, PLL_CON0_PLL_AUD), |
| SFR_ACCESS(PLL_CON0_PLL_AUD_DIV_M, 16, 10, PLL_CON0_PLL_AUD), |
| SFR_ACCESS(PLL_CON0_PLL_AUD_DIV_S, 0, 3, PLL_CON0_PLL_AUD), |
| SFR_ACCESS(PLL_CON0_PLL_AUD_ENABLE, 31, 1, PLL_CON0_PLL_AUD), |
| SFR_ACCESS(PLL_CON0_PLL_AUD_STABLE, 29, 1, PLL_CON0_PLL_AUD), |
| SFR_ACCESS(PLL_CON3_PLL_AUD_DIV_K, 0, 16, PLL_CON3_PLL_AUD), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_AUD), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DSIM0_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DSIM0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DSIM0_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DSIM0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DSIM0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DSIM0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI2APB_DISPAUD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI2APB_DISPAUD_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI2APB_DISPAUD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI2APB_DISPAUD_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI2APB_DISPAUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI2APB_DISPAUD_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_XIU_P_DISPAUD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_XIU_P_DISPAUD_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_XIU_P_DISPAUD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_XIU_P_DISPAUD_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_XIU_P_DISPAUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_XIU_P_DISPAUD_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK), |
| SFR_ACCESS(DMYQCH_CON_ABOX_QCH_ABOX_ENABLE, 0, 1, DMYQCH_CON_ABOX_QCH_ABOX), |
| SFR_ACCESS(DMYQCH_CON_ABOX_QCH_ABOX_CLOCK_REQ, 1, 1, DMYQCH_CON_ABOX_QCH_ABOX), |
| SFR_ACCESS(DMYQCH_CON_ABOX_QCH_CPU_ENABLE, 0, 1, DMYQCH_CON_ABOX_QCH_CPU), |
| SFR_ACCESS(DMYQCH_CON_ABOX_QCH_CPU_CLOCK_REQ, 1, 1, DMYQCH_CON_ABOX_QCH_CPU), |
| SFR_ACCESS(QCH_CON_ABOX_QCH_BUS_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BUS), |
| SFR_ACCESS(QCH_CON_ABOX_QCH_BUS_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BUS), |
| SFR_ACCESS(QCH_CON_ABOX_QCH_BUS_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BUS), |
| SFR_ACCESS(QCH_CON_ABOX_QCH_UAIF0_ENABLE, 0, 1, QCH_CON_ABOX_QCH_UAIF0), |
| SFR_ACCESS(QCH_CON_ABOX_QCH_UAIF0_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_UAIF0), |
| SFR_ACCESS(QCH_CON_ABOX_QCH_UAIF0_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_UAIF0), |
| SFR_ACCESS(QCH_CON_ABOX_QCH_UAIF2_ENABLE, 0, 1, QCH_CON_ABOX_QCH_UAIF2), |
| SFR_ACCESS(QCH_CON_ABOX_QCH_UAIF2_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_UAIF2), |
| SFR_ACCESS(QCH_CON_ABOX_QCH_UAIF2_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_UAIF2), |
| SFR_ACCESS(QCH_CON_ABOX_QCH_UAIF3_ENABLE, 0, 1, QCH_CON_ABOX_QCH_UAIF3), |
| SFR_ACCESS(QCH_CON_ABOX_QCH_UAIF3_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_UAIF3), |
| SFR_ACCESS(QCH_CON_ABOX_QCH_UAIF3_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_UAIF3), |
| SFR_ACCESS(DMYQCH_CON_ABOX_QCH_FM_ENABLE, 0, 1, DMYQCH_CON_ABOX_QCH_FM), |
| SFR_ACCESS(DMYQCH_CON_ABOX_QCH_FM_CLOCK_REQ, 1, 1, DMYQCH_CON_ABOX_QCH_FM), |
| SFR_ACCESS(QCH_CON_DISPAUD_CMU_DISPAUD_QCH_ENABLE, 0, 1, QCH_CON_DISPAUD_CMU_DISPAUD_QCH), |
| SFR_ACCESS(QCH_CON_DISPAUD_CMU_DISPAUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_DISPAUD_CMU_DISPAUD_QCH), |
| SFR_ACCESS(QCH_CON_DISPAUD_CMU_DISPAUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DISPAUD_CMU_DISPAUD_QCH), |
| SFR_ACCESS(QCH_CON_DPU_QCH_DPP_ENABLE, 0, 1, QCH_CON_DPU_QCH_DPP), |
| SFR_ACCESS(QCH_CON_DPU_QCH_DPP_CLOCK_REQ, 1, 1, QCH_CON_DPU_QCH_DPP), |
| SFR_ACCESS(QCH_CON_DPU_QCH_DPP_EXPIRE_VAL, 16, 10, QCH_CON_DPU_QCH_DPP), |
| SFR_ACCESS(QCH_CON_DPU_QCH_DMA_ENABLE, 0, 1, QCH_CON_DPU_QCH_DMA), |
| SFR_ACCESS(QCH_CON_DPU_QCH_DMA_CLOCK_REQ, 1, 1, QCH_CON_DPU_QCH_DMA), |
| SFR_ACCESS(QCH_CON_DPU_QCH_DMA_EXPIRE_VAL, 16, 10, QCH_CON_DPU_QCH_DMA), |
| SFR_ACCESS(QCH_CON_DPU_QCH_DECON0_ENABLE, 0, 1, QCH_CON_DPU_QCH_DECON0), |
| SFR_ACCESS(QCH_CON_DPU_QCH_DECON0_CLOCK_REQ, 1, 1, QCH_CON_DPU_QCH_DECON0), |
| SFR_ACCESS(QCH_CON_DPU_QCH_DECON0_EXPIRE_VAL, 16, 10, QCH_CON_DPU_QCH_DECON0), |
| SFR_ACCESS(QCH_CON_GPIO_DISPAUD_QCH_ENABLE, 0, 1, QCH_CON_GPIO_DISPAUD_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_DISPAUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_DISPAUD_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_DISPAUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_DISPAUD_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DISPAUD_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DISPAUD_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DISPAUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DISPAUD_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DISPAUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DISPAUD_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_ABOX_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_DPU_QCH), |
| SFR_ACCESS(QCH_CON_BCM_ABOX_QCH_ENABLE, 0, 1, QCH_CON_BCM_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_BCM_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_BCM_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_BCM_DPU_QCH_ENABLE, 0, 1, QCH_CON_BCM_DPU_QCH), |
| SFR_ACCESS(QCH_CON_BCM_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_DPU_QCH), |
| SFR_ACCESS(QCH_CON_BCM_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_DPU_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_ABOX_QCH_ENABLE, 0, 1, QCH_CON_SMMU_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_DPU_QCH_ENABLE, 0, 1, QCH_CON_SMMU_DPU_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_DPU_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_DPU_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DISPAUD_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DISPAUD_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DISPAUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DISPAUD_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DISPAUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DISPAUD_QCH), |
| SFR_ACCESS(QCH_CON_WDT_ABOXCPU_QCH_ENABLE, 0, 1, QCH_CON_WDT_ABOXCPU_QCH), |
| SFR_ACCESS(QCH_CON_WDT_ABOXCPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_ABOXCPU_QCH), |
| SFR_ACCESS(QCH_CON_WDT_ABOXCPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_ABOXCPU_QCH), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS_BUS_USER), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS_MMC_CARD_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS_MMC_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS_MMC_EMBD_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_BUS_CLK_EARLY_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_BUS_CLK_EARLY), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_BUS_CLK_EARLY_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_BUS_CLK_EARLY), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_BUS_CLK_EARLY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_BUS_CLK_EARLY), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_PHYCTRL), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_PHYCTRL), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_PHYCTRL), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_AXI2AHB_FSYS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AXI2AHB_FSYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_AXI2AHB_FSYS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AXI2AHB_FSYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_AXI2AHB_FSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AXI2AHB_FSYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_1X4_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_1X4_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_1X4_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_1X4_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_1X4_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_1X4_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_AXI_D_FSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_AXI_D_FSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_AXI_D_FSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_AXI_D_FSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_AXI_D_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_AXI_D_FSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_FSYS_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_FSYS_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_FSYS_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_FSYS_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_FSYS_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_FSYS_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHB2APB_FSYS_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHB2APB_FSYS_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHB2APB_FSYS_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHB2APB_FSYS_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHB2APB_FSYS_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHB2APB_FSYS_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS_MMC_SDIO_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS_MMC_SDIO_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_SDCLKIN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_SDCLKIN), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_SDCLKIN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_SDCLKIN), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_SDCLKIN), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(QCH_CON_ADM_AHB_SSS_QCH_ENABLE, 0, 1, QCH_CON_ADM_AHB_SSS_QCH), |
| SFR_ACCESS(QCH_CON_ADM_AHB_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_ADM_AHB_SSS_QCH), |
| SFR_ACCESS(QCH_CON_ADM_AHB_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ADM_AHB_SSS_QCH), |
| SFR_ACCESS(QCH_CON_FSYS_CMU_FSYS_QCH_ENABLE, 0, 1, QCH_CON_FSYS_CMU_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_FSYS_CMU_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_FSYS_CMU_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_FSYS_CMU_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_FSYS_CMU_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_FSYS_QCH_ENABLE, 0, 1, QCH_CON_GPIO_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_FSYS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_MMC_CARD_QCH_ENABLE, 0, 1, QCH_CON_MMC_CARD_QCH), |
| SFR_ACCESS(QCH_CON_MMC_CARD_QCH_CLOCK_REQ, 1, 1, QCH_CON_MMC_CARD_QCH), |
| SFR_ACCESS(QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MMC_CARD_QCH), |
| SFR_ACCESS(QCH_CON_MMC_EMBD_QCH_ENABLE, 0, 1, QCH_CON_MMC_EMBD_QCH), |
| SFR_ACCESS(QCH_CON_MMC_EMBD_QCH_CLOCK_REQ, 1, 1, QCH_CON_MMC_EMBD_QCH), |
| SFR_ACCESS(QCH_CON_MMC_EMBD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MMC_EMBD_QCH), |
| SFR_ACCESS(QCH_CON_MMC_SDIO_QCH_ENABLE, 0, 1, QCH_CON_MMC_SDIO_QCH), |
| SFR_ACCESS(QCH_CON_MMC_SDIO_QCH_CLOCK_REQ, 1, 1, QCH_CON_MMC_SDIO_QCH), |
| SFR_ACCESS(QCH_CON_MMC_SDIO_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MMC_SDIO_QCH), |
| SFR_ACCESS(QCH_CON_BCM_FSYS_QCH_ENABLE, 0, 1, QCH_CON_BCM_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_BCM_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_BCM_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_RTIC_QCH_ENABLE, 0, 1, QCH_CON_RTIC_QCH), |
| SFR_ACCESS(QCH_CON_RTIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_RTIC_QCH), |
| SFR_ACCESS(QCH_CON_RTIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RTIC_QCH), |
| SFR_ACCESS(QCH_CON_SSS_QCH_ENABLE, 0, 1, QCH_CON_SSS_QCH), |
| SFR_ACCESS(QCH_CON_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSS_QCH), |
| SFR_ACCESS(QCH_CON_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSS_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_FSYS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_USB20DRD_QCH_HSDRD_ENABLE, 0, 1, QCH_CON_USB20DRD_QCH_HSDRD), |
| SFR_ACCESS(QCH_CON_USB20DRD_QCH_HSDRD_CLOCK_REQ, 1, 1, QCH_CON_USB20DRD_QCH_HSDRD), |
| SFR_ACCESS(QCH_CON_USB20DRD_QCH_HSDRD_EXPIRE_VAL, 16, 10, QCH_CON_USB20DRD_QCH_HSDRD), |
| SFR_ACCESS(QCH_CON_USB20DRD_QCH_USB_ENABLE, 0, 1, QCH_CON_USB20DRD_QCH_USB), |
| SFR_ACCESS(QCH_CON_USB20DRD_QCH_USB_CLOCK_REQ, 1, 1, QCH_CON_USB20DRD_QCH_USB), |
| SFR_ACCESS(QCH_CON_USB20DRD_QCH_USB_EXPIRE_VAL, 16, 10, QCH_CON_USB20DRD_QCH_USB), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_G3D_BUSP), |
| SFR_ACCESS(PLL_CON0_PLL_G3D_DIV_P, 8, 6, PLL_CON0_PLL_G3D), |
| SFR_ACCESS(PLL_CON0_PLL_G3D_DIV_M, 16, 10, PLL_CON0_PLL_G3D), |
| SFR_ACCESS(PLL_CON0_PLL_G3D_DIV_S, 0, 3, PLL_CON0_PLL_G3D), |
| SFR_ACCESS(PLL_CON0_PLL_G3D_ENABLE, 31, 1, PLL_CON0_PLL_G3D), |
| SFR_ACCESS(PLL_CON0_PLL_G3D_STABLE, 29, 1, PLL_CON0_PLL_G3D), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_G3D), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_BUSD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_G3D_BUSD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_G3D_BUSD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_BUSD_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_G3D_BUSD), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_G3D_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_G3D_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_G3D_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_G3D_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_G3D_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_G3D_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_GPU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_GPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_GPU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_GPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_GPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_GPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_ENABLE, 0, 1, QCH_CON_AGPU_QCH), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_AGPU_QCH), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_AGPU_QCH), |
| SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_ENABLE, 0, 1, QCH_CON_G3D_CMU_G3D_QCH), |
| SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G3D_CMU_G3D_QCH), |
| SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G3D_CMU_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_G3DSFR_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_G3DSFR_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_G3DSFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_G3DSFR_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_G3DSFR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_G3DSFR_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_G3DSFR_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_G3DSFR_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_G3DSFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_G3DSFR_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_G3DSFR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_G3DSFR_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_G3D_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_G3D_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_G3D_QCH), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_IS_VRA_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_IS_VRA_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_IS_VRA_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_IS_VRA_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_IS_VRA_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_IS_VRA_USER), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IS_APB_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_IS_APB), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IS_APB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_IS_APB), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IS_APB_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_IS_APB), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IS_UID_IS_CMU_IS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_IS_UID_IS_CMU_IS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IS_UID_IS_CMU_IS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_IS_UID_IS_CMU_IS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IS_UID_IS_CMU_IS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_IS_UID_IS_CMU_IS_IPCLKPORT_PCLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_IS_ISP_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_IS_ISP_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_IS_ISP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_IS_ISP_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_IS_ISP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_IS_ISP_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCM_P_IS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCM_P_IS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCM_P_IS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCM_P_IS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCM_P_IS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCM_P_IS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_SYSREG_IS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_SYSREG_IS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_SYSREG_IS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_SYSREG_IS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_SYSREG_IS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_SYSREG_IS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_VRA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_VRA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_VRA_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_VRA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_VRA_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_VRA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_VRA_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_APB_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_APB_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_APB_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_APB_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_APB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_APB_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_PCLK_IS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_PCLK_IS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_PCLK_IS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_PCLK_IS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_PCLK_IS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_PCLK_IS), |
| SFR_ACCESS(CLKOUT_CON_BLK_IS_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_IS_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_IS_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_IS_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_IS_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_IS_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_IS_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_IS_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_IS_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_IS_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_IS_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_IS_CMU_CLKOUT1), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_IS_3AA_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_IS_3AA_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_IS_3AA_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_IS_3AA_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_IS_3AA_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_IS_3AA_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D1_IS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D1_IS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D1_IS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D1_IS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D1_IS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D1_IS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D0_IS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D0_IS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D0_IS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D0_IS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D0_IS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D0_IS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_3AA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_3AA_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_3AA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_3AA_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_3AA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_3AA_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_XIU_IS_D_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_XIU_IS_D), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_XIU_IS_D_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_XIU_IS_D), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_XIU_IS_D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_XIU_IS_D), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0_HALF_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0_HALF), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0_HALF_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0_HALF), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0_HALF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0_HALF), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1_HALF_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1_HALF), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1_HALF_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1_HALF), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1_HALF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1_HALF), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_3AA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_3AA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_3AA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_3AA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_3AA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_3AA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_DMA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_DMA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_DMA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_DMA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_DMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_DMA), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_IS_TPU_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_IS_TPU_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_IS_TPU_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_IS_TPU_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_IS_TPU_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_IS_TPU_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_TPU_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_TPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_TPU_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_TPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_TPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_TPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_SMMU_IS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_SMMU_IS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_SMMU_IS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_SMMU_IS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_SMMU_IS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_SMMU_IS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_TPU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_TPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_TPU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_TPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_TPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_TPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS1_ISP_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS1_ISP), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS1_ISP_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS1_ISP), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS1_ISP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS1_ISP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_3AA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_3AA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_3AA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_3AA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_3AA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_3AA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_CSIS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_CSIS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_CSIS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_CSIS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_CSIS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_CSIS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_VRA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_TPU_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_TPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_TPU_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_TPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_TPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_TPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_RT_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_RT), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_RT_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_RT), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_RT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_RT), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_NRT_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_NRT), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_NRT_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_NRT), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_NRT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_NRT), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_MCSC_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_MCSC_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_MCSC_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_MCSC_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_MCSC), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IS_3AA_HALF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_IS_3AA_HALF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IS_3AA_HALF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_IS_3AA_HALF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IS_3AA_HALF_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_CLK_IS_3AA_HALF), |
| SFR_ACCESS(QCH_CON_ASYNCM_P_IS_QCH_ENABLE, 0, 1, QCH_CON_ASYNCM_P_IS_QCH), |
| SFR_ACCESS(QCH_CON_ASYNCM_P_IS_QCH_CLOCK_REQ, 1, 1, QCH_CON_ASYNCM_P_IS_QCH), |
| SFR_ACCESS(QCH_CON_ASYNCM_P_IS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ASYNCM_P_IS_QCH), |
| SFR_ACCESS(QCH_CON_ASYNCS_D0_IS_QCH_ENABLE, 0, 1, QCH_CON_ASYNCS_D0_IS_QCH), |
| SFR_ACCESS(QCH_CON_ASYNCS_D0_IS_QCH_CLOCK_REQ, 1, 1, QCH_CON_ASYNCS_D0_IS_QCH), |
| SFR_ACCESS(QCH_CON_ASYNCS_D0_IS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ASYNCS_D0_IS_QCH), |
| SFR_ACCESS(QCH_CON_ASYNCS_D1_IS_QCH_ENABLE, 0, 1, QCH_CON_ASYNCS_D1_IS_QCH), |
| SFR_ACCESS(QCH_CON_ASYNCS_D1_IS_QCH_CLOCK_REQ, 1, 1, QCH_CON_ASYNCS_D1_IS_QCH), |
| SFR_ACCESS(QCH_CON_ASYNCS_D1_IS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ASYNCS_D1_IS_QCH), |
| SFR_ACCESS(QCH_CON_IS_CMU_IS_QCH_ENABLE, 0, 1, QCH_CON_IS_CMU_IS_QCH), |
| SFR_ACCESS(QCH_CON_IS_CMU_IS_QCH_CLOCK_REQ, 1, 1, QCH_CON_IS_CMU_IS_QCH), |
| SFR_ACCESS(QCH_CON_IS_CMU_IS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_IS_CMU_IS_QCH), |
| SFR_ACCESS(QCH_CON_BCM_NRT_QCH_ENABLE, 0, 1, QCH_CON_BCM_NRT_QCH), |
| SFR_ACCESS(QCH_CON_BCM_NRT_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_NRT_QCH), |
| SFR_ACCESS(QCH_CON_BCM_NRT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_NRT_QCH), |
| SFR_ACCESS(QCH_CON_BCM_RT_QCH_ENABLE, 0, 1, QCH_CON_BCM_RT_QCH), |
| SFR_ACCESS(QCH_CON_BCM_RT_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_RT_QCH), |
| SFR_ACCESS(QCH_CON_BCM_RT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_RT_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_IS_QCH_ENABLE, 0, 1, QCH_CON_SMMU_IS_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_IS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_IS_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_IS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_IS_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_IS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_IS_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_IS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_IS_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_IS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_IS_QCH), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_ISP_ENABLE, 0, 1, QCH_CON_IS5P15P0_IS_QCH_ISP), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_ISP_CLOCK_REQ, 1, 1, QCH_CON_IS5P15P0_IS_QCH_ISP), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_ISP_EXPIRE_VAL, 16, 10, QCH_CON_IS5P15P0_IS_QCH_ISP), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_MCSC_ENABLE, 0, 1, QCH_CON_IS5P15P0_IS_QCH_MCSC), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_MCSC_CLOCK_REQ, 1, 1, QCH_CON_IS5P15P0_IS_QCH_MCSC), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_MCSC_EXPIRE_VAL, 16, 10, QCH_CON_IS5P15P0_IS_QCH_MCSC), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_VRA_ENABLE, 0, 1, QCH_CON_IS5P15P0_IS_QCH_VRA), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_VRA_CLOCK_REQ, 1, 1, QCH_CON_IS5P15P0_IS_QCH_VRA), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_VRA_EXPIRE_VAL, 16, 10, QCH_CON_IS5P15P0_IS_QCH_VRA), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_CSIS_0_ENABLE, 0, 1, QCH_CON_IS5P15P0_IS_QCH_CSIS_0), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_CSIS_0_CLOCK_REQ, 1, 1, QCH_CON_IS5P15P0_IS_QCH_CSIS_0), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_CSIS_0_EXPIRE_VAL, 16, 10, QCH_CON_IS5P15P0_IS_QCH_CSIS_0), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_CSIS_1_ENABLE, 0, 1, QCH_CON_IS5P15P0_IS_QCH_CSIS_1), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_CSIS_1_CLOCK_REQ, 1, 1, QCH_CON_IS5P15P0_IS_QCH_CSIS_1), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_CSIS_1_EXPIRE_VAL, 16, 10, QCH_CON_IS5P15P0_IS_QCH_CSIS_1), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_IS_3AA_ENABLE, 0, 1, QCH_CON_IS5P15P0_IS_QCH_IS_3AA), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_IS_3AA_CLOCK_REQ, 1, 1, QCH_CON_IS5P15P0_IS_QCH_IS_3AA), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_IS_3AA_EXPIRE_VAL, 16, 10, QCH_CON_IS5P15P0_IS_QCH_IS_3AA), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_TPU_ENABLE, 0, 1, QCH_CON_IS5P15P0_IS_QCH_TPU), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_TPU_CLOCK_REQ, 1, 1, QCH_CON_IS5P15P0_IS_QCH_TPU), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_TPU_EXPIRE_VAL, 16, 10, QCH_CON_IS5P15P0_IS_QCH_TPU), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_CSIS_DMA_ENABLE, 0, 1, QCH_CON_IS5P15P0_IS_QCH_CSIS_DMA), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_CSIS_DMA_CLOCK_REQ, 1, 1, QCH_CON_IS5P15P0_IS_QCH_CSIS_DMA), |
| SFR_ACCESS(QCH_CON_IS5P15P0_IS_QCH_CSIS_DMA_EXPIRE_VAL, 16, 10, QCH_CON_IS5P15P0_IS_QCH_CSIS_DMA), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFCMSCL_MSCL_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_MFCMSCL_MSCL_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFCMSCL_MSCL_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MFCMSCL_MSCL_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_MFCMSCL_MSCL_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_MFCMSCL_MSCL_USER), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFCMSCL_APB_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MFCMSCL_APB), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFCMSCL_APB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MFCMSCL_APB), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFCMSCL_APB_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_MFCMSCL_APB), |
| SFR_ACCESS(CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFCMSCL_UID_MFCMSCL_CMU_MFCMSCL_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFCMSCL_UID_MFCMSCL_CMU_MFCMSCL_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFCMSCL_UID_MFCMSCL_CMU_MFCMSCL_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFCMSCL_UID_MFCMSCL_CMU_MFCMSCL_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFCMSCL_UID_MFCMSCL_CMU_MFCMSCL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFCMSCL_UID_MFCMSCL_CMU_MFCMSCL_IPCLKPORT_PCLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_MFCMSCL_MFC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_MFCMSCL_MFC_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHM_AXI_P_MFCMSCL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHM_AXI_P_MFCMSCL_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHM_AXI_P_MFCMSCL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHM_AXI_P_MFCMSCL_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHM_AXI_P_MFCMSCL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHM_AXI_P_MFCMSCL_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_AXI2APB_MFCMSCL_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_AXI2APB_MFCMSCL_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_AXI2APB_MFCMSCL_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_AXI2APB_MFCMSCL_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_AXI2APB_MFCMSCL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_AXI2APB_MFCMSCL_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MFC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MFC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MFC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MFC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MFC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SYSREG_MFCMSCL_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SYSREG_MFCMSCL_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SYSREG_MFCMSCL_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SYSREG_MFCMSCL_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SYSREG_MFCMSCL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SYSREG_MFCMSCL_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MFC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MFC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MFC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MFC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MFC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MSCL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MSCL_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MSCL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MSCL_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MSCL_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_APB_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_APB_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_APB_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_APB_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_APB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_APB_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_G2D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_G2D_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_G2D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_G2D_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_G2D_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SMMU_MFCMSCL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SMMU_MFCMSCL_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SMMU_MFCMSCL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SMMU_MFCMSCL_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SMMU_MFCMSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SMMU_MFCMSCL_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_XIU_D_MFCMSCL_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_XIU_D_MFCMSCL_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_XIU_D_MFCMSCL_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_XIU_D_MFCMSCL_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_XIU_D_MFCMSCL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_XIU_D_MFCMSCL_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_JPEG_IPCLKPORT_I_FIMP_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_JPEG_IPCLKPORT_I_FIMP_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_JPEG_IPCLKPORT_I_FIMP_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_JPEG_IPCLKPORT_I_FIMP_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_JPEG_IPCLKPORT_I_FIMP_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_JPEG_IPCLKPORT_I_FIMP_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHS_AXI_D_MFCMSCL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHS_AXI_D_MFCMSCL_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHS_AXI_D_MFCMSCL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHS_AXI_D_MFCMSCL_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHS_AXI_D_MFCMSCL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHS_AXI_D_MFCMSCL_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MSCL_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MSCL_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MSCL_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MSCL_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MSCL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MSCL_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKS), |
| SFR_ACCESS(QCH_CON_G2D_QCH_ENABLE, 0, 1, QCH_CON_G2D_QCH), |
| SFR_ACCESS(QCH_CON_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G2D_QCH), |
| SFR_ACCESS(QCH_CON_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G2D_QCH), |
| SFR_ACCESS(QCH_CON_JPEG_QCH_ENABLE, 0, 1, QCH_CON_JPEG_QCH), |
| SFR_ACCESS(QCH_CON_JPEG_QCH_CLOCK_REQ, 1, 1, QCH_CON_JPEG_QCH), |
| SFR_ACCESS(QCH_CON_JPEG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_JPEG_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MFCMSCL_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MFCMSCL_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MFCMSCL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_MFCMSCL_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_MFCMSCL_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_MFCMSCL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_MFC_QCH_ENABLE, 0, 1, QCH_CON_MFC_QCH), |
| SFR_ACCESS(QCH_CON_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC_QCH), |
| SFR_ACCESS(QCH_CON_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MFC_QCH), |
| SFR_ACCESS(QCH_CON_MFCMSCL_CMU_MFCMSCL_QCH_ENABLE, 0, 1, QCH_CON_MFCMSCL_CMU_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_MFCMSCL_CMU_MFCMSCL_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFCMSCL_CMU_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_MFCMSCL_CMU_MFCMSCL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MFCMSCL_CMU_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_MSCL_QCH_ENABLE, 0, 1, QCH_CON_MSCL_QCH), |
| SFR_ACCESS(QCH_CON_MSCL_QCH_CLOCK_REQ, 1, 1, QCH_CON_MSCL_QCH), |
| SFR_ACCESS(QCH_CON_MSCL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MSCL_QCH), |
| SFR_ACCESS(QCH_CON_BCM_MFCMSCL_QCH_ENABLE, 0, 1, QCH_CON_BCM_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_BCM_MFCMSCL_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_BCM_MFCMSCL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_MFCMSCL_QCH_ENABLE, 0, 1, QCH_CON_SMMU_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_MFCMSCL_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_MFCMSCL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MFCMSCL_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MFCMSCL_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MFCMSCL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MFCMSCL_QCH), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X), |
| SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_MIF_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_MIF_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_MIF_CMUREF), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_MIF_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_MIF_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MIF_CMU_CLKOUT0), |
| SFR_ACCESS(PLL_CON0_PLL_MEM_DIV_P, 8, 6, PLL_CON0_PLL_MEM), |
| SFR_ACCESS(PLL_CON0_PLL_MEM_DIV_M, 16, 10, PLL_CON0_PLL_MEM), |
| SFR_ACCESS(PLL_CON0_PLL_MEM_DIV_S, 0, 3, PLL_CON0_PLL_MEM), |
| SFR_ACCESS(PLL_CON0_PLL_MEM_ENABLE, 31, 1, PLL_CON0_PLL_MEM), |
| SFR_ACCESS(PLL_CON0_PLL_MEM_STABLE, 29, 1, PLL_CON0_PLL_MEM), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_MEM_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MEM), |
| SFR_ACCESS(CLK_CON_DIV_PLL_MEM_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_MEM_DIV2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_MIF_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_MIF_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_MIF_BUS), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MIF_BUS), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF_BUS), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_MIF_BUS), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MIF_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_BUSP_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_MIF_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB_BRIDGE_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB_BRIDGE_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB_BRIDGE_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB_BRIDGE_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB_BRIDGE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB_BRIDGE_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_COREP0_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_COREP0_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_COREP0_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_COREP0_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_COREP0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_COREP0_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_COREP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_COREP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_COREP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_COREP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_COREP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_COREP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_2MB_BUSCP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_2MB_BUSCP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_2MB_BUSCP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_2MB_BUSCP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_2MB_BUSCP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_2MB_BUSCP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_CCI_400_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_CCI_400_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_CCI_400_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_CCI_400_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_CCI_400_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_CCI_400_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_FSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_FSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_FSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_FSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_FSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPNRT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPNRT_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPNRT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPNRT_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPNRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPNRT_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPRT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPRT_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPRT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPRT_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPRT_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_MFCMSCL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_MFCMSCL_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_MFCMSCL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_MFCMSCL_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_MFCMSCL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_MFCMSCL_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_IS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_IS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_IS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_IS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_IS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_IS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_MFCMSCL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_MFCMSCL_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_MFCMSCL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_MFCMSCL_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_MFCMSCL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_MFCMSCL_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_GNSSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_GNSSS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_GNSSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_GNSSS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_GNSSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_GNSSS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_CCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_CCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_CCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_CCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_CCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_HCLK_AHB2APB_BRIDGE_MIF_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_HCLK_AHB2APB_BRIDGE_MIF), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_HCLK_AHB2APB_BRIDGE_MIF_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_HCLK_AHB2APB_BRIDGE_MIF), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_HCLK_AHB2APB_BRIDGE_MIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_HCLK_AHB2APB_BRIDGE_MIF), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_DDR_PHY0_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_DDR_PHY0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_DDR_PHY0_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_DDR_PHY0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_DDR_PHY0_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_DDR_PHY0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_DMC0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_DMC0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_DMC0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_DMC0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_DMC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_DMC0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_SECURE_DMC0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_SECURE_DMC0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_SECURE_DMC0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_SECURE_DMC0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_SECURE_DMC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_SECURE_DMC0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PF_DMC0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PF_DMC0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PF_DMC0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PF_DMC0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PF_DMC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PF_DMC0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PPMPU_DMC0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PPMPU_DMC0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PPMPU_DMC0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PPMPU_DMC0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PPMPU_DMC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PPMPU_DMC0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_CCI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_CCI_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_CCI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_CCI_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_CCI_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_PHY_CLK2X_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_PHY_CLK2X_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_PHY_CLK2X_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_PHY_CLK2X_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_PHY_CLK2X_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_PHY_CLK2X_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_ACLK_DMC0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_ACLK_DMC0), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_ACLK_DMC0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_ACLK_DMC0), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_ACLK_DMC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_ACLK_DMC0), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF_SWITCH_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_MIF_SWITCH_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MIF_SWITCH_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_MIF_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_MIF_SWITCH_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_MIF_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MIF_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_MIF_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_MIF_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLK_MIF_CCI_USER_BUSY, 7, 1, PLL_CON0_MUX_CLK_MIF_CCI_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLK_MIF_CCI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLK_MIF_CCI_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLK_MIF_CCI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLK_MIF_CCI_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF_GIC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_MIF_GIC), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF_GIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_MIF_GIC), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF_GIC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_MIF_GIC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_GIC400_AIHWACG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_GIC400_AIHWACG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_GIC400_AIHWACG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_GIC400_AIHWACG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_GIC400_AIHWACG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_GIC400_AIHWACG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_I_PCLK_ASYNCSFR_WR_DMC_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_I_PCLK_ASYNCSFR_WR_DMC_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_I_PCLK_ASYNCSFR_WR_DMC_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_I_PCLK_ASYNCSFR_WR_DMC_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_I_PCLK_ASYNCSFR_WR_DMC_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_I_PCLK_ASYNCSFR_WR_DMC_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_APBBR_DMC_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_APBBR_DMC_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_APBBR_DMC_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_APBBR_DMC_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_APBBR_DMC_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_APBBR_DMC_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_PDMA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_PDMA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_PDMA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_PDMA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_PDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_PDMA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_SDMA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_SDMA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_SDMA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_SDMA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_SDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_SDMA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_64TO128_CSSYS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_64TO128_CSSYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_64TO128_CSSYS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_64TO128_CSSYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_64TO128_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_64TO128_CSSYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_DDRPHY_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_DDRPHY_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_DDRPHY_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_DDRPHY_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_DDRPHY_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_DDRPHY_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_MCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_MCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_MCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_MCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_MCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_MCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_XIU_D_PDMA_3X1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_XIU_D_PDMA_3X1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_XIU_D_PDMA_3X1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_XIU_D_PDMA_3X1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_XIU_D_PDMA_3X1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_XIU_D_PDMA_3X1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_PHY_CLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF_PHY_CLKM), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_MIF_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_MIF_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MIF_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_ADS_APB_G_CSSYS_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_ADS_APB_G_CSSYS_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_ADS_APB_G_CSSYS_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_ADS_APB_G_CSSYS_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_ADS_APB_G_CSSYS_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_ADS_APB_G_CSSYS_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_CSSYS_DBG_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_CSSYS_DBG_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_CSSYS_DBG_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_CSSYS_DBG_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_CSSYS_DBG_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_CSSYS_DBG_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_CORE_CSSYS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_CORE_CSSYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_CORE_CSSYS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_CORE_CSSYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_CORE_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_CORE_CSSYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_GIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_GIC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_GIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_GIC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_GIC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFR_APBIF_CMU_CMU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFR_APBIF_CMU_CMU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFR_APBIF_CMU_CMU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFR_APBIF_CMU_CMU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFR_APBIF_CMU_CMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFR_APBIF_CMU_CMU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF_CCI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_MIF_CCI), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF_CCI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_MIF_CCI), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF_CCI_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_MIF_CCI), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_CCI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MIF_CCI), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_CCI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF_CCI), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_CCI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_MIF_CCI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_ABOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_ABOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_MIF_PHY_CLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_MIF_PHY_CLKM), |
| SFR_ACCESS(CLK_CON_GAT_CLK_MIF_PHY_CLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_MIF_PHY_CLKM), |
| SFR_ACCESS(CLK_CON_GAT_CLK_MIF_PHY_CLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_MIF_PHY_CLKM), |
| SFR_ACCESS(DMYQCH_CON_AXI2AHB_CORE_CSSYS_QCH_ENABLE, 0, 1, DMYQCH_CON_AXI2AHB_CORE_CSSYS_QCH), |
| SFR_ACCESS(DMYQCH_CON_AXI2AHB_CORE_CSSYS_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_AXI2AHB_CORE_CSSYS_QCH), |
| SFR_ACCESS(QCH_CON_CCI_400_QCH_ENABLE, 0, 1, QCH_CON_CCI_400_QCH), |
| SFR_ACCESS(QCH_CON_CCI_400_QCH_CLOCK_REQ, 1, 1, QCH_CON_CCI_400_QCH), |
| SFR_ACCESS(QCH_CON_CCI_400_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CCI_400_QCH), |
| SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH), |
| SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH), |
| SFR_ACCESS(QCH_CON_GIC400_AIHWACG_QCH_ENABLE, 0, 1, QCH_CON_GIC400_AIHWACG_QCH), |
| SFR_ACCESS(QCH_CON_GIC400_AIHWACG_QCH_CLOCK_REQ, 1, 1, QCH_CON_GIC400_AIHWACG_QCH), |
| SFR_ACCESS(QCH_CON_GIC400_AIHWACG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GIC400_AIHWACG_QCH), |
| SFR_ACCESS(QCH_CON_LBLK_MIF_QCH_DMC_ENABLE, 0, 1, QCH_CON_LBLK_MIF_QCH_DMC), |
| SFR_ACCESS(QCH_CON_LBLK_MIF_QCH_DMC_CLOCK_REQ, 1, 1, QCH_CON_LBLK_MIF_QCH_DMC), |
| SFR_ACCESS(QCH_CON_LBLK_MIF_QCH_DMC_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_MIF_QCH_DMC), |
| SFR_ACCESS(QCH_CON_LBLK_MIF_QCH_BCM_ENABLE, 0, 1, QCH_CON_LBLK_MIF_QCH_BCM), |
| SFR_ACCESS(QCH_CON_LBLK_MIF_QCH_BCM_CLOCK_REQ, 1, 1, QCH_CON_LBLK_MIF_QCH_BCM), |
| SFR_ACCESS(QCH_CON_LBLK_MIF_QCH_BCM_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_MIF_QCH_BCM), |
| SFR_ACCESS(QCH_CON_LBLK_MIF_QCH_APBBR_ENABLE, 0, 1, QCH_CON_LBLK_MIF_QCH_APBBR), |
| SFR_ACCESS(QCH_CON_LBLK_MIF_QCH_APBBR_CLOCK_REQ, 1, 1, QCH_CON_LBLK_MIF_QCH_APBBR), |
| SFR_ACCESS(QCH_CON_LBLK_MIF_QCH_APBBR_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_MIF_QCH_APBBR), |
| SFR_ACCESS(DMYQCH_CON_LBLK_MIF_QCH_ASYNCSFR_ENABLE, 0, 1, DMYQCH_CON_LBLK_MIF_QCH_ASYNCSFR), |
| SFR_ACCESS(DMYQCH_CON_LBLK_MIF_QCH_ASYNCSFR_CLOCK_REQ, 1, 1, DMYQCH_CON_LBLK_MIF_QCH_ASYNCSFR), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ABOX_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_APM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_APM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_APM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_APM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_CP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_CP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_CP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_CP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_CSSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_CSSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_CSSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_FSYS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_GNSS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_GNSS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_GNSS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_GNSS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPNRT_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_ISPNRT_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPNRT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_ISPNRT_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPNRT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_ISPNRT_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPRT_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_ISPRT_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPRT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_ISPRT_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPRT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_ISPRT_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_MFCMSCL_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_MFCMSCL_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_MFCMSCL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_WLBT_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_WLBT_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_WLBT_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_WLBT_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_APM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_APM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_APM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_DISPAUD_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_DISPAUD_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_DISPAUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_DISPAUD_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_DISPAUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_DISPAUD_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_FSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_IS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_IS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_IS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_IS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_IS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_IS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MFCMSCL_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MFCMSCL_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MFCMSCL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MFCMSCL_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_PERI_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_PERI_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_PERI_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_PERI_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_QCH_S0_ENABLE, 0, 1, QCH_CON_MAILBOX_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_QCH_S0_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_QCH_S0_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_ABOX_QCH_S0_ENABLE, 0, 1, QCH_CON_MAILBOX_ABOX_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_ABOX_QCH_S0_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_ABOX_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_ABOX_QCH_S0_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_ABOX_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_GNSSS_QCH_S0_ENABLE, 0, 1, QCH_CON_MAILBOX_GNSSS_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_GNSSS_QCH_S0_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_GNSSS_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_GNSSS_QCH_S0_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_GNSSS_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_SECURE_QCH_S0_ENABLE, 0, 1, QCH_CON_MAILBOX_SECURE_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_SECURE_QCH_S0_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_SECURE_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_SECURE_QCH_S0_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_SECURE_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_WLBT0_QCH_S0_ENABLE, 0, 1, QCH_CON_MAILBOX_WLBT0_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_WLBT0_QCH_S0_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_WLBT0_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_WLBT0_QCH_S0_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_WLBT0_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_WLBT1_QCH_S0_ENABLE, 0, 1, QCH_CON_MAILBOX_WLBT1_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_WLBT1_QCH_S0_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_WLBT1_QCH_S0), |
| SFR_ACCESS(QCH_CON_MAILBOX_WLBT1_QCH_S0_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_WLBT1_QCH_S0), |
| SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_ENABLE, 0, 1, QCH_CON_MIF_CMU_MIF_QCH), |
| SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_MIF_CMU_MIF_QCH), |
| SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MIF_CMU_MIF_QCH), |
| SFR_ACCESS(QCH_CON_PDMA_CORE_QCH_ENABLE, 0, 1, QCH_CON_PDMA_CORE_QCH), |
| SFR_ACCESS(QCH_CON_PDMA_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_PDMA_CORE_QCH), |
| SFR_ACCESS(QCH_CON_PDMA_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PDMA_CORE_QCH), |
| SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_ENABLE, 0, 1, QCH_CON_PPCFW_G3D_QCH), |
| SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPCFW_G3D_QCH), |
| SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPCFW_G3D_QCH), |
| SFR_ACCESS(QCH_CON_BCM_ACE_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_BCM_ACE_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_ACE_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_ACE_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_ACE_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_ACE_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_ACE_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_BCM_ACE_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_ACE_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_ACE_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_ACE_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_ACE_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_QE_QCH_ENABLE, 0, 1, QCH_CON_QE_QCH), |
| SFR_ACCESS(QCH_CON_QE_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_QCH), |
| SFR_ACCESS(QCH_CON_QE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_QCH), |
| SFR_ACCESS(DMYQCH_CON_RSTNSYNC_CLK_MIF_CCI_QCH_OCC_ENABLE, 0, 1, DMYQCH_CON_RSTNSYNC_CLK_MIF_CCI_QCH_OCC), |
| SFR_ACCESS(DMYQCH_CON_RSTNSYNC_CLK_MIF_CCI_QCH_OCC_CLOCK_REQ, 1, 1, DMYQCH_CON_RSTNSYNC_CLK_MIF_CCI_QCH_OCC), |
| SFR_ACCESS(QCH_CON_SFR_APBIF_CMU_CMU_QCH_ENABLE, 0, 1, QCH_CON_SFR_APBIF_CMU_CMU_QCH), |
| SFR_ACCESS(QCH_CON_SFR_APBIF_CMU_CMU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SFR_APBIF_CMU_CMU_QCH), |
| SFR_ACCESS(QCH_CON_SFR_APBIF_CMU_CMU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SFR_APBIF_CMU_CMU_QCH), |
| SFR_ACCESS(QCH_CON_SPDMA_CORE_QCH_ENABLE, 0, 1, QCH_CON_SPDMA_CORE_QCH), |
| SFR_ACCESS(QCH_CON_SPDMA_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPDMA_CORE_QCH), |
| SFR_ACCESS(QCH_CON_SPDMA_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPDMA_CORE_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MIF_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MIF_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MIF_QCH), |
| SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_CORE_QCH), |
| SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_CORE_QCH), |
| SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_CORE_QCH), |
| SFR_ACCESS(QCH_CON_TREX_P_CORE_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_CORE_QCH), |
| SFR_ACCESS(QCH_CON_TREX_P_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_CORE_QCH), |
| SFR_ACCESS(QCH_CON_TREX_P_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P_CORE_QCH), |
| SFR_ACCESS(QCH_CON_WRAP_ADC_IF_QCH_0_ENABLE, 0, 1, QCH_CON_WRAP_ADC_IF_QCH_0), |
| SFR_ACCESS(QCH_CON_WRAP_ADC_IF_QCH_0_CLOCK_REQ, 1, 1, QCH_CON_WRAP_ADC_IF_QCH_0), |
| SFR_ACCESS(QCH_CON_WRAP_ADC_IF_QCH_0_EXPIRE_VAL, 16, 10, QCH_CON_WRAP_ADC_IF_QCH_0), |
| SFR_ACCESS(QCH_CON_WRAP_ADC_IF_QCH_1_ENABLE, 0, 1, QCH_CON_WRAP_ADC_IF_QCH_1), |
| SFR_ACCESS(QCH_CON_WRAP_ADC_IF_QCH_1_CLOCK_REQ, 1, 1, QCH_CON_WRAP_ADC_IF_QCH_1), |
| SFR_ACCESS(QCH_CON_WRAP_ADC_IF_QCH_1_EXPIRE_VAL, 16, 10, QCH_CON_WRAP_ADC_IF_QCH_1), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_IPCLKPORT_PCLK), |
| SFR_ACCESS(QCH_CON_MODEM_CMU_QCH_ENABLE, 0, 1, QCH_CON_MODEM_CMU_QCH), |
| SFR_ACCESS(QCH_CON_MODEM_CMU_QCH_CLOCK_REQ, 1, 1, QCH_CON_MODEM_CMU_QCH), |
| SFR_ACCESS(QCH_CON_MODEM_CMU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MODEM_CMU_QCH), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERI_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_PERI_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERI_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_PERI_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERI_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_PERI_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERI_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_PERI_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERI_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_PERI_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERI_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_PERI_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C6_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C6_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C6_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C6_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C6_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C6_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C0_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C0_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C0_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C1_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C1_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C1_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C1_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C1_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C1_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C2_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C2_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C2_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C2_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C2_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C2_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C3_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C3_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C3_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C3_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C3_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C3_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C4_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C4_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C4_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C4_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C4_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C4_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C5_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C5_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C5_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C5_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C5_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C5_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_PWM_MOTOR_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_PWM_MOTOR_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_PWM_MOTOR_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_PWM_MOTOR_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_PWM_MOTOR_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_PWM_MOTOR_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_SPI_EXT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_SPI_EXT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_SPI_EXT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_SPI_EXT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_SPI_EXT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_SPI_EXT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_SPI_EXT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_SPI_EXT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_SPI_EXT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_SPI_EXT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_SPI_EXT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_SPI_EXT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_EXT_UCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_EXT_UCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_EXT_UCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_EXT_UCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_EXT_UCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_EXT_UCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_EXT_UCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_EXT_UCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_EXT_UCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_EXT_UCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_EXT_UCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_EXT_UCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C3_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C3_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C3_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C3_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C3_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C3_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C1_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C1_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C1_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C1_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C1_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C1_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C0_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C0_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C0_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C2_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C2_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C2_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C2_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C2_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C2_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SECUCON_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SECUCON_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SECUCON_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SECUCON_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SECUCON_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SECUCON_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_PERI_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_PERI_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_PERI_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_PERI_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_PERI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_PERI_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP_BR_PERI_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP_BR_PERI_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP_BR_PERI_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP_BR_PERI_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP_BR_PERI_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP_BR_PERI_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC0_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC0_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC0_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC0_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC0_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC0_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC1_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC1_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC1_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC1_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC1_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC1_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_GPIO_TOP_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_GPIO_TOP_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_GPIO_TOP_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_GPIO_TOP_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_GPIO_TOP_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_GPIO_TOP_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_SCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_SCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_SCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_SCLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERI_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERI_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_UART_0_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERI_UART_0_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_UART_0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_UART_0_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERI_UART_0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERI_UART_0_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_UART_1_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERI_UART_1_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_UART_1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_UART_1_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERI_UART_1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERI_UART_1_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI0_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERI_USI0_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_USI0_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERI_USI0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERI_USI0_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI1_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERI_USI1_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_USI1_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERI_USI1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERI_USI1_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI2_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERI_USI2_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI2_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_USI2_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERI_USI2_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERI_USI2_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERI_SPI0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERI_SPI0_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERI_SPI1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERI_SPI1_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_UART_2_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERI_UART_2_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_UART_2_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_UART_2_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERI_UART_2_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERI_UART_2_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_EXT_UCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_EXT_UCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_EXT_UCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_EXT_UCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_EXT_UCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_EXT_UCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_PCLK), |
| SFR_ACCESS(QCH_CON_BUSIF_TMU_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_TMU_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_TMU_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_TMU_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_TMU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_TMU_QCH), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C0_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_I2C0), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C0_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_I2C0), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C0_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_I2C0), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C1_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_I2C1), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C1_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_I2C1), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C1_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_I2C1), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C2_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_I2C2), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C2_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_I2C2), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C2_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_I2C2), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C3_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_I2C3), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C3_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_I2C3), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C3_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_I2C3), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C4_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_I2C4), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C4_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_I2C4), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C4_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_I2C4), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C5_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_I2C5), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C5_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_I2C5), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C5_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_I2C5), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C6_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_I2C6), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C6_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_I2C6), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_I2C6_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_I2C6), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_PWM_MOTOR_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_PWM_MOTOR), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_PWM_MOTOR_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_PWM_MOTOR), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_PWM_MOTOR_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_PWM_MOTOR), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_SPI0_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_SPI0), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_SPI0_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_SPI0), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_SPI0_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_SPI0), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_SPI1_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_SPI1), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_SPI1_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_SPI1), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_SPI1_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_SPI1), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_USI2_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_USI2), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_USI2_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_USI2), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_USI2_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_USI2), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_UART0_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_UART0), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_UART0_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_UART0), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_UART0_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_UART0), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_UART1_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_UART1), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_UART1_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_UART1), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_UART1_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_UART1), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_HSI2C0_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_HSI2C0), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_HSI2C0_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_HSI2C0), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_HSI2C0_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_HSI2C0), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_HSI2C1_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_HSI2C1), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_HSI2C1_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_HSI2C1), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_HSI2C1_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_HSI2C1), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_HSI2C2_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_HSI2C2), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_HSI2C2_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_HSI2C2), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_HSI2C2_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_HSI2C2), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_HSI2C3_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_HSI2C3), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_HSI2C3_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_HSI2C3), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_HSI2C3_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_HSI2C3), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_USI0_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_USI0), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_USI0_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_USI0), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_USI0_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_USI0), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_USI1_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_USI1), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_USI1_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_USI1), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_USI1_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_USI1), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_GPIO_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_GPIO), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_GPIO_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_GPIO), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_GPIO_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_GPIO), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_UART2_ENABLE, 0, 1, QCH_CON_LBLK_PERIC_QCH_UART2), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_UART2_CLOCK_REQ, 1, 1, QCH_CON_LBLK_PERIC_QCH_UART2), |
| SFR_ACCESS(QCH_CON_LBLK_PERIC_QCH_UART2_EXPIRE_VAL, 16, 10, QCH_CON_LBLK_PERIC_QCH_UART2), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_PERI_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_PERI_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_PERI_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_PERI_QCH), |
| SFR_ACCESS(QCH_CON_MCT_QCH_ENABLE, 0, 1, QCH_CON_MCT_QCH), |
| SFR_ACCESS(QCH_CON_MCT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCT_QCH), |
| SFR_ACCESS(QCH_CON_MCT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MCT_QCH), |
| SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_ENABLE, 0, 1, QCH_CON_OTP_CON_TOP_QCH), |
| SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_OTP_CON_TOP_QCH), |
| SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_OTP_CON_TOP_QCH), |
| SFR_ACCESS(QCH_CON_PERI_CMU_PERI_QCH_ENABLE, 0, 1, QCH_CON_PERI_CMU_PERI_QCH), |
| SFR_ACCESS(QCH_CON_PERI_CMU_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERI_CMU_PERI_QCH), |
| SFR_ACCESS(QCH_CON_PERI_CMU_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PERI_CMU_PERI_QCH), |
| SFR_ACCESS(QCH_CON_SECUCON_QCH_ENABLE, 0, 1, QCH_CON_SECUCON_QCH), |
| SFR_ACCESS(QCH_CON_SECUCON_QCH_CLOCK_REQ, 1, 1, QCH_CON_SECUCON_QCH), |
| SFR_ACCESS(QCH_CON_SECUCON_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SECUCON_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_PERI_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERI_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERI_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_PERI_QCH), |
| SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_WDT_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_ENABLE, 0, 1, QCH_CON_WDT_CLUSTER1_QCH), |
| SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_CLUSTER1_QCH), |
| SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_CLUSTER1_QCH), |
| /*====================The section of controller option SFR ACCESS instance===================*/ |
| SFR_ACCESS(APM_ENABLE_POWER_MANAGEMENT, 29, 1, APM_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(APM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, APM_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(CMU_ENABLE_POWER_MANAGEMENT, 29, 1, CMU_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(CMU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CMU_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(CPUCL0_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL0_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(CPUCL0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL0_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(CPUCL1_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL1_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(CPUCL1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL1_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(DISPAUD_ENABLE_POWER_MANAGEMENT, 29, 1, DISPAUD_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(DISPAUD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DISPAUD_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(FSYS_ENABLE_POWER_MANAGEMENT, 29, 1, FSYS_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(FSYS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, FSYS_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(G3D_ENABLE_POWER_MANAGEMENT, 29, 1, G3D_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(G3D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, G3D_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(IS_ENABLE_POWER_MANAGEMENT, 29, 1, IS_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(IS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, IS_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(MFCMSCL_ENABLE_POWER_MANAGEMENT, 29, 1, MFCMSCL_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(MFCMSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MFCMSCL_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(MIF_ENABLE_POWER_MANAGEMENT, 29, 1, MIF_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(MIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MIF_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(MODEM_ENABLE_POWER_MANAGEMENT, 29, 1, MODEM_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(MODEM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MODEM_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(PERI_ENABLE_POWER_MANAGEMENT, 29, 1, PERI_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(PERI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERI_CMU_CONTROLLER_OPTION), |
| }; |
| |
| unsigned int cmucal_sfr_access_size = 2282; |
| |