drivers/soc/samsung/cal-if/exynos7872/cmucal-qch.h

#ifndef __CMUCAL_QCH_H__
#define __CMUCAL_QCH_H__

#include "../cmucal.h"

/*=================CMUCAL version: S5E7872================================*/

/*=================Q-channel information================================*/

enum qch_id {
	APBIF_GPIO_ALIVE_QCH = QCH_TYPE,
	APBIF_PMU_ALIVE_QCH,
	APM_QCH_CPU,
	APM_QCH_INTMEM,
	APM_QCH_OSCCLK,
	APM_QCH_DBG,
	APM_QCH_SYS,
	APM_CMU_APM_QCH,
	I2C_APM_QCH,
	IP_BATCHER_AP_QCH,
	IP_BATCHER_CP_QCH,
	LHM_AXI_P_ALIVE_QCH,
	LHS_AXI_D_ALIVE_QCH,
	MAILBOX_APM2AP_QCH,
	MAILBOX_APM2CP_QCH,
	MAILBOX_APM2GNSS_QCH,
	MAILBOX_APM2WLBT_QCH,
	MP_APBSEMA_HWACG_2CH_QCH,
	SPEEDY_QCH,
	SPEEDY_QCH_OSCCLK,
	SYSREG_APM_QCH,
	WDT_APM_QCH,
	WDT_APM_QCH_OSCCLK,
	CMU_CMU_CMUREF_QCH,
	DFTMUX_TOP_QCH_CLK_CSIS0,
	DFTMUX_TOP_QCH_CLK_CSIS1,
	DFTMUX_TOP_QCH_CLK_CSIS2,
	CLUSTER0_QCH_CPU,
	CLUSTER0_QCH_DBG,
	CMU_CPUCL0_SHORTSTOP_QCH,
	CPUCL0_CMU_CPUCL0_QCH,
	CSSYS_DBG_QCH,
	DUMP_PC_CPUCL0_QCH,
	LHM_AXI_P_CPUCL0_QCH,
	LHS_ACE_D_CPUCL0_QCH,
	LHS_AXI_T_CSSYS_DBG_QCH,
	SECJTAG_QCH,
	SYSREG_CPUCL0_QCH,
	CLUSTER1_QCH_CPU,
	CLUSTER1_QCH_DBG,
	CMU_CPUCL1_SHORTSTOP_QCH,
	CPUCL1_CMU_CPUCL1_QCH,
	DUMP_PC_CPUCL1_QCH,
	LHM_AXI_P_CPUCL1_QCH,
	LHS_ACE_D_CPUCL1_QCH,
	SYSREG_CPUCL1_QCH,
	ABOX_QCH_ABOX,
	ABOX_QCH_CPU,
	ABOX_QCH_BUS,
	ABOX_QCH_UAIF0,
	ABOX_QCH_UAIF2,
	ABOX_QCH_UAIF3,
	ABOX_QCH_FM,
	DISPAUD_CMU_DISPAUD_QCH,
	DPU_QCH_DPP,
	DPU_QCH_DMA,
	DPU_QCH_DECON0,
	GPIO_DISPAUD_QCH,
	LHM_AXI_P_DISPAUD_QCH,
	LHS_AXI_D_ABOX_QCH,
	LHS_AXI_D_DPU_QCH,
	BCM_ABOX_QCH,
	BCM_DPU_QCH,
	SMMU_ABOX_QCH,
	SMMU_DPU_QCH,
	SYSREG_DISPAUD_QCH,
	WDT_ABOXCPU_QCH,
	ADM_AHB_SSS_QCH,
	FSYS_CMU_FSYS_QCH,
	GPIO_FSYS_QCH,
	LHM_AXI_P_FSYS_QCH,
	LHS_AXI_D_FSYS_QCH,
	MMC_CARD_QCH,
	MMC_EMBD_QCH,
	MMC_SDIO_QCH,
	BCM_FSYS_QCH,
	RTIC_QCH,
	SSS_QCH,
	SYSREG_FSYS_QCH,
	USB20DRD_QCH_HSDRD,
	USB20DRD_QCH_USB,
	AGPU_QCH,
	G3D_CMU_G3D_QCH,
	LHM_AXI_G3DSFR_QCH,
	LHM_AXI_P_G3D_QCH,
	LHS_AXI_D_G3D_QCH,
	LHS_AXI_G3DSFR_QCH,
	SYSREG_G3D_QCH,
	ASYNCM_P_IS_QCH,
	ASYNCS_D0_IS_QCH,
	ASYNCS_D1_IS_QCH,
	IS_CMU_IS_QCH,
	BCM_NRT_QCH,
	BCM_RT_QCH,
	SMMU_IS_QCH,
	SYSREG_IS_QCH,
	IS5P15P0_IS_QCH_ISP,
	IS5P15P0_IS_QCH_MCSC,
	IS5P15P0_IS_QCH_VRA,
	IS5P15P0_IS_QCH_CSIS_0,
	IS5P15P0_IS_QCH_CSIS_1,
	IS5P15P0_IS_QCH_IS_3AA,
	IS5P15P0_IS_QCH_TPU,
	IS5P15P0_IS_QCH_CSIS_DMA,
	G2D_QCH,
	JPEG_QCH,
	LHM_AXI_P_MFCMSCL_QCH,
	LHS_AXI_D_MFCMSCL_QCH,
	MFC_QCH,
	MFCMSCL_CMU_MFCMSCL_QCH,
	MSCL_QCH,
	BCM_MFCMSCL_QCH,
	SMMU_MFCMSCL_QCH,
	SYSREG_MFCMSCL_QCH,
	AXI2AHB_CORE_CSSYS_QCH,
	CCI_400_QCH,
	CMU_MIF_CMUREF_QCH,
	GIC400_AIHWACG_QCH,
	LBLK_MIF_QCH_DMC,
	LBLK_MIF_QCH_BCM,
	LBLK_MIF_QCH_APBBR,
	LBLK_MIF_QCH_ASYNCSFR,
	LHM_ACE_D_CPUCL0_QCH,
	LHM_ACE_D_CPUCL1_QCH,
	LHM_AXI_D_ABOX_QCH,
	LHM_AXI_D_APM_QCH,
	LHM_AXI_D_CP_QCH,
	LHM_AXI_D_CSSYS_QCH,
	LHM_AXI_D_DPU_QCH,
	LHM_AXI_D_FSYS_QCH,
	LHM_AXI_D_G3D_QCH,
	LHM_AXI_D_GNSS_QCH,
	LHM_AXI_D_ISPNRT_QCH,
	LHM_AXI_D_ISPRT_QCH,
	LHM_AXI_D_MFCMSCL_QCH,
	LHM_AXI_D_WLBT_QCH,
	LHM_AXI_P_CP_QCH,
	LHS_AXI_P_APM_QCH,
	LHS_AXI_P_CPUCL0_QCH,
	LHS_AXI_P_CPUCL1_QCH,
	LHS_AXI_P_DISPAUD_QCH,
	LHS_AXI_P_FSYS_QCH,
	LHS_AXI_P_G3D_QCH,
	LHS_AXI_P_IS_QCH,
	LHS_AXI_P_MFCMSCL_QCH,
	LHS_AXI_P_PERI_QCH,
	MAILBOX_QCH_S0,
	MAILBOX_ABOX_QCH_S0,
	MAILBOX_GNSSS_QCH_S0,
	MAILBOX_SECURE_QCH_S0,
	MAILBOX_WLBT0_QCH_S0,
	MAILBOX_WLBT1_QCH_S0,
	MIF_CMU_MIF_QCH,
	PDMA_CORE_QCH,
	PPCFW_G3D_QCH,
	BCM_ACE_CPUCL0_QCH,
	BCM_ACE_CPUCL1_QCH,
	QE_QCH,
	RSTNSYNC_CLK_MIF_CCI_QCH_OCC,
	SFR_APBIF_CMU_CMU_QCH,
	SPDMA_CORE_QCH,
	SYSREG_MIF_QCH,
	TREX_D_CORE_QCH,
	TREX_P_CORE_QCH,
	WRAP_ADC_IF_QCH_0,
	WRAP_ADC_IF_QCH_1,
	MODEM_CMU_QCH,
	BUSIF_TMU_QCH,
	LBLK_PERIC_QCH_I2C0,
	LBLK_PERIC_QCH_I2C1,
	LBLK_PERIC_QCH_I2C2,
	LBLK_PERIC_QCH_I2C3,
	LBLK_PERIC_QCH_I2C4,
	LBLK_PERIC_QCH_I2C5,
	LBLK_PERIC_QCH_I2C6,
	LBLK_PERIC_QCH_PWM_MOTOR,
	LBLK_PERIC_QCH_SPI0,
	LBLK_PERIC_QCH_SPI1,
	LBLK_PERIC_QCH_USI2,
	LBLK_PERIC_QCH_UART0,
	LBLK_PERIC_QCH_UART1,
	LBLK_PERIC_QCH_HSI2C0,
	LBLK_PERIC_QCH_HSI2C1,
	LBLK_PERIC_QCH_HSI2C2,
	LBLK_PERIC_QCH_HSI2C3,
	LBLK_PERIC_QCH_USI0,
	LBLK_PERIC_QCH_USI1,
	LBLK_PERIC_QCH_GPIO,
	LBLK_PERIC_QCH_UART2,
	LHM_AXI_P_PERI_QCH,
	MCT_QCH,
	OTP_CON_TOP_QCH,
	PERI_CMU_PERI_QCH,
	SECUCON_QCH,
	SYSREG_PERI_QCH,
	WDT_CLUSTER0_QCH,
	WDT_CLUSTER1_QCH,
	end_of_qch,
	num_of_qch = end_of_qch - QCH_TYPE,
};

/*=================Controller Option information================================*/

enum option_id {
	CTRL_OPTION_BLK_APM = OPTION_TYPE,
	CTRL_OPTION_BLK_CMU,
	CTRL_OPTION_BLK_CPUCL0,
	CTRL_OPTION_BLK_CPUCL1,
	CTRL_OPTION_BLK_DISPAUD,
	CTRL_OPTION_BLK_FSYS,
	CTRL_OPTION_BLK_G3D,
	CTRL_OPTION_BLK_IS,
	CTRL_OPTION_BLK_MFCMSCL,
	CTRL_OPTION_BLK_MIF,
	CTRL_OPTION_BLK_MODEM,
	CTRL_OPTION_BLK_PERI,
	end_of_option,
	num_of_option = end_of_option - OPTION_TYPE,
};

#endif