| #include "../cmucal.h" |
| #include "cmucal-node.h" |
| #include "cmucal-sfr.h" |
| |
| /*=================CMUCAL version: S5E7872================================*/ |
| |
| /*====================The section of PLL rate tables===================*/ |
| struct cmucal_pll_table pll_shared0_rate_table[] = { |
| PLL_RATE_MPS(1599000000, 246, 4, 0), |
| PLL_RATE_MPS(1600000000, 800, 13, 0), |
| }; |
| |
| struct cmucal_pll_table pll_shared1_rate_table[] = { |
| PLL_RATE_MPS(1332500000, 205, 4, 0), |
| PLL_RATE_MPS(1332000000, 666, 13, 0), |
| }; |
| |
| struct cmucal_pll_table pll_cpucl0_rate_table[] = { |
| PLL_RATE_MPS(1300000000, 150, 3, 0), |
| PLL_RATE_MPS(1698666748, 196, 3, 0), |
| PLL_RATE_MPS(275166656, 254, 3, 3), |
| PLL_RATE_MPS(477000000, 477, 13, 1), |
| PLL_RATE_MPS(747500000, 230, 4, 1), |
| }; |
| |
| struct cmucal_pll_table pll_cpucl1_rate_table[] = { |
| PLL_RATE_MPS(1005333374, 116, 3, 0), |
| PLL_RATE_MPS(1352000000, 156, 3, 0), |
| PLL_RATE_MPS(1603333374, 185, 3, 0), |
| PLL_RATE_MPS(385000000, 385, 13, 1), |
| PLL_RATE_MPS(600000000, 300, 13, 0), |
| }; |
| |
| struct cmucal_pll_table pll_aud_rate_table[] = { |
| PLL_RATE_MPSK(1179648000, 45, 1, 0, 24319), |
| PLL_RATE_MPSK(1083801600, 42, 1, 0, -20665), |
| }; |
| |
| struct cmucal_pll_table pll_g3d_rate_table[] = { |
| PLL_RATE_MPS(747500000, 115, 4, 0), |
| PLL_RATE_MPS(949999939, 475, 13, 0), |
| PLL_RATE_MPS(1200000000, 600, 13, 0), |
| PLL_RATE_MPS(300000000, 150, 13, 0), |
| PLL_RATE_MPS(550000000, 550, 13, 1), |
| }; |
| |
| struct cmucal_pll_table pll_mem_rate_table[] = { |
| PLL_RATE_MPS(1865500000, 287, 4, 0), |
| PLL_RATE_MPS(667000000, 205, 4, 1), |
| PLL_RATE_MPS(1332500000, 205, 4, 0), |
| }; |
| |
| /*====================The section of PLLs===================*/ |
| unsigned int cmucal_pll_size = 7; |
| |
| struct cmucal_pll cmucal_pll_list[] = { |
| CLK_PLL(PLL_1417X, PLL_SHARED0, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED0_ENABLE, PLL_CON0_PLL_SHARED0_STABLE, PLL_CON0_PLL_SHARED0_DIV_P, PLL_CON0_PLL_SHARED0_DIV_M, PLL_CON0_PLL_SHARED0_DIV_S, EMPTY_CAL_ID, pll_shared0_rate_table, 150, 0), |
| CLK_PLL(PLL_1417X, PLL_SHARED1, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED1_ENABLE, PLL_CON0_PLL_SHARED1_STABLE, PLL_CON0_PLL_SHARED1_DIV_P, PLL_CON0_PLL_SHARED1_DIV_M, PLL_CON0_PLL_SHARED1_DIV_S, EMPTY_CAL_ID, pll_shared1_rate_table, 150, 0), |
| CLK_PLL(PLL_1417X, PLL_CPUCL0, OSCCLK_CPUCL0, PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, PLL_CON0_PLL_CPUCL0_ENABLE, PLL_CON0_PLL_CPUCL0_STABLE, PLL_CON0_PLL_CPUCL0_DIV_P, PLL_CON0_PLL_CPUCL0_DIV_M, PLL_CON0_PLL_CPUCL0_DIV_S, EMPTY_CAL_ID, pll_cpucl0_rate_table, 150, 0), |
| CLK_PLL(PLL_1417X, PLL_CPUCL1, OSCCLK_CPUCL1, PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, PLL_CON0_PLL_CPUCL1_ENABLE, PLL_CON0_PLL_CPUCL1_STABLE, PLL_CON0_PLL_CPUCL1_DIV_P, PLL_CON0_PLL_CPUCL1_DIV_M, PLL_CON0_PLL_CPUCL1_DIV_S, EMPTY_CAL_ID, pll_cpucl1_rate_table, 150, 0), |
| CLK_PLL(PLL_1431X, PLL_AUD, OSCCLK_DISPAUD, PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME, PLL_CON0_PLL_AUD_ENABLE, PLL_CON0_PLL_AUD_STABLE, PLL_CON0_PLL_AUD_DIV_P, PLL_CON0_PLL_AUD_DIV_M, PLL_CON0_PLL_AUD_DIV_S, PLL_CON3_PLL_AUD_DIV_K, pll_aud_rate_table, 150, 3000), |
| CLK_PLL(PLL_1417X, PLL_G3D, OSCCLK_G3D, PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, PLL_CON0_PLL_G3D_ENABLE, PLL_CON0_PLL_G3D_STABLE, PLL_CON0_PLL_G3D_DIV_P, PLL_CON0_PLL_G3D_DIV_M, PLL_CON0_PLL_G3D_DIV_S, EMPTY_CAL_ID, pll_g3d_rate_table, 150, 0), |
| CLK_PLL(PLL_1417X, PLL_MEM, OSCCLK_MIF, PLL_LOCKTIME_PLL_MEM_PLL_LOCK_TIME, PLL_CON0_PLL_MEM_ENABLE, PLL_CON0_PLL_MEM_STABLE, PLL_CON0_PLL_MEM_DIV_P, PLL_CON0_PLL_MEM_DIV_M, PLL_CON0_PLL_MEM_DIV_S, EMPTY_CAL_ID, pll_mem_rate_table, 150, 0), |
| }; |
| |
| /*====================The section of MUXs' parents===================*/ |
| enum clk_id cmucal_mux_clkcmu_mfcmscl_mscl_parents[] = { |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_mfcmscl_mfc_parents[] = { |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_is_vra_parents[] = { |
| PLL_SHARED0, |
| PLL_SHARED1, |
| }; |
| enum clk_id cmucal_mux_clkcmu_is_3aa_parents[] = { |
| PLL_SHARED0, |
| PLL_SHARED1, |
| }; |
| enum clk_id cmucal_mux_clkcmu_is_isp_parents[] = { |
| PLL_SHARED0, |
| PLL_SHARED1, |
| }; |
| enum clk_id cmucal_mux_clkcmu_dispaud_bus_parents[] = { |
| PLL_SHARED0_DIV2, |
| PLL_SHARED1_DIV2, |
| }; |
| enum clk_id cmucal_mux_clkcmu_fsys_bus_parents[] = { |
| PLL_SHARED0_DIV2, |
| PLL_SHARED1_DIV2, |
| }; |
| enum clk_id cmucal_mux_clkcmu_fsys_mmc_embd_parents[] = { |
| PLL_SHARED0_DIV2, |
| PLL_SHARED1_DIV2, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_bus_parents[] = { |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_uart_0_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_uart_1_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_usi2_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_spi_0_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_spi_1_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_fsys_mmc_card_parents[] = { |
| PLL_SHARED0_DIV2, |
| PLL_SHARED1_DIV2, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cis_clk0_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cis_clk1_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cis_clk2_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_usi0_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_usi1_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_cmu_cmuref_parents[] = { |
| OSCCLK_CMU, |
| DIV_CLK_CMU_CMUREF, |
| }; |
| enum clk_id cmucal_mux_clk_cmu_cmuref_parents[] = { |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_apm_bus_parents[] = { |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_mif_switch_parents[] = { |
| PLL_SHARED0, |
| PLL_SHARED1, |
| }; |
| enum clk_id cmucal_mux_clkcmu_mif_bus_parents[] = { |
| PLL_SHARED0_DIV2, |
| PLL_SHARED1_DIV2, |
| }; |
| enum clk_id cmucal_mux_clkcmu_mif_cci_parents[] = { |
| PLL_SHARED0_DIV2, |
| PLL_SHARED0_DIV3, |
| }; |
| enum clk_id cmucal_mux_clkcmu_is_tpu_parents[] = { |
| PLL_SHARED0, |
| PLL_SHARED1, |
| }; |
| enum clk_id cmucal_mux_clkcmu_fsys_mmc_sdio_parents[] = { |
| PLL_SHARED0_DIV2, |
| PLL_SHARED1_DIV2, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_uart_2_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clk_cpucl0_pll_parents[] = { |
| PLL_CPUCL0, |
| MUX_CLKCMU_CPUCL0_SWITCH_USER, |
| }; |
| enum clk_id cmucal_mux_clk_cpucl1_pll_parents[] = { |
| PLL_CPUCL1, |
| MUX_CLKCMU_CPUCL1_SWITCH_USER, |
| }; |
| enum clk_id cmucal_mux_clk_aud_cpu_parents[] = { |
| DIV_CLK_AUD_PLL, |
| MUX_CLKCMU_AUD_CPU_USER, |
| }; |
| enum clk_id cmucal_mux_clk_aud_uaif0_parents[] = { |
| DIV_CLK_AUD_UAIF0, |
| IOCLK_AUDIOCDCLK0, |
| }; |
| enum clk_id cmucal_mux_clk_aud_uaif2_parents[] = { |
| DIV_CLK_AUD_UAIF2, |
| IOCLK_AUDIOCDCLK2, |
| }; |
| enum clk_id cmucal_mux_clk_aud_uaif3_parents[] = { |
| DIV_CLK_AUD_UAIF3, |
| IOCLK_AUDIOCDCLK3, |
| }; |
| enum clk_id cmucal_mux_clk_aud_cpu_hch_parents[] = { |
| MUX_CLK_AUD_CPU, |
| OSCCLK_DISPAUD, |
| }; |
| enum clk_id cmucal_mux_clk_g3d_busd_parents[] = { |
| PLL_G3D, |
| MUX_CLKCMU_G3D_SWITCH_USER, |
| }; |
| enum clk_id cmucal_mux_clk_mif_ddrphy_clk2x_parents[] = { |
| PLL_MEM, |
| MUX_CLKCMU_MIF_SWITCH_USER, |
| }; |
| enum clk_id cmucal_mux_mif_cmuref_parents[] = { |
| OSCCLK_MIF, |
| DIV_CLK_MIF_BUSP, |
| }; |
| enum clk_id cmucal_mux_clk_mif_bus_parents[] = { |
| PLL_MEM_DIV2, |
| MUX_CLKCMU_MIF_BUS_USER, |
| }; |
| enum clk_id cmucal_mux_clk_mif_gic_parents[] = { |
| DIV_CLK_MIF_BUSP, |
| OSCCLK_MIF, |
| }; |
| enum clk_id cmucal_mux_clk_mif_cci_parents[] = { |
| PLL_MEM_DIV2, |
| MUX_CLK_MIF_CCI_USER, |
| }; |
| enum clk_id cmucal_mux_clkcmu_apm_bus_user_parents[] = { |
| OSCCLK_APM, |
| CLKCMU_APM_BUS, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cpucl0_switch_user_parents[] = { |
| OSCCLK_CPUCL0, |
| CLKCMU_CPUCL0_SWITCH, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cpucl0_secjtag_user_parents[] = { |
| OSCCLK_CPUCL0, |
| CLKCMU_CPUCL0_SECJTAG, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cpucl1_switch_user_parents[] = { |
| OSCCLK_CPUCL1, |
| CLKCMU_CPUCL1_SWITCH, |
| }; |
| enum clk_id cmucal_mux_clkcmu_aud_cpu_user_parents[] = { |
| OSCCLK_DISPAUD, |
| CLKCMU_DISPAUD_CPU, |
| }; |
| enum clk_id cmucal_mux_clkcmu_dispaud_bus_user_parents[] = { |
| OSCCLK_DISPAUD, |
| CLKCMU_DISPAUD_BUS, |
| }; |
| enum clk_id cmucal_mux_clkcmu_fsys_bus_user_parents[] = { |
| OSCCLK_FSYS, |
| CLKCMU_FSYS_BUS, |
| }; |
| enum clk_id cmucal_mux_clkcmu_fsys_mmc_card_user_parents[] = { |
| OSCCLK_FSYS, |
| CLKCMU_FSYS_MMC_CARD, |
| }; |
| enum clk_id cmucal_mux_clkcmu_fsys_mmc_embd_user_parents[] = { |
| OSCCLK_FSYS, |
| CLKCMU_FSYS_MMC_EMBD, |
| }; |
| enum clk_id cmucal_mux_clkcmu_fsys_mmc_sdio_user_parents[] = { |
| OSCCLK_FSYS, |
| CLKCMU_FSYS_MMC_SDIO, |
| }; |
| enum clk_id cmucal_mux_clkcmu_g3d_switch_user_parents[] = { |
| OSCCLK_G3D, |
| CLKCMU_G3D_SWITCH, |
| }; |
| enum clk_id cmucal_mux_clkcmu_is_vra_user_parents[] = { |
| OSCCLK_IS, |
| CLKCMU_IS_VRA, |
| }; |
| enum clk_id cmucal_mux_clkcmu_is_isp_user_parents[] = { |
| OSCCLK_IS, |
| CLKCMU_IS_ISP, |
| }; |
| enum clk_id cmucal_mux_clkcmu_is_3aa_user_parents[] = { |
| OSCCLK_IS, |
| CLKCMU_IS_3AA, |
| }; |
| enum clk_id cmucal_mux_clkcmu_is_tpu_user_parents[] = { |
| OSCCLK_IS, |
| CLKCMU_IS_TPU, |
| }; |
| enum clk_id cmucal_mux_clkcmu_mfcmscl_mscl_user_parents[] = { |
| OSCCLK_MFCMSCL, |
| CLKCMU_MFCMSCL_MSCL, |
| }; |
| enum clk_id cmucal_mux_clkcmu_mfcmscl_mfc_user_parents[] = { |
| OSCCLK_MFCMSCL, |
| CLKCMU_MFCMSCL_MFC, |
| }; |
| enum clk_id cmucal_mux_clkcmu_mif_switch_user_parents[] = { |
| OSCCLK_MIF, |
| CLKCMU_MIF_SWITCH, |
| }; |
| enum clk_id cmucal_mux_clkcmu_mif_bus_user_parents[] = { |
| OSCCLK_MIF, |
| CLKCMU_MIF_BUS, |
| }; |
| enum clk_id cmucal_mux_clk_mif_cci_user_parents[] = { |
| OSCCLK_MIF, |
| CLKCMU_MIF_CCI, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_bus_user_parents[] = { |
| OSCCLK_PERI, |
| CLKCMU_PERI_BUS, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_uart_0_user_parents[] = { |
| OSCCLK_PERI, |
| CLKCMU_PERI_UART_0, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_uart_1_user_parents[] = { |
| OSCCLK_PERI, |
| CLKCMU_PERI_UART_1, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_usi0_user_parents[] = { |
| OSCCLK_PERI, |
| CLKCMU_PERI_USI0, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_usi1_user_parents[] = { |
| OSCCLK_PERI, |
| CLKCMU_PERI_USI1, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_usi2_user_parents[] = { |
| OSCCLK_PERI, |
| CLKCMU_PERI_USI2, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_spi0_user_parents[] = { |
| OSCCLK_PERI, |
| CLKCMU_PERI_SPI_0, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_spi1_user_parents[] = { |
| OSCCLK_PERI, |
| CLKCMU_PERI_SPI_1, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_uart_2_user_parents[] = { |
| OSCCLK_PERI, |
| CLKCMU_PERI_UART_2, |
| }; |
| |
| |
| /*====================The section of MUXs===================*/ |
| unsigned int cmucal_mux_size = 93; |
| |
| |
| struct cmucal_mux cmucal_mux_list[] = { |
| CLK_MUX(MUX_CLKCMU_MFCMSCL_MSCL, cmucal_mux_clkcmu_mfcmscl_mscl_parents, CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MSCL_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MSCL_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MSCL_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_MFCMSCL_MFC, cmucal_mux_clkcmu_mfcmscl_mfc_parents, CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_IS_VRA, cmucal_mux_clkcmu_is_vra_parents, CLK_CON_MUX_MUX_CLKCMU_IS_VRA_SELECT, CLK_CON_MUX_MUX_CLKCMU_IS_VRA_BUSY, CLK_CON_MUX_MUX_CLKCMU_IS_VRA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_IS_3AA, cmucal_mux_clkcmu_is_3aa_parents, CLK_CON_MUX_MUX_CLKCMU_IS_3AA_SELECT, CLK_CON_MUX_MUX_CLKCMU_IS_3AA_BUSY, CLK_CON_MUX_MUX_CLKCMU_IS_3AA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_IS_ISP, cmucal_mux_clkcmu_is_isp_parents, CLK_CON_MUX_MUX_CLKCMU_IS_ISP_SELECT, CLK_CON_MUX_MUX_CLKCMU_IS_ISP_BUSY, CLK_CON_MUX_MUX_CLKCMU_IS_ISP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_DISPAUD_BUS, cmucal_mux_clkcmu_dispaud_bus_parents, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_FSYS_BUS, cmucal_mux_clkcmu_fsys_bus_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_FSYS_MMC_EMBD, cmucal_mux_clkcmu_fsys_mmc_embd_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_BUS, cmucal_mux_clkcmu_peri_bus_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_UART_0, cmucal_mux_clkcmu_peri_uart_0_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_0_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_0_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_UART_1, cmucal_mux_clkcmu_peri_uart_1_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_1_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_1_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_USI2, cmucal_mux_clkcmu_peri_usi2_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_USI2_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_USI2_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_USI2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_SPI_0, cmucal_mux_clkcmu_peri_spi_0_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_0_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_0_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_SPI_1, cmucal_mux_clkcmu_peri_spi_1_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_1_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_1_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_SPI_1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_FSYS_MMC_CARD, cmucal_mux_clkcmu_fsys_mmc_card_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CIS_CLK0, cmucal_mux_clkcmu_cis_clk0_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CIS_CLK1, cmucal_mux_clkcmu_cis_clk1_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CIS_CLK2, cmucal_mux_clkcmu_cis_clk2_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_USI0, cmucal_mux_clkcmu_peri_usi0_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_USI0_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_USI0_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_USI0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_USI1, cmucal_mux_clkcmu_peri_usi1_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_USI1_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_USI1_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_USI1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CMU_CMUREF, cmucal_mux_cmu_cmuref_parents, CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_CMU_CMUREF, cmucal_mux_clk_cmu_cmuref_parents, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_APM_BUS, cmucal_mux_clkcmu_apm_bus_parents, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_MIF_SWITCH, cmucal_mux_clkcmu_mif_switch_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_MIF_BUS, cmucal_mux_clkcmu_mif_bus_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_MIF_CCI, cmucal_mux_clkcmu_mif_cci_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_CCI_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_CCI_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_CCI_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_IS_TPU, cmucal_mux_clkcmu_is_tpu_parents, CLK_CON_MUX_MUX_CLKCMU_IS_TPU_SELECT, CLK_CON_MUX_MUX_CLKCMU_IS_TPU_BUSY, CLK_CON_MUX_MUX_CLKCMU_IS_TPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_FSYS_MMC_SDIO, cmucal_mux_clkcmu_fsys_mmc_sdio_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_UART_2, cmucal_mux_clkcmu_peri_uart_2_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_2_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_2_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_CPUCL0_PLL, cmucal_mux_clk_cpucl0_pll_parents, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_CPUCL1_PLL, cmucal_mux_clk_cpucl1_pll_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_AUD_CPU, cmucal_mux_clk_aud_cpu_parents, CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT, CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY, CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_AUD_UAIF0, cmucal_mux_clk_aud_uaif0_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_AUD_UAIF2, cmucal_mux_clk_aud_uaif2_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_AUD_UAIF3, cmucal_mux_clk_aud_uaif3_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_AUD_CPU_HCH, cmucal_mux_clk_aud_cpu_hch_parents, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_SELECT, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_BUSY, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_G3D_BUSD, cmucal_mux_clk_g3d_busd_parents, CLK_CON_MUX_MUX_CLK_G3D_BUSD_SELECT, CLK_CON_MUX_MUX_CLK_G3D_BUSD_BUSY, CLK_CON_MUX_MUX_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_MIF_DDRPHY_CLK2X, cmucal_mux_clk_mif_ddrphy_clk2x_parents, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_SELECT, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_BUSY, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_MIF_CMUREF, cmucal_mux_mif_cmuref_parents, CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_MIF_BUS, cmucal_mux_clk_mif_bus_parents, CLK_CON_MUX_MUX_CLK_MIF_BUS_SELECT, CLK_CON_MUX_MUX_CLK_MIF_BUS_BUSY, CLK_CON_MUX_MUX_CLK_MIF_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_MIF_GIC, cmucal_mux_clk_mif_gic_parents, CLK_CON_MUX_MUX_CLK_MIF_GIC_SELECT, CLK_CON_MUX_MUX_CLK_MIF_GIC_BUSY, CLK_CON_MUX_MUX_CLK_MIF_GIC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_MIF_CCI, cmucal_mux_clk_mif_cci_parents, CLK_CON_MUX_MUX_CLK_MIF_CCI_SELECT, CLK_CON_MUX_MUX_CLK_MIF_CCI_BUSY, CLK_CON_MUX_MUX_CLK_MIF_CCI_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(APM_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_APM_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_APM_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_APM_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(APM_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_APM_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_APM_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_APM_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(CMU_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_CMU_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CMU_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CMU_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(CMU_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_CMU_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CMU_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CMU_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(CPUCL0_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(CPUCL0_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(CPUCL1_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(CPUCL1_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(DISPAUD_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(DISPAUD_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_DISPAUD_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(FSYS_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_FSYS_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_FSYS_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_FSYS_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(FSYS_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_FSYS_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_FSYS_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_FSYS_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(G3D_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_G3D_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_G3D_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_G3D_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(G3D_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_G3D_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_G3D_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_G3D_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(IS_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_IS_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_IS_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_IS_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(IS_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_IS_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_IS_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_IS_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MFCMSCL_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MFCMSCL_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_MFCMSCL_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MIF_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_MIF_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_MIF_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_MIF_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MIF_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_MIF_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_MIF_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_MIF_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(PERI_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_PERI_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_PERI_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_PERI_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(PERI_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_PERI_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_PERI_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_PERI_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_APM_BUS_USER, cmucal_mux_clkcmu_apm_bus_user_parents, PLL_CON0_MUX_CLKCMU_APM_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_APM_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_APM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH_USER, cmucal_mux_clkcmu_cpucl0_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CPUCL0_SECJTAG_USER, cmucal_mux_clkcmu_cpucl0_secjtag_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_SECJTAG_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_SECJTAG_USER_BUSY, PLL_CON2_MUX_CLKCMU_CPUCL0_SECJTAG_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH_USER, cmucal_mux_clkcmu_cpucl1_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_AUD_CPU_USER, cmucal_mux_clkcmu_aud_cpu_user_parents, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_BUSY, PLL_CON2_MUX_CLKCMU_AUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_DISPAUD_BUS_USER, cmucal_mux_clkcmu_dispaud_bus_user_parents, PLL_CON0_MUX_CLKCMU_DISPAUD_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DISPAUD_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_DISPAUD_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_FSYS_BUS_USER, cmucal_mux_clkcmu_fsys_bus_user_parents, PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_FSYS_MMC_CARD_USER, cmucal_mux_clkcmu_fsys_mmc_card_user_parents, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_FSYS_MMC_EMBD_USER, cmucal_mux_clkcmu_fsys_mmc_embd_user_parents, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS_MMC_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_FSYS_MMC_SDIO_USER, cmucal_mux_clkcmu_fsys_mmc_sdio_user_parents, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS_MMC_SDIO_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_G3D_SWITCH_USER, cmucal_mux_clkcmu_g3d_switch_user_parents, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY, PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_IS_VRA_USER, cmucal_mux_clkcmu_is_vra_user_parents, PLL_CON0_MUX_CLKCMU_IS_VRA_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_IS_VRA_USER_BUSY, PLL_CON2_MUX_CLKCMU_IS_VRA_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_IS_ISP_USER, cmucal_mux_clkcmu_is_isp_user_parents, PLL_CON0_MUX_CLKCMU_IS_ISP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_IS_ISP_USER_BUSY, PLL_CON2_MUX_CLKCMU_IS_ISP_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_IS_3AA_USER, cmucal_mux_clkcmu_is_3aa_user_parents, PLL_CON0_MUX_CLKCMU_IS_3AA_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_IS_3AA_USER_BUSY, PLL_CON2_MUX_CLKCMU_IS_3AA_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_IS_TPU_USER, cmucal_mux_clkcmu_is_tpu_user_parents, PLL_CON0_MUX_CLKCMU_IS_TPU_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_IS_TPU_USER_BUSY, PLL_CON2_MUX_CLKCMU_IS_TPU_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_MFCMSCL_MSCL_USER, cmucal_mux_clkcmu_mfcmscl_mscl_user_parents, PLL_CON0_MUX_CLKCMU_MFCMSCL_MSCL_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFCMSCL_MSCL_USER_BUSY, PLL_CON2_MUX_CLKCMU_MFCMSCL_MSCL_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_MFCMSCL_MFC_USER, cmucal_mux_clkcmu_mfcmscl_mfc_user_parents, PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER_BUSY, PLL_CON2_MUX_CLKCMU_MFCMSCL_MFC_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_MIF_SWITCH_USER, cmucal_mux_clkcmu_mif_switch_user_parents, PLL_CON0_MUX_CLKCMU_MIF_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MIF_SWITCH_USER_BUSY, PLL_CON2_MUX_CLKCMU_MIF_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_MIF_BUS_USER, cmucal_mux_clkcmu_mif_bus_user_parents, PLL_CON0_MUX_CLKCMU_MIF_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MIF_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_MIF_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_MIF_CCI_USER, cmucal_mux_clk_mif_cci_user_parents, PLL_CON0_MUX_CLK_MIF_CCI_USER_MUX_SEL, PLL_CON0_MUX_CLK_MIF_CCI_USER_BUSY, PLL_CON2_MUX_CLK_MIF_CCI_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_BUS_USER, cmucal_mux_clkcmu_peri_bus_user_parents, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_UART_0_USER, cmucal_mux_clkcmu_peri_uart_0_user_parents, PLL_CON0_MUX_CLKCMU_PERI_UART_0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_UART_0_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_UART_0_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_UART_1_USER, cmucal_mux_clkcmu_peri_uart_1_user_parents, PLL_CON0_MUX_CLKCMU_PERI_UART_1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_UART_1_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_UART_1_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_USI0_USER, cmucal_mux_clkcmu_peri_usi0_user_parents, PLL_CON0_MUX_CLKCMU_PERI_USI0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI0_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_USI0_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_USI1_USER, cmucal_mux_clkcmu_peri_usi1_user_parents, PLL_CON0_MUX_CLKCMU_PERI_USI1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI1_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_USI1_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_USI2_USER, cmucal_mux_clkcmu_peri_usi2_user_parents, PLL_CON0_MUX_CLKCMU_PERI_USI2_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI2_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_USI2_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_SPI0_USER, cmucal_mux_clkcmu_peri_spi0_user_parents, PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_SPI0_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_SPI1_USER, cmucal_mux_clkcmu_peri_spi1_user_parents, PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_SPI1_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_UART_2_USER, cmucal_mux_clkcmu_peri_uart_2_user_parents, PLL_CON0_MUX_CLKCMU_PERI_UART_2_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_UART_2_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_UART_2_USER_ENABLE_AUTOMATIC_CLKGATING), |
| }; |
| |
| /*====================The section of DIVs===================*/ |
| unsigned int cmucal_div_size = 72; |
| |
| |
| struct cmucal_div cmucal_div_list[] = { |
| CLK_DIV(DIV_CLK_APM_I2C, OSCCLK_APM, CLK_CON_DIV_DIV_CLK_APM_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_APM_I2C_BUSY, CLK_CON_DIV_DIV_CLK_APM_I2C_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CPUCL1_SWITCH, GATE_CLKCMU_CPUCL1_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_G3D_SWITCH, GATE_CLKCMU_G3D_SWITCH, CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_IS_3AA, GATE_CLKCMU_IS_3AA, CLK_CON_DIV_CLKCMU_IS_3AA_DIVRATIO, CLK_CON_DIV_CLKCMU_IS_3AA_BUSY, CLK_CON_DIV_CLKCMU_IS_3AA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_IS_VRA, GATE_CLKCMU_IS_VRA, CLK_CON_DIV_CLKCMU_IS_VRA_DIVRATIO, CLK_CON_DIV_CLKCMU_IS_VRA_BUSY, CLK_CON_DIV_CLKCMU_IS_VRA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_DISPAUD_BUS, GATE_CLKCMU_DISPAUD_BUS, CLK_CON_DIV_CLKCMU_DISPAUD_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_DISPAUD_BUS_BUSY, CLK_CON_DIV_CLKCMU_DISPAUD_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_FSYS_BUS, GATE_CLKCMU_FSYS_BUS, CLK_CON_DIV_CLKCMU_FSYS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS_BUS_BUSY, CLK_CON_DIV_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CPUCL0_SWITCH, GATE_CLKCMU_CPUCL0_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_MFCMSCL_MSCL, GATE_CLKCMU_MFCMSCL_MSCL, CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL_DIVRATIO, CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL_BUSY, CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_MFCMSCL_MFC, GATE_CLKCMU_MFCMSCL_MFC, CLK_CON_DIV_CLKCMU_MFCMSCL_MFC_DIVRATIO, CLK_CON_DIV_CLKCMU_MFCMSCL_MFC_BUSY, CLK_CON_DIV_CLKCMU_MFCMSCL_MFC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_IS_ISP, GATE_CLKCMU_IS_ISP, CLK_CON_DIV_CLKCMU_IS_ISP_DIVRATIO, CLK_CON_DIV_CLKCMU_IS_ISP_BUSY, CLK_CON_DIV_CLKCMU_IS_ISP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(AP2CP_SHARED0_PLL_CLK, GATE_CLKCMU_MODEM_SHARED0, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_DIVRATIO, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_BUSY, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_PERI_BUS, GATE_CLKCMU_PERI_BUS, CLK_CON_DIV_CLKCMU_PERI_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_PERI_UART_0, GATE_CLKCMU_PERI_UART_0, CLK_CON_DIV_CLKCMU_PERI_UART_0_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_UART_0_BUSY, CLK_CON_DIV_CLKCMU_PERI_UART_0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_PERI_UART_1, GATE_CLKCMUC_PERI_UART_1, CLK_CON_DIV_CLKCMU_PERI_UART_1_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_UART_1_BUSY, CLK_CON_DIV_CLKCMU_PERI_UART_1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_PERI_USI2, GATE_CLKCMU_PERI_USI2, CLK_CON_DIV_CLKCMU_PERI_USI2_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_USI2_BUSY, CLK_CON_DIV_CLKCMU_PERI_USI2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_PERI_SPI_0, GATE_CLKCMU_PERI_SPI_0, CLK_CON_DIV_CLKCMU_PERI_SPI_0_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_SPI_0_BUSY, CLK_CON_DIV_CLKCMU_PERI_SPI_0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_PERI_SPI_1, GATE_CLKCMU_PERI_SPI_1, CLK_CON_DIV_CLKCMU_PERI_SPI_1_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_SPI_1_BUSY, CLK_CON_DIV_CLKCMU_PERI_SPI_1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_APM_BUS, GATE_CLKCMU_APM_BUS, CLK_CON_DIV_CLKCMU_APM_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_APM_BUS_BUSY, CLK_CON_DIV_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_FSYS_MMC_CARD, GATE_CLKCMU_FSYS_MMC_CARD, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_BUSY, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CIS_CLK0, GATE_CLKCMU_CIS_CLK0, CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CIS_CLK1, GATE_CLKCMU_CIS_CLK1, CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CIS_CLK2, GATE_CLKCMU_CIS_CLK2, CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_FSYS_MMC_EMBD, GATE_CLKCMU_FSYS_MMC_EMBD, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_BUSY, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_PERI_USI0, GATE_CLKCMU_PERI_USI0, CLK_CON_DIV_CLKCMU_PERI_USI0_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_USI0_BUSY, CLK_CON_DIV_CLKCMU_PERI_USI0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_PERI_USI1, GATE_CLKCMU_PERI_USI1, CLK_CON_DIV_CLKCMU_PERI_USI1_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_USI1_BUSY, CLK_CON_DIV_CLKCMU_PERI_USI1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(AP2CP_SHARED1_PLL_CLK, GATE_CLKCMU_MODEM_SHARED1, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_DIVRATIO, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_BUSY, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CMU_CMUREF, MUX_CLK_CMU_CMUREF, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_DISPAUD_CPU, GATE_CLKCMU_DISPAUD_VCLK, CLK_CON_DIV_CLKCMU_DISPAUD_CPU_DIVRATIO, CLK_CON_DIV_CLKCMU_DISPAUD_CPU_BUSY, CLK_CON_DIV_CLKCMU_DISPAUD_CPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_MIF_CCI, GATE_CLKCMU_MIF_CCI, CLK_CON_DIV_CLKCMU_MIF_CCI_DIVRATIO, CLK_CON_DIV_CLKCMU_MIF_CCI_BUSY, CLK_CON_DIV_CLKCMU_MIF_CCI_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_IS_TPU, GATE_CLKCMU_IS_TPU, CLK_CON_DIV_CLKCMU_IS_TPU_DIVRATIO, CLK_CON_DIV_CLKCMU_IS_TPU_BUSY, CLK_CON_DIV_CLKCMU_IS_TPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_MIF_SWITCH, GATE_CLKCMU_MIF_SWITCH, CLK_CON_DIV_CLKCMU_MIF_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_MIF_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_FSYS_MMC_SDIO, GATE_CLKCMU_FSYS_MMC_SDIO, CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO_BUSY, CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_MIF_BUS, GATE_CLKCMU_MIF_BUS, CLK_CON_DIV_CLKCMU_MIF_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_MIF_BUS_BUSY, CLK_CON_DIV_CLKCMU_MIF_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_PERI_UART_2, GATE_CLKCMU_PERI_UART_2, CLK_CON_DIV_CLKCMU_PERI_UART_2_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_UART_2_BUSY, CLK_CON_DIV_CLKCMU_PERI_UART_2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(PLL_SHARED0_DIV3, PLL_SHARED0, CLK_CON_DIV_PLL_SHARED0_DIV3_DIVRATIO, CLK_CON_DIV_PLL_SHARED0_DIV3_BUSY, CLK_CON_DIV_PLL_SHARED0_DIV3_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CPUCL0_SECJTAG, GATE_CLKCMU_CPUCL0_SECJTAG, CLK_CON_DIV_CLKCMU_CPUCL0_SECJTAG_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_SECJTAG_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_SECJTAG_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(PLL_SHARED0_DIV2, PLL_SHARED0, CLK_CON_DIV_PLL_SHARED0_DIV2_DIVRATIO, CLK_CON_DIV_PLL_SHARED0_DIV2_BUSY, CLK_CON_DIV_PLL_SHARED0_DIV2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(PLL_SHARED0_DIV4, PLL_SHARED0_DIV2, CLK_CON_DIV_PLL_SHARED0_DIV4_DIVRATIO, CLK_CON_DIV_PLL_SHARED0_DIV4_BUSY, CLK_CON_DIV_PLL_SHARED0_DIV4_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(PLL_SHARED1_DIV2, PLL_SHARED1, CLK_CON_DIV_PLL_SHARED1_DIV2_DIVRATIO, CLK_CON_DIV_PLL_SHARED1_DIV2_BUSY, CLK_CON_DIV_PLL_SHARED1_DIV2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(PLL_SHARED1_DIV4, PLL_SHARED1_DIV2, CLK_CON_DIV_PLL_SHARED1_DIV4_DIVRATIO, CLK_CON_DIV_PLL_SHARED1_DIV4_BUSY, CLK_CON_DIV_PLL_SHARED1_DIV4_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL0_PCLK, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL0_CMUREF, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL0_ACLK, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL0_ATCLK, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_ATCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_ATCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_ATCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL0_CNTCLK, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_CNTCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_CNTCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CNTCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL0_PCLKDBG, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL0_CPU, MUX_CLK_CPUCL0_PLL, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL1_PCLK, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL1_CMUREF, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL1_ACLK, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL1_ATCLK, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_ATCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_ATCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_ATCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL1_PCLKDBG, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL1_CPU, MUX_CLK_CPUCL1_PLL, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL1_CNTCLK, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_CNTCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_CNTCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CNTCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_BUS, PLL_AUD, CLK_CON_DIV_DIV_CLK_AUD_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_BUS_BUSY, CLK_CON_DIV_DIV_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_PLL, PLL_AUD, CLK_CON_DIV_DIV_CLK_AUD_PLL_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_PLL_BUSY, CLK_CON_DIV_DIV_CLK_AUD_PLL_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_CPU_PCLKDBG, MUX_CLK_AUD_CPU_HCH, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_CPU_ACLK, MUX_CLK_AUD_CPU_HCH, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_UAIF0, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_AUDIF, PLL_AUD, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_UAIF2, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_UAIF3, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_FM, OSCCLK_DISPAUD, CLK_CON_DIV_DIV_CLK_AUD_FM_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_FM_BUSY, CLK_CON_DIV_DIV_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_DISPAUD_BUSP, MUX_CLKCMU_DISPAUD_BUS_USER, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_G3D_BUSP, MUX_CLK_G3D_BUSD, CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_IS_APB, MUX_CLKCMU_IS_VRA_USER, CLK_CON_DIV_DIV_CLK_IS_APB_DIVRATIO, CLK_CON_DIV_DIV_CLK_IS_APB_BUSY, CLK_CON_DIV_DIV_CLK_IS_APB_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_IS_3AA_HALF, MUX_CLKCMU_IS_3AA_USER, CLK_CON_DIV_DIV_CLK_IS_3AA_HALF_DIVRATIO, CLK_CON_DIV_DIV_CLK_IS_3AA_HALF_BUSY, CLK_CON_DIV_DIV_CLK_IS_3AA_HALF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_MFCMSCL_APB, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_DIV_DIV_CLK_MFCMSCL_APB_DIVRATIO, CLK_CON_DIV_DIV_CLK_MFCMSCL_APB_BUSY, CLK_CON_DIV_DIV_CLK_MFCMSCL_APB_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_MIF_BUS, MUX_CLK_MIF_BUS, CLK_CON_DIV_DIV_CLK_MIF_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_MIF_BUS_BUSY, CLK_CON_DIV_DIV_CLK_MIF_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_MIF_BUSP, DIV_CLK_MIF_BUS, CLK_CON_DIV_DIV_CLK_MIF_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MIF_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_MIF_CCI, MUX_CLK_MIF_CCI, CLK_CON_DIV_DIV_CLK_MIF_CCI_DIVRATIO, CLK_CON_DIV_DIV_CLK_MIF_CCI_BUSY, CLK_CON_DIV_DIV_CLK_MIF_CCI_ENABLE_AUTOMATIC_CLKGATING), |
| }; |
| |
| /*====================The section of GATEs===================*/ |
| unsigned int cmucal_gate_size = 382; |
| |
| |
| struct cmucal_gate cmucal_gate_list[] = { |
| CLK_GATE(CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_IntMEM, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_INTMEM_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_INTMEM_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_INTMEM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_RSTnSYNC_CLK_APM_BUS_IPCLKPORT_CLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_RSTnSYNC_CLK_APM_BUS_NORET_IPCLKPORT_CLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_NORET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_NORET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_NORET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_IP_BATCHER_AP_IPCLKPORT_i_pclk, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_AP_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_AP_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_AP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_IP_BATCHER_CP_IPCLKPORT_i_pclk, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_CP_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_CP_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_IP_BATCHER_CP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MP_APBSEMA_HWACG_2CH_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_MP_APBSEMA_HWACG_2CH_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MP_APBSEMA_HWACG_2CH_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MP_APBSEMA_HWACG_2CH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_SPEEDY_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_I2C_APM_IPCLKPORT_PCLK, DIV_CLK_APM_I2C, CLK_CON_GAT_GOUT_BLK_APM_UID_I2C_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_I2C_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_I2C_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKM, DIV_CLK_APM_I2C, CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKS, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_ASYNCAPB_APM_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_MFCMSCL_MSCL, MUX_CLKCMU_MFCMSCL_MSCL, CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MSCL_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MSCL_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MSCL_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_MFCMSCL_MFC, MUX_CLKCMU_MFCMSCL_MFC, CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CPUCL0_SWITCH, PLL_SHARED0, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CPUCL1_SWITCH, PLL_SHARED0_DIV2, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_G3D_SWITCH, PLL_SHARED0_DIV2, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_IS_3AA, MUX_CLKCMU_IS_3AA, CLK_CON_GAT_GATE_CLKCMU_IS_3AA_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_IS_3AA_MANUAL, CLK_CON_GAT_GATE_CLKCMU_IS_3AA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_IS_VRA, MUX_CLKCMU_IS_VRA, CLK_CON_GAT_GATE_CLKCMU_IS_VRA_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_IS_VRA_MANUAL, CLK_CON_GAT_GATE_CLKCMU_IS_VRA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_IS_ISP, MUX_CLKCMU_IS_ISP, CLK_CON_GAT_GATE_CLKCMU_IS_ISP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_IS_ISP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_IS_ISP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_DISPAUD_BUS, MUX_CLKCMU_DISPAUD_BUS, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_FSYS_MMC_EMBD, MUX_CLKCMU_FSYS_MMC_EMBD, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_FSYS_BUS, MUX_CLKCMU_FSYS_BUS, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_MODEM_SHARED0, PLL_SHARED0_DIV2, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_PERI_BUS, MUX_CLKCMU_PERI_BUS, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_PERI_UART_0, MUX_CLKCMU_PERI_UART_0, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMUC_PERI_UART_1, MUX_CLKCMU_PERI_UART_1, CLK_CON_GAT_GATE_CLKCMUC_PERI_UART_1_CG_VAL, CLK_CON_GAT_GATE_CLKCMUC_PERI_UART_1_MANUAL, CLK_CON_GAT_GATE_CLKCMUC_PERI_UART_1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_PERI_USI2, MUX_CLKCMU_PERI_USI2, CLK_CON_GAT_GATE_CLKCMU_PERI_USI2_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_USI2_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_USI2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_PERI_SPI_0, MUX_CLKCMU_PERI_SPI_0, CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_PERI_SPI_1, MUX_CLKCMU_PERI_SPI_1, CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_SPI_1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_APM_BUS, MUX_CLKCMU_APM_BUS, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_FSYS_MMC_CARD, MUX_CLKCMU_FSYS_MMC_CARD, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CIS_CLK0, MUX_CLKCMU_CIS_CLK0, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CIS_CLK1, MUX_CLKCMU_CIS_CLK1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CIS_CLK2, MUX_CLKCMU_CIS_CLK2, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_PERI_USI0, MUX_CLKCMU_PERI_USI0, CLK_CON_GAT_GATE_CLKCMU_PERI_USI0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_USI0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_USI0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_PERI_USI1, MUX_CLKCMU_PERI_USI1, CLK_CON_GAT_GATE_CLKCMU_PERI_USI1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_USI1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_USI1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_MODEM_SHARED1, PLL_SHARED1_DIV2, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_DISPAUD_VCLK, PLL_SHARED0_DIV2, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_VCLK_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_VCLK_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_VCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_MIF_CCI, MUX_CLKCMU_MIF_CCI, CLK_CON_GAT_GATE_CLKCMU_MIF_CCI_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MIF_CCI_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MIF_CCI_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_IS_TPU, MUX_CLKCMU_IS_TPU, CLK_CON_GAT_GATE_CLKCMU_IS_TPU_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_IS_TPU_MANUAL, CLK_CON_GAT_GATE_CLKCMU_IS_TPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_MIF_SWITCH, MUX_CLKCMU_MIF_SWITCH, CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_FSYS_MMC_SDIO, MUX_CLKCMU_FSYS_MMC_SDIO, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_MIF_BUS, MUX_CLKCMU_MIF_BUS, CLK_CON_GAT_GATE_CLKCMU_MIF_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MIF_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MIF_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_PERI_UART_2, MUX_CLKCMU_PERI_UART_2, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_2_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_2_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CPUCL0_SECJTAG, PLL_SHARED0_DIV2, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SECJTAG_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SECJTAG_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SECJTAG_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_ADM_APB_P_CSSYS_DBG_IPCLKPORT_PCLKM, DIV_CLK_CPUCL0_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_P_CSSYS_DBG_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_P_CSSYS_DBG_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_P_CSSYS_DBG_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG, DIV_CLK_CPUCL0_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_LHS_AXI_T_CSSYS_DBG_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_T_CSSYS_DBG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_T_CSSYS_DBG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_T_CSSYS_DBG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_CPUCL0_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_DBG_IPCLKPORT_PCLKS, DIV_CLK_CPUCL0_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_DBG_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_DBG_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_DBG_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM, DIV_CLK_CPUCL0_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKS, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_ACLK_IPCLKPORT_CLK, DIV_CLK_CPUCL0_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK, DIV_CLK_CPUCL0_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLK, DIV_CLK_CPUCL0_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL_SECJTAG_IPCLKPORT_CLK, MUX_CLKCMU_CPUCL0_SECJTAG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL_SECJTAG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL_SECJTAG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL_SECJTAG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKM, MUX_CLKCMU_CPUCL0_SECJTAG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKS, DIV_CLK_CPUCL0_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_SECJTAG_CPUCL0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_i_clk, MUX_CLKCMU_CPUCL0_SECJTAG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_RSTnSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK, DIV_CLK_CPUCL1_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_RSTnSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK, DIV_CLK_CPUCL1_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_RSTnSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_CPUCL1_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_ADM_APB_G_CPUCL1_IPCLKPORT_PCLKM, DIV_CLK_CPUCL1_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CPUCL1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CPUCL1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CPUCL1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM, DIV_CLK_CPUCL1_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKS, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK, DIV_CLK_CPUCL1_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0, MUX_CLK_AUD_UAIF0, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3, MUX_CLK_AUD_UAIF3, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7, MUX_CLK_AUD_CPU_HCH, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB, DIV_CLK_AUD_CPU_ACLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK, DIV_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AXI_US_32to128_IPCLKPORT_aclk, DIV_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK, MUX_CLK_AUD_UAIF0, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK, MUX_CLK_AUD_UAIF2, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK, MUX_CLK_AUD_UAIF3, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_CPU_IPCLKPORT_CLK, MUX_CLK_AUD_CPU_HCH, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_BUS_IPCLKPORT_CLK, DIV_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM, DIV_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK, DIV_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_WDT_ABOXCPU_IPCLKPORT_PCLK, DIV_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_ABOXCPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_ABOXCPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_ABOXCPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2, MUX_CLK_AUD_UAIF2, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK, DIV_CLK_AUD_AUDIF, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_ACLK, DIV_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_PCLK, DIV_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK, DIV_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKS, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKM, MUX_CLKCMU_DISPAUD_BUS_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM, MUX_CLKCMU_DISPAUD_BUS_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKS, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKM, MUX_CLKCMU_DISPAUD_BUS_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM, MUX_CLKCMU_DISPAUD_BUS_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM, MUX_CLKCMU_DISPAUD_BUS_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AD_APB_DSIM0_IPCLKPORT_PCLKS, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DSIM0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DSIM0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_DSIM0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AXI2APB_DISPAUD_IPCLKPORT_ACLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI2APB_DISPAUD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI2APB_DISPAUD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI2APB_DISPAUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP, MUX_CLKCMU_DISPAUD_BUS_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA, MUX_CLKCMU_DISPAUD_BUS_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON0, MUX_CLKCMU_DISPAUD_BUS_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON0_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON0_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_LHS_AXI_D_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_DISPAUD_BUS_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_DISPAUD_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_DISPAUD_BUS_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_ACLK, MUX_CLKCMU_DISPAUD_BUS_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_PCLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BCM_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK, MUX_CLKCMU_DISPAUD_BUS_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_XIU_P_DISPAUD_IPCLKPORT_ACLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_XIU_P_DISPAUD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_XIU_P_DISPAUD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_XIU_P_DISPAUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK, DIV_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_ACLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_DAP_IPCLKPORT_dapclk, DIV_CLK_AUD_CPU_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY, DIV_CLK_AUD_FM, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKM, MUX_CLKCMU_DISPAUD_BUS_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKS, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKM, MUX_CLKCMU_DISPAUD_BUS_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKS, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AD_APB_SMMU_DPU_SECURE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_i_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_i_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_i_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_i_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN, MUX_CLKCMU_FSYS_MMC_CARD_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN, MUX_CLKCMU_FSYS_MMC_EMBD_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_bus_clk_early, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_BUS_CLK_EARLY_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_BUS_CLK_EARLY_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_BUS_CLK_EARLY_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_PHYCTRL, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_RSTnSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_AXI2AHB_FSYS_IPCLKPORT_aclk, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AXI2AHB_FSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AXI2AHB_FSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AXI2AHB_FSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_AHBBR_FSYS_1x4_IPCLKPORT_HCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_1X4_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_1X4_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_1X4_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_AHBBR_FSYS_IPCLKPORT_HCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHBBR_FSYS_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_LHS_AXI_D_FSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_AXI_D_FSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_AXI_D_FSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_AXI_D_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BCM_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_AHB2APB_FSYS_IPCLKPORT_HCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHB2APB_FSYS_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHB2APB_FSYS_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_AHB2APB_FSYS_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_SDCLKIN, MUX_CLKCMU_FSYS_MMC_SDIO_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_SDIO_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_RSTnSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_RSTnSYNC_CLK_G3D_GPU_IPCLKPORT_CLK, MUX_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_GPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_GPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_GPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_RSTnSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK, MUX_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK, MUX_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK, MUX_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_IS_UID_IS_CMU_IS_IPCLKPORT_PCLK, DIV_CLK_IS_APB, CLK_CON_GAT_CLK_BLK_IS_UID_IS_CMU_IS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_IS_UID_IS_CMU_IS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_IS_UID_IS_CMU_IS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_ASYNCM_P_IS_IPCLKPORT_I_CLK, DIV_CLK_IS_APB, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCM_P_IS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCM_P_IS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCM_P_IS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_SYSREG_IS_IPCLKPORT_PCLK, DIV_CLK_IS_APB, CLK_CON_GAT_GOUT_BLK_IS_UID_SYSREG_IS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_SYSREG_IS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_SYSREG_IS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS_VRA, MUX_CLKCMU_IS_VRA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_VRA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_RSTnSYNC_CLK_IS_VRA_IPCLKPORT_CLK, MUX_CLKCMU_IS_VRA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_VRA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_VRA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_VRA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_RSTnSYNC_CLK_IS_APB_IPCLKPORT_CLK, DIV_CLK_IS_APB, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_APB_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_APB_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_APB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_PCLK_IS, DIV_CLK_IS_APB, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_PCLK_IS_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_PCLK_IS_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_PCLK_IS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_ASYNCS_D1_IS_IPCLKPORT_I_CLK, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D1_IS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D1_IS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D1_IS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_ASYNCS_D0_IS_IPCLKPORT_I_CLK, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D0_IS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D0_IS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_ASYNCS_D0_IS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_RSTnSYNC_CLK_IS_3AA_IPCLKPORT_CLK, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_3AA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_3AA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_3AA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_XIU_IS_D, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_XIU_IS_D_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_XIU_IS_D_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_XIU_IS_D_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS_CSIS_0, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS_CSIS_0_HALF, DIV_CLK_IS_3AA_HALF, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0_HALF_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0_HALF_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_0_HALF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS_CSIS_1, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS_CSIS_1_HALF, DIV_CLK_IS_3AA_HALF, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1_HALF_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1_HALF_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_1_HALF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS_3AA, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_3AA_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_3AA_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_3AA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS_CSIS_DMA, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_CSIS_DMA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS_TPU, MUX_CLKCMU_IS_TPU_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_TPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_TPU_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_TPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_SMMU_IS_IPCLKPORT_ACLK, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_SMMU_IS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_SMMU_IS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_SMMU_IS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_ACLK, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_PCLK, DIV_CLK_IS_APB, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_RT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_ACLK, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_PCLK, DIV_CLK_IS_APB, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_BCM_NRT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_RSTnSYNC_CLK_IS_TPU_IPCLKPORT_CLK, MUX_CLKCMU_IS_TPU_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_TPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_TPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_RSTNSYNC_CLK_IS_TPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS1_ISP, MUX_CLKCMU_IS_ISP_USER, CLK_CON_GAT_CLK_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS1_ISP_CG_VAL, CLK_CON_GAT_CLK_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS1_ISP_MANUAL, CLK_CON_GAT_CLK_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS1_ISP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS_ASYNCM_3AA, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_3AA_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_3AA_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_3AA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS_ASYNCM_CSIS, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_CSIS_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_CSIS_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_CSIS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS_ASYNCM_VRA, MUX_CLKCMU_IS_VRA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_VRA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS_ASYNCM_TPU, MUX_CLKCMU_IS_TPU_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_TPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_TPU_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_TPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_RT, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_RT_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_RT_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_RT_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_NRT, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_NRT_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_NRT_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_SMMU_NRT_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS_ASYNCM_MCSC, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_MCSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_MCSC_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_ASYNCM_MCSC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_IS_UID_is5p15p0_IS_IPCLKPORT_CLK_IS_MCSC, MUX_CLKCMU_IS_3AA_USER, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_MCSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_MCSC_MANUAL, CLK_CON_GAT_GOUT_BLK_IS_UID_IS5P15P0_IS_IPCLKPORT_CLK_IS_MCSC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MFCMSCL_UID_MFCMSCL_CMU_MFCMSCL_IPCLKPORT_PCLK, DIV_CLK_MFCMSCL_APB, CLK_CON_GAT_CLK_BLK_MFCMSCL_UID_MFCMSCL_CMU_MFCMSCL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFCMSCL_UID_MFCMSCL_CMU_MFCMSCL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFCMSCL_UID_MFCMSCL_CMU_MFCMSCL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_LHM_AXI_P_MFCMSCL_IPCLKPORT_I_CLK, DIV_CLK_MFCMSCL_APB, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHM_AXI_P_MFCMSCL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHM_AXI_P_MFCMSCL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHM_AXI_P_MFCMSCL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKM, MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKS, DIV_CLK_MFCMSCL_APB, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MFC_P_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKS, DIV_CLK_MFCMSCL_APB, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKM, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKS, DIV_CLK_MFCMSCL_APB, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_MSCL_P_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_AXI2APB_MFCMSCL_IPCLKPORT_ACLK, DIV_CLK_MFCMSCL_APB, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_AXI2APB_MFCMSCL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_AXI2APB_MFCMSCL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_AXI2APB_MFCMSCL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_MFC_IPCLKPORT_Clk, MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MFC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MFC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_SYSREG_MFCMSCL_IPCLKPORT_PCLK, DIV_CLK_MFCMSCL_APB, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SYSREG_MFCMSCL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SYSREG_MFCMSCL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SYSREG_MFCMSCL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_RSTnSYNC_CLK_MFCMSCL_MFC_IPCLKPORT_CLK, MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MFC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MFC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_RSTnSYNC_CLK_MFCMSCL_MSCL_IPCLKPORT_CLK, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MSCL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MSCL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_MSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKS, DIV_CLK_MFCMSCL_APB, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_RSTnSYNC_CLK_MFCMSCL_APB_IPCLKPORT_CLK, DIV_CLK_MFCMSCL_APB, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_APB_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_APB_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_RSTNSYNC_CLK_MFCMSCL_APB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKS, DIV_CLK_MFCMSCL_APB, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_G2D_IPCLKPORT_Clk, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_G2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_G2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_PCLK, DIV_CLK_MFCMSCL_APB, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_ACLK, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_BCM_MFCMSCL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_SMMU_MFCMSCL_IPCLKPORT_CLK, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SMMU_MFCMSCL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SMMU_MFCMSCL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_SMMU_MFCMSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_XIU_D_MFCMSCL_IPCLKPORT_ACLK, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_XIU_D_MFCMSCL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_XIU_D_MFCMSCL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_XIU_D_MFCMSCL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKM, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_G2D_P_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKM, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_JPEG_P_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_JPEG_IPCLKPORT_I_FIMP_CLK, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_JPEG_IPCLKPORT_I_FIMP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_JPEG_IPCLKPORT_I_FIMP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_JPEG_IPCLKPORT_I_FIMP_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_LHS_AXI_D_MFCMSCL_IPCLKPORT_I_CLK, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHS_AXI_D_MFCMSCL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHS_AXI_D_MFCMSCL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_LHS_AXI_D_MFCMSCL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKM, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_NS_P_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_MSCL_IPCLKPORT_ACLK, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MSCL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MSCL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_MSCL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKM, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKS, DIV_CLK_MFCMSCL_APB, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_SMMU_S_P_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKM, MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKS, MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MFCMSCL_UID_ASYNC_AXI_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_RSTnSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AHB_BRIDGE_IPCLKPORT_HCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB_BRIDGE_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB_BRIDGE_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB_BRIDGE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AHB2APB_COREP0_IPCLKPORT_HCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_COREP0_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_COREP0_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_COREP0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AXI2AHB_COREP_IPCLKPORT_aclk, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_COREP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_COREP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_COREP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AXI2APB_2MB_BUSCP_IPCLKPORT_ACLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_2MB_BUSCP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_2MB_BUSCP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_2MB_BUSCP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_CCI_400_IPCLKPORT_ACLK, DIV_CLK_MIF_CCI, CLK_CON_GAT_GOUT_BLK_MIF_UID_CCI_400_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_CCI_400_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_CCI_400_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_MIF_CCI, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK, DIV_CLK_MIF_CCI, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_MIF_CCI, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_D_DPU_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_D_FSYS_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_FSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_FSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_D_ISPNRT_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPNRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPNRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPNRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_D_ISPRT_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ISPRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_D_MFCMSCL_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_MFCMSCL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_MFCMSCL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_MFCMSCL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHS_AXI_P_IS_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_IS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_IS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_IS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHS_AXI_P_MFCMSCL_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_MFCMSCL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_MFCMSCL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_MFCMSCL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_MAILBOX_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_MAILBOX_GNSSS_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_GNSSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_GNSSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_GNSSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_MAILBOX_WLBT0_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_ACLK, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPCFW_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_ACLK, DIV_CLK_MIF_CCI, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_ACLK, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_pclk, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_ACLK, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_CCLK, DIV_CLK_MIF_CCI, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_CCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_CCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_P_CORE_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_HCLK_AHB2APB_BRIDGE_MIF, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_HCLK_AHB2APB_BRIDGE_MIF_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_HCLK_AHB2APB_BRIDGE_MIF_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_HCLK_AHB2APB_BRIDGE_MIF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_DDR_PHY0_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_DDR_PHY0_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_DDR_PHY0_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_DDR_PHY0_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_DMC0, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_DMC0_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_DMC0_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_DMC0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_SECURE_DMC0, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_SECURE_DMC0_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_SECURE_DMC0_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_SECURE_DMC0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PF_DMC0, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PF_DMC0_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PF_DMC0_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PF_DMC0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PPMPU_DMC0, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PPMPU_DMC0_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PPMPU_DMC0_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_PPMPU_DMC0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_RSTnSYNC_CLK_MIF_CCI_IPCLKPORT_CLK, DIV_CLK_MIF_CCI, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_CCI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_CCI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_RSTnSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_RSTnSYNC_CLK_MIF_PHY_CLK2X_IPCLKPORT_CLK, MUX_CLK_MIF_DDRPHY_CLK2X, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_PHY_CLK2X_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_PHY_CLK2X_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_PHY_CLK2X_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_ACLK, CLK_MIF_DDRPHY, CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_BCM_CPU_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_ACLK_DMC0, CLK_MIF_DDRPHY, CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_ACLK_DMC0_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_ACLK_DMC0_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_ACLK_DMC0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK, DIV_CLK_MIF_CCI, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_GIC400_AIHWACG_IPCLKPORT_CLK, MUX_CLK_MIF_GIC, CLK_CON_GAT_GOUT_BLK_MIF_UID_GIC400_AIHWACG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_GIC400_AIHWACG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_GIC400_AIHWACG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKS, DIV_CLK_MIF_CCI, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_I_PCLK_ASYNCSFR_WR_DMC_SECURE, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_I_PCLK_ASYNCSFR_WR_DMC_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_I_PCLK_ASYNCSFR_WR_DMC_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_I_PCLK_ASYNCSFR_WR_DMC_SECURE_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_APBBR_DMC_SECURE, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_APBBR_DMC_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_APBBR_DMC_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_PCLK_APBBR_DMC_SECURE_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKM, CLK_MIF_DDRPHY, CLK_CON_GAT_CLK_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK, DIV_CLK_MIF_CCI, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AXI_US_A40_32to128_PDMA_IPCLKPORT_aclk, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_PDMA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_PDMA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_PDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AXI_US_A40_32to128_SDMA_IPCLKPORT_aclk, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_SDMA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_SDMA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_32TO128_SDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AXI_US_A40_64to128_CSSYS_IPCLKPORT_aclk, DIV_CLK_MIF_CCI, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_64TO128_CSSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_64TO128_CSSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_US_A40_64TO128_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MIF_UID_RSTnSYNC_CLK_MIF_DDRPHY_IPCLKPORT_CLK, CLK_MIF_DDRPHY, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_DDRPHY_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_DDRPHY_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_DDRPHY_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_MCLK, CLK_MIF_DDRPHY, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_MCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_MCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_TREX_D_CORE_IPCLKPORT_MCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_XIU_D_PDMA_3x1_IPCLKPORT_ACLK, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_XIU_D_PDMA_3X1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_XIU_D_PDMA_3X1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_XIU_D_PDMA_3X1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_ACLK, DIV_CLK_MIF_CCI, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCM_ACE_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM, DIV_CLK_MIF_BUS, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKS, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_ADS_APB_G_CSSYS_IPCLKPORT_PCLKS, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_ADS_APB_G_CSSYS_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_ADS_APB_G_CSSYS_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_ADS_APB_G_CSSYS_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AHB2APB_CSSYS_DBG_IPCLKPORT_HCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_CSSYS_DBG_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_CSSYS_DBG_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AHB2APB_CSSYS_DBG_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI_ASYNC_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_QE_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AXI2AHB_CORE_CSSYS_IPCLKPORT_aclk, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_CORE_CSSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_CORE_CSSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2AHB_CORE_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_RSTnSYNC_CLK_MIF_GIC_IPCLKPORT_CLK, MUX_CLK_MIF_GIC, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_clk, MUX_CLK_MIF_DDRPHY_CLK2X, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LBLK_MIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_QE_IPCLKPORT_ACLK, CLK_MIF_DDRPHY, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKM, MUX_CLK_MIF_GIC, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_SFR_APBIF_CMU_CMU_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFR_APBIF_CMU_CMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFR_APBIF_CMU_CMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFR_APBIF_CMU_CMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_MAILBOX_ABOX_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_MAILBOX_WLBT1_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_MAILBOX_WLBT1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_MIF_PHY_CLKM, DIV_CLK_MIF_PHY_CLKM, CLK_CON_GAT_CLK_MIF_PHY_CLKM_CG_VAL, CLK_CON_GAT_CLK_MIF_PHY_CLKM_MANUAL, CLK_CON_GAT_CLK_MIF_PHY_CLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MODEM_UID_MODEM_CMU_IPCLKPORT_PCLK, AP2CP_SHARED0_PLL_CLK, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_BUS_IPCLKPORT_CLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C6_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C6_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C6_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C6_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C0_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C0_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C0_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C0_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C1_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C1_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C1_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C1_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C2_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C2_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C2_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C2_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C3_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C3_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C3_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C3_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C4_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C4_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C4_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C4_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C5_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C5_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C5_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_I2C5_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_PWM_MOTOR_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_PWM_MOTOR_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_PWM_MOTOR_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_PWM_MOTOR_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_SPI_EXT_CLK, MUX_CLKCMU_PERI_SPI0_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_SPI_EXT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_SPI_EXT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_SPI_EXT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI0_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_SPI_EXT_CLK, MUX_CLKCMU_PERI_SPI1_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_SPI_EXT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_SPI_EXT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_SPI1_SPI_EXT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_EXT_UCLK, MUX_CLKCMU_PERI_UART_0_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_EXT_UCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_EXT_UCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART0_EXT_UCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_EXT_UCLK, MUX_CLKCMU_PERI_UART_1_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_EXT_UCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_EXT_UCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART1_EXT_UCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C3_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C3_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C3_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C3_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C1_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C1_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C1_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C1_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C0_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C0_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C0_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C0_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C2_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C2_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C2_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_HSI2C2_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_SECUCON_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_SECUCON_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SECUCON_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SECUCON_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_AXI2AHB_PERI_IPCLKPORT_aclk, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_PERI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_PERI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_PERI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_BUSP_BR_PERI_IPCLKPORT_HCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP_BR_PERI_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP_BR_PERI_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP_BR_PERI_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC0_HCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC0_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC0_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC0_HCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC1_HCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC1_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC1_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_BUSP1_PERIC1_HCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_GPIO_TOP_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_GPIO_TOP_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_GPIO_TOP_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_GPIO_TOP_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_SCLK, MUX_CLKCMU_PERI_USI0_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI0_SCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_SCLK, MUX_CLKCMU_PERI_USI1_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI1_SCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_SCLK, MUX_CLKCMU_PERI_USI2_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_SCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_EXT_UCLK, MUX_CLKCMU_PERI_UART_2_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_EXT_UCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_EXT_UCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_UART2_EXT_UCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LBLK_PERIC_IPCLKPORT_USI2_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| }; |
| |
| /*====================The section of FIXED RATEs===================*/ |
| unsigned int cmucal_fixed_rate_size = 17; |
| |
| |
| struct cmucal_clk_fixed_rate cmucal_fixed_rate_list[] = { |
| FIXEDRATE(OSCCLK_APM, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_CMU, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_CPUCL0, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_CPUCL1, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_DISPAUD, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(IOCLK_AUDIOCDCLK0, 10000000, EMPTY_CAL_ID), |
| FIXEDRATE(IOCLK_AUDIOCDCLK2, 10000000, EMPTY_CAL_ID), |
| FIXEDRATE(IOCLK_AUDIOCDCLK3, 100000000, EMPTY_CAL_ID), |
| FIXEDRATE(CLK_DEBUG_DECON0, 100000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_FSYS, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(WIFI2AP_USBPLL_CLK, 20000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_G3D, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_IS, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_MFCMSCL, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_MIF, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(CLK_MIF_DDRPHY, 466000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_PERI, 26000000, EMPTY_CAL_ID), |
| }; |
| |
| /*====================The section of FIXED FACTORs===================*/ |
| unsigned int cmucal_fixed_factor_size = 2; |
| |
| |
| struct cmucal_clk_fixed_factor cmucal_fixed_factor_list[] = { |
| FIXEDFACTOR(PLL_MEM_DIV2, PLL_MEM, 1, CLK_CON_DIV_PLL_MEM_DIV2_ENABLE_AUTOMATIC_CLKGATING), |
| FIXEDFACTOR(DIV_CLK_MIF_PHY_CLKM, MUX_CLK_MIF_DDRPHY_CLK2X, 1, CLK_CON_DIV_DIV_CLK_MIF_PHY_CLKM_ENABLE_AUTOMATIC_CLKGATING), |
| }; |
| |