| /* |
| ***************************************************************************** |
| * Copyright by ams AG * |
| * All rights are reserved. * |
| * * |
| * IMPORTANT - PLEASE READ CAREFULLY BEFORE COPYING, INSTALLING OR USING * |
| * THE SOFTWARE. * |
| * * |
| * THIS SOFTWARE IS PROVIDED FOR USE ONLY IN CONJUNCTION WITH AMS PRODUCTS. * |
| * USE OF THE SOFTWARE IN CONJUNCTION WITH NON-AMS-PRODUCTS IS EXPLICITLY * |
| * EXCLUDED. * |
| * * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * |
| * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * |
| * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * |
| * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * |
| * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * |
| * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * |
| * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * |
| * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * |
| ***************************************************************************** |
| */ |
| |
| /*! \file |
| * \brief Device driver for monitoring ambient light intensity in (lux) |
| * proximity detection (prox), and color temperature functionality within the |
| * AMS-TAOS AMS family of devices. |
| */ |
| |
| #ifndef AMS_REG_H |
| #define AMS_REG_H |
| |
| #define AMS_REG_RAM_START 0x00 |
| #define AMS_REG_ENABLE 0x80 |
| #define AMS_REG_ATIME 0x81 |
| #define AMS_REG_PTIME 0x82 |
| #define AMS_REG_WTIME 0x83 |
| #define AMS_REG_AILTL 0x84 |
| #define AMS_REG_AILTH 0x85 |
| #define AMS_REG_AIHTL 0x86 |
| #define AMS_REG_AIHTH 0x87 |
| #define AMS_REG_PILTL0 0x88 |
| #define AMS_REG_PILTH0 0x89 |
| #define AMS_REG_PILTL1 0x8A |
| #define AMS_REG_PILTH1 0x8B |
| #define AMS_REG_PIHTL0 0x8C |
| #define AMS_REG_PIHTH0 0x8D |
| #define AMS_REG_PIHTL1 0x8E |
| #define AMS_REG_PIHTH1 0x8F |
| #define AMS_REG_AUXID 0x90 |
| #define AMS_REG_REVID 0x91 |
| #define AMS_REG_ID 0x92 |
| #define AMS_REG_STATUS 0x93 |
| #define AMS_REG_ASTATUS 0x94 |
| #define AMS_REG_ADATAL0 0x95 |
| #define AMS_REG_ADATAH0 0x96 |
| #define AMS_REG_ADATAL1 0x97 |
| #define AMS_REG_ADATAH1 0x98 |
| #define AMS_REG_ADATAL2 0x99 |
| #define AMS_REG_ADATAH2 0x9A |
| #define AMS_REG_ADATAL3 0x9B |
| #define AMS_REG_ADATAH3 0x9C |
| #define AMS_REG_ADATAL4 0x9D |
| #define AMS_REG_ADATAH4 0x9E |
| #define AMS_REG_ADATAL5 0x9F |
| #define AMS_REG_ADATAH5 0xA0 |
| #define AMS_REG_PDATAL 0xA1 |
| #define AMS_REG_PDATAH 0xA2 |
| #define AMS_REG_STATUS2 0xA3 |
| #define AMS_REG_STATUS3 0xA4 |
| #define AMS_REG_STATUS4 0xA5 |
| #define AMS_REG_STATUS5 0xA6 |
| #define AMS_REG_STATUS6 0xA7 |
| #define AMS_REG_CFG0 0xA9 |
| #define AMS_REG_CFG1 0xAA |
| #define AMS_REG_CFG3 0xAC |
| #define AMS_REG_CFG4 0xAD |
| #define AMS_REG_CFG6 0xAF |
| #define AMS_REG_CFG8 0xB1 |
| #define AMS_REG_CFG9 0xB2 |
| #define AMS_REG_CFG10 0xB3 |
| #define AMS_REG_CFG11 0xB4 |
| #define AMS_REG_CFG12 0xB5 |
| #define AMS_REG_CFG14 0xB7 |
| #define AMS_REG_PCFG1 0xB8 |
| #define AMS_REG_PCFG2 0xB9 |
| #define AMS_REG_PCFG4 0xBB |
| #define AMS_REG_PCFG5 0xBC |
| #define AMS_REG_PERS 0xBD |
| #define AMS_REG_GPIO 0xBE |
| #define AMS_REG_POFFSETL 0xC7 |
| #define AMS_REG_POFFSETH 0xC8 |
| #define AMS_REG_ASTEPL 0xCA |
| #define AMS_REG_ASTEPH 0xCB |
| #define AMS_REG_AGC_GAIN_MAX 0xCF |
| #define AMS_REG_PXAVEL 0xD0 |
| #define AMS_REG_PXAVEH 0xD1 |
| #define AMS_REG_PBSLNL 0xD2 |
| #define AMS_REG_PBSLNH 0xD3 |
| #define AMS_REG_ALS_CHANNEL_CTRL 0xD5 |
| #define AMS_REG_AZCONFIG 0xD6 |
| #define AMS_REG_FD_STATUS 0xDB |
| #define AMS_ICONFIG 0xE0 |
| #define AMS_ICONFIG2 0xE1 |
| #define AMS_ISNL 0xE2 |
| #define AMS_ISOFF 0xE3 |
| #define AMS_IPNL 0xE4 |
| #define AMS_IPOFF 0xE5 |
| #define AMS_IBT 0xE6 |
| #define AMS_ISLEN 0xE7 |
| #define AMS_ISTART 0xE8 |
| #define AMS_REG_CALIB 0xEA |
| #define AMS_REG_CALIBCFG0 0xEB |
| #define AMS_REG_CALIBCFG1 0xEC |
| #define AMS_REG_CALIBCFG2 0xED |
| #define AMS_REG_CALIBSTAT 0xEE |
| #define AMS_REG_INTENAB 0xF9 |
| #define AMS_REG_CONTROL 0xFA |
| #define AMS_REG_FIFO_MAP 0xFC |
| #define AMS_REG_FIFO_LVL 0xFD |
| #define AMS_REG_FDATAL 0xFE |
| #define AMS_REG_FDATAH 0xFF |
| |
| #define AMS_PON_SHIFT 0 |
| #define AMS_MASK_PON (1 << AMS_PON_SHIFT) |
| |
| #define AMS_AEN_SHIFT 1 |
| #define AMS_MASK_AEN (1 << AMS_AEN_SHIFT) |
| |
| #define AMS_PEN_SHIFT 2 |
| #define AMS_MASK_PEN (1 << AMS_PEN_SHIFT) |
| |
| #define AMS_WEN_SHIFT 3 |
| #define AMS_MASK_WEN (1 << AMS_WEN_SHIFT) |
| |
| #define AMS_FDEN_SHIFT 6 |
| #define AMS_MASK_FDEN (1 << AMS_FDEN_SHIFT) |
| |
| #define AMS_IBEN_SHIFT 7 |
| #define AMS_MASK_IBEN (1 << AMS_IBEN_SHIFT) |
| |
| #define AMS_SIEN_SHIFT 0 |
| #define AMS_MASK_SIEN (1 << AMS_SIEN_SHIFT) |
| |
| #define AMS_CIEN_SHIFT 1 |
| #define AMS_MASK_CIEN (1 << AMS_CIEN_SHIFT) |
| |
| #define AMS_FIEN_SHIFT 2 |
| #define AMS_MASK_FIEN (1 << AMS_FIEN_SHIFT) |
| |
| #define AMS_AIEN_SHIFT 3 |
| #define AMS_MASK_AIEN (1 << AMS_AIEN_SHIFT) |
| |
| #define AMS_PIEN0_SHIFT 4 |
| #define AMS_MASK_PIEN0 (1 << AMS_PIEN0_SHIFT) |
| |
| #define AMS_PIEN1_SHIFT 5 |
| #define AMS_MASK_PIEN1 (1 << AMS_PIEN1_SHIFT) |
| |
| #define AMS_PSIEN_SHIFT 6 |
| #define AMS_MASK_PSIEN (1 << AMS_PSIEN_SHIFT) |
| |
| #define AMS_ASIEN_SHIFT 7 |
| #define AMS_MASK_ASIEN (1 << AMS_ASIEN_SHIFT) |
| |
| #define AMS_CLEAR_SAI_ACTIVE_SHIFT 0 |
| #define AMS_MASK_CLEAR_SAI_ACTIVE (1 << AMS_CLEAR_SAI_ACTIVE_SHIFT) |
| |
| #define AMS_FIFO_CLR_SHIFT 1 |
| #define AMS_MASK_FIFO_CLR (1 << AMS_FIFO_CLR_SHIFT) |
| |
| #define AMS_ALS_MANUAL_AZ_SHIFT 2 |
| #define AMS_MASK_ALS_MANUAL_AZ (1 << AMS_ALS_MANUAL_AZ_SHIFT) |
| |
| #define AMS_AGAIN_SHIFT 0 |
| #define AMS_MASK_AGAIN (0x1F << AMS_AGAIN_SHIFT) |
| |
| #define AMS_RAM_BANK_SHIFT 0 |
| #define AMS_MASK_RAM_BANK (0x3 << AMS_RAM_BANK_SHIFT) |
| |
| #define AMS_ALS_TRIGGER_LONG_SHIFT 2 |
| #define AMS_MASK_ALS_TRIGGER_LONG (1 << AMS_ALS_TRIGGER_LONG_SHIFT) |
| |
| #define AMS_PROX_TRIGGER_LONG_SHIFT 3 |
| #define AMS_MASK_PROX_TRIGGER_LONG (1 << AMS_PROX_TRIGGER_LONG) |
| |
| #define AMS_LOWPOWER_IDLE_SHIFT 5 |
| #define AMS_MASK_LOWPOWER_IDLE (1 << AMS_LOWPOWER_IDLE_SHIFT) |
| |
| #define AMS_SWAP_PROX_ALS5_SHIFT 0 |
| #define AMS_MASK_SWAP_PROX_ALS5 (1 << AMS_SWAP_PROX_ALS5_SHIFT) |
| |
| #define AMS_ALS_AGC_ENABLE_SHIFT 2 |
| #define AMS_MASK_ALS_AGC_ENABLE (1 << AMS_ALS_AGC_ENABLE_SHIFT) |
| |
| #define AMS_FD_AGC_DISABLE_SHIFT 3 |
| #define AMS_MASK_FD_AGC_DISABLE (1 << AMS_FD_AGC_DISABLE_SHIFT) |
| |
| #define AMS_CONCURRENT_PROX_AND_ALS_SHIFT 4 |
| #define AMS_MASK_CONCURRENT_PROX_AND_ALS (1 << AMS_CONCURRENT_PROX_AND_ALS_SHIFT) |
| |
| #define AMS_FIFO_THR_SHIFT 6 |
| #define AMS_MASK_FIFO_THR (0xC0 << AMS_FIFO_THR_SHIFT) |
| |
| #define AMS_APERS_SHIFT 0 |
| #define AMS_MASK_APERS (0xF << AMS_APERS_SHIFT) |
| |
| #define AMS_PPERS_SHIFT 4 |
| #define AMS_MASK_PPERS (0xF0 << AMS_PPERS_SHIFT) |
| |
| #define AMS_FIFO_WRITE_ASTATUS_SHIFT 0 |
| #define AMS_MASK_FIFO_WRITE_ASTATUS (1 << AMS_FIFO_WRITE_ASTATUS_SHIFT) |
| |
| #define AMS_FIFO_WRITE_ADATA0_SHIFT 1 |
| #define AMS_MASK_FIFO_WRITE_ADATA0 (1 << AMS_FIFO_WRITE_ADATA0_SHIFT) |
| |
| #define AMS_FIFO_WRITE_ADATA1_SHIFT 2 |
| #define AMS_MASK_FIFO_WRITE_ADATA1 (1 << AMS_FIFO_WRITE_ADATA1_SHIFT) |
| |
| #define AMS_FIFO_WRITE_ADATA2_SHIFT 3 |
| #define AMS_MASK_FIFO_WRITE_ADATA2 (1 << AMS_FIFO_WRITE_ADATA2_SHIFT) |
| |
| #define AMS_FIFO_WRITE_ADATA3_SHIFT 4 |
| #define AMS_MASK_FIFO_WRITE_ADATA3 (1 << AMS_FIFO_WRITE_ADATA3_SHIFT) |
| |
| #define AMS_FIFO_WRITE_ADATA4_SHIFT 5 |
| #define AMS_MASK_FIFO_WRITE_ADATA4 (1 << AMS_FIFO_WRITE_ADATA4_SHIFT) |
| |
| #define AMS_FIFO_WRITE_ADATA5_SHIFT 6 |
| #define AMS_MASK_FIFO_WRITE_ADATA5 (1 << AMS_FIFO_WRITE_ADATA5_SHIFT) |
| |
| #define AMS_FIFO_WRITE_PDATA_SHIFT 7 |
| #define AMS_MASK_FIFO_WRITE_PDATA (1 << AMS_FIFO_WRITE_PDATA_SHIFT) |
| |
| #define AMS_SINT_SHIFT 0 |
| #define AMS_MASK_SINT (1 << AMS_SINT_SHIFT) |
| |
| #define AMS_CINT_SHIFT 1 |
| #define AMS_MASK_CINT (1 << AMS_CINT_SHIFT) |
| |
| #define AMS_FINT_SHIFT 2 |
| #define AMS_MASK_FINT (1 << AMS_FINT_SHIFT) |
| |
| #define AMS_AINT_SHIFT 3 |
| #define AMS_MASK_AINT (1 << AMS_AINT_SHIFT) |
| |
| #define AMS_PINT0_SHIFT 4 |
| #define AMS_MASK_PINT0 (1 << AMS_PINT0_SHIFT) |
| |
| #define AMS_PINT1_SHIFT 5 |
| #define AMS_MASK_PINT1 (1 << AMS_PINT1_SHIFT) |
| |
| #define AMS_PSAT_SHIFT 6 |
| #define AMS_MASK_PSAT (1 << AMS_PSAT_SHIFT) |
| |
| #define AMS_ASAT_SHIFT 7 |
| #define AMS_MASK_ASAT (1 << AMS_ASAT_SHIFT) |
| |
| #define AMS_FIFO_OV_SHIFT 7 |
| #define AMS_MASK_FIFO_OV (1 << AMS_FIFO_OV_SHIFT) |
| |
| #endif /* AMS_REG_H */ |