| /* |
| * Copyright (c) 2016 Samsung Electronics Co., Ltd. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * Device Tree binding constants for Emulator8895 clock controller. |
| */ |
| |
| #ifndef _DT_BINDINGS_CLOCK_EMULATOR_8895_H |
| #define _DT_BINDINGS_CLOCK_EMULATOR_8895_H |
| |
| #define NONE (0 + 0) |
| #define OSCCLK (0 + 1) |
| |
| /* NUMBER FOR MFC DRIVER STARTS FROM 10 */ |
| #define CLK_MFC_BASE (10) |
| #define GATE_MFC (CLK_MFC_BASE + 0) |
| #define GATE_BTM_MFCD0 (CLK_MFC_BASE + 1) |
| #define GATE_BTM_MFCD1 (CLK_MFC_BASE + 2) |
| #define GATE_MFC_CMU_MFC (CLK_MFC_BASE + 3) |
| #define GATE_PMU_MFC (CLK_MFC_BASE + 4) |
| #define GATE_BCM_MFCD0 (CLK_MFC_BASE + 5) |
| #define GATE_BCM_MFCD1 (CLK_MFC_BASE + 6) |
| #define GATE_SMMU_MFCD0 (CLK_MFC_BASE + 7) |
| #define GATE_SMMU_MFCD1 (CLK_MFC_BASE + 8) |
| #define GATE_SYSREG_MFC (CLK_MFC_BASE + 9) |
| #define UMUX_CLKCMU_MFC_BUS (CLK_MFC_BASE + 10) |
| |
| /* NUMBER FOR MSCL DRIVER STARTS FROM 50 */ |
| #define CLK_MSCL_BASE (50) |
| |
| /* NUMBER FOR IMEM DRIVER STARTS FROM 100 */ |
| #define CLK_IMEM_BASE (100) |
| #define GATE_INTMEM (CLK_IMEM_BASE + 0) |
| #define GATE_IMEM_CMU_IMEM (CLK_IMEM_BASE + 1) |
| #define GATE_PMU_IMEM (CLK_IMEM_BASE + 2) |
| #define GATE_SYSREG_IMEM (CLK_IMEM_BASE + 3) |
| #define UMUX_CLKCMU_IMEM_BUS (CLK_IMEM_BASE + 4) |
| |
| /* NUMBER FOR PERIS DRIVER STARTS FROM 150 */ |
| #define CLK_PERIS_BASE (150) |
| #define GATE_BUSIF_TMU (CLK_PERIS_BASE + 0) |
| #define GATE_GIC (CLK_PERIS_BASE + 1) |
| #define GATE_MCT (CLK_PERIS_BASE + 2) |
| #define GATE_OTP_CON_BIRA (CLK_PERIS_BASE + 3) |
| #define GATE_OTP_CON_TOP (CLK_PERIS_BASE + 4) |
| #define GATE_TZPC00 (CLK_PERIS_BASE + 5) |
| #define GATE_TZPC01 (CLK_PERIS_BASE + 6) |
| #define GATE_TZPC02 (CLK_PERIS_BASE + 7) |
| #define GATE_TZPC03 (CLK_PERIS_BASE + 8) |
| #define GATE_TZPC04 (CLK_PERIS_BASE + 9) |
| #define GATE_TZPC05 (CLK_PERIS_BASE + 10) |
| #define GATE_TZPC06 (CLK_PERIS_BASE + 11) |
| #define GATE_TZPC07 (CLK_PERIS_BASE + 12) |
| #define GATE_TZPC08 (CLK_PERIS_BASE + 13) |
| #define GATE_TZPC09 (CLK_PERIS_BASE + 14) |
| #define GATE_TZPC10 (CLK_PERIS_BASE + 15) |
| #define GATE_TZPC11 (CLK_PERIS_BASE + 16) |
| #define GATE_TZPC12 (CLK_PERIS_BASE + 17) |
| #define GATE_TZPC13 (CLK_PERIS_BASE + 18) |
| #define GATE_TZPC14 (CLK_PERIS_BASE + 19) |
| #define GATE_TZPC15 (CLK_PERIS_BASE + 20) |
| #define GATE_WDT_CLUSTER0 (CLK_PERIS_BASE + 21) |
| #define GATE_WDT_CLUSTER1 (CLK_PERIS_BASE + 22) |
| #define GATE_PERIS_CMU_PERIS (CLK_PERIS_BASE + 23) |
| #define GATE_PMU_PERIS (CLK_PERIS_BASE + 24) |
| #define GATE_SYSREG_PERIS (CLK_PERIS_BASE + 25) |
| #define UMUX_CLKCMU_PERIS_BUS (CLK_PERIS_BASE + 26) |
| |
| /* NUMBER FOR PERIC0 DRIVER STARTS FROM 200 */ |
| #define CLK_PERIC0_BASE (200) |
| #define UART_DBG (CLK_PERIC0_BASE + 0) |
| #define USI00 (CLK_PERIC0_BASE + 1) |
| #define USI01 (CLK_PERIC0_BASE + 2) |
| #define USI02 (CLK_PERIC0_BASE + 3) |
| #define USI03 (CLK_PERIC0_BASE + 4) |
| #define GATE_USI00 (CLK_PERIC0_BASE + 5) |
| #define GATE_USI01 (CLK_PERIC0_BASE + 6) |
| #define GATE_USI02 (CLK_PERIC0_BASE + 7) |
| #define GATE_USI03 (CLK_PERIC0_BASE + 8) |
| #define GATE_GPIO_PERIC0 (CLK_PERIC0_BASE + 9) |
| #define GATE_PERIC0_CMU_PERIC0 (CLK_PERIC0_BASE + 10) |
| #define GATE_PMU_PERIC0 (CLK_PERIC0_BASE + 11) |
| #define GATE_PWM (CLK_PERIC0_BASE + 12) |
| #define GATE_SPEEDY2_TSP (CLK_PERIC0_BASE + 13) |
| #define GATE_SYSREG_PERIC0 (CLK_PERIC0_BASE + 14) |
| #define GATE_UART_DBG (CLK_PERIC0_BASE + 15) |
| #define UMUX_CLKCMU_PERIC0_BUS (CLK_PERIC0_BASE + 16) |
| #define UMUX_CLKCMU_PERIC0_UART_DBG (CLK_PERIC0_BASE + 17) |
| #define UMUX_CLKCMU_PERIC0_USI00 (CLK_PERIC0_BASE + 18) |
| #define UMUX_CLKCMU_PERIC0_USI01 (CLK_PERIC0_BASE + 19) |
| #define UMUX_CLKCMU_PERIC0_USI02 (CLK_PERIC0_BASE + 20) |
| #define UMUX_CLKCMU_PERIC0_USI03 (CLK_PERIC0_BASE + 21) |
| |
| /* NUMBER FOR PERIC1 DRIVER STARTS FROM 250 */ |
| #define CLK_PERIC1_BASE (250) |
| #define SPI_CAM0 (CLK_PERIC1_BASE + 0) |
| #define SPI_CAM1 (CLK_PERIC1_BASE + 1) |
| #define UART_BT (CLK_PERIC1_BASE + 2) |
| #define USI04 (CLK_PERIC1_BASE + 3) |
| #define USI05 (CLK_PERIC1_BASE + 4) |
| #define USI06 (CLK_PERIC1_BASE + 5) |
| #define USI07 (CLK_PERIC1_BASE + 6) |
| #define USI08 (CLK_PERIC1_BASE + 7) |
| #define USI09 (CLK_PERIC1_BASE + 8) |
| #define USI10 (CLK_PERIC1_BASE + 9) |
| #define USI11 (CLK_PERIC1_BASE + 10) |
| #define USI12 (CLK_PERIC1_BASE + 11) |
| #define USI13 (CLK_PERIC1_BASE + 12) |
| #define GATE_USI04 (CLK_PERIC1_BASE + 13) |
| #define GATE_USI05 (CLK_PERIC1_BASE + 14) |
| #define GATE_USI06 (CLK_PERIC1_BASE + 15) |
| #define GATE_USI07 (CLK_PERIC1_BASE + 16) |
| #define GATE_USI08 (CLK_PERIC1_BASE + 17) |
| #define GATE_USI09 (CLK_PERIC1_BASE + 18) |
| #define GATE_USI10 (CLK_PERIC1_BASE + 19) |
| #define GATE_USI11 (CLK_PERIC1_BASE + 20) |
| #define GATE_USI12 (CLK_PERIC1_BASE + 21) |
| #define GATE_USI13 (CLK_PERIC1_BASE + 22) |
| #define GATE_UART_BT (CLK_PERIC1_BASE + 23) |
| #define GATE_HSI2C_CAM0 (CLK_PERIC1_BASE + 24) |
| #define GATE_HSI2C_CAM1 (CLK_PERIC1_BASE + 25) |
| #define GATE_HSI2C_CAM2 (CLK_PERIC1_BASE + 26) |
| #define GATE_HSI2C_CAM3 (CLK_PERIC1_BASE + 27) |
| #define GATE_GPIO_PERIC1 (CLK_PERIC1_BASE + 28) |
| #define GATE_PERIC1_CMU_PERIC1 (CLK_PERIC1_BASE + 29) |
| #define GATE_PMU_PERIC1 (CLK_PERIC1_BASE + 30) |
| #define GATE_SPEEDY2_DDI (CLK_PERIC1_BASE + 31) |
| #define GATE_SPEEDY2_DDI1 (CLK_PERIC1_BASE + 32) |
| #define GATE_SPEEDY2_DDI2 (CLK_PERIC1_BASE + 33) |
| #define GATE_SPEEDY2_TSP1 (CLK_PERIC1_BASE + 34) |
| #define GATE_SPEEDY2_TSP2 (CLK_PERIC1_BASE + 35) |
| #define GATE_SPI_CAM0 (CLK_PERIC1_BASE + 36) |
| #define GATE_SPI_CAM1 (CLK_PERIC1_BASE + 37) |
| #define GATE_SYSREG_PERIC1 (CLK_PERIC1_BASE + 38) |
| #define UMUX_CLKCMU_PERIC1_BUS (CLK_PERIC1_BASE + 39) |
| #define UMUX_CLKCMU_PERIC1_UART_BT (CLK_PERIC1_BASE + 40) |
| #define UMUX_CLKCMU_PERIC1_USI04 (CLK_PERIC1_BASE + 41) |
| #define UMUX_CLKCMU_PERIC1_USI05 (CLK_PERIC1_BASE + 42) |
| #define UMUX_CLKCMU_PERIC1_USI06 (CLK_PERIC1_BASE + 43) |
| #define UMUX_CLKCMU_PERIC1_USI07 (CLK_PERIC1_BASE + 44) |
| #define UMUX_CLKCMU_PERIC1_USI08 (CLK_PERIC1_BASE + 45) |
| #define UMUX_CLKCMU_PERIC1_USI09 (CLK_PERIC1_BASE + 46) |
| #define UMUX_CLKCMU_PERIC1_USI10 (CLK_PERIC1_BASE + 47) |
| #define UMUX_CLKCMU_PERIC1_USI11 (CLK_PERIC1_BASE + 48) |
| #define UMUX_CLKCMU_PERIC1_USI12 (CLK_PERIC1_BASE + 49) |
| #define UMUX_CLKCMU_PERIC1_USI13 (CLK_PERIC1_BASE + 50) |
| #define UMUX_CLKCMU_PERIC1_SPI_CAM0 (CLK_PERIC1_BASE + 51) |
| #define UMUX_CLKCMU_PERIC1_SPI_CAM1 (CLK_PERIC1_BASE + 52) |
| #define UMUX_CLKCMU_PERIC1_SPEEDY2 (CLK_PERIC1_BASE + 53) |
| |
| /* NUMBER FOR CMU DRIVER STARTS FROM 320 */ |
| #define CLK_CMU_BASE (320) |
| #define CMU_CMUREF (CLK_CMU_BASE + 0) |
| #define HPM (CLK_CMU_BASE + 1) |
| #define GATE_CMU_CMU_CMUREF (CLK_CMU_BASE + 2) |
| #define GATE_DFTMUX_TOP_CIS_CLK0 (CLK_CMU_BASE + 3) |
| #define GATE_DFTMUX_TOP_CIS_CLK1 (CLK_CMU_BASE + 4) |
| #define GATE_DFTMUX_TOP_CIS_CLK2 (CLK_CMU_BASE + 5) |
| #define GATE_DFTMUX_TOP_CIS_CLK3 (CLK_CMU_BASE + 6) |
| |
| /* NUMBER FOR CIS DRIVER STARTS FROM 350 */ |
| #define CLK_CIS_BASE (350) |
| #define CIS_CLK0 (CLK_CIS_BASE + 0) |
| #define CIS_CLK1 (CLK_CIS_BASE + 1) |
| #define CIS_CLK2 (CLK_CIS_BASE + 2) |
| #define CIS_CLK3 (CLK_CIS_BASE + 3) |
| |
| /* NUMBER FOR ISPHQ DRIVER STARTS FROM 400 */ |
| #define CLK_ISPHQ_BASE (400) |
| #define GATE_ISP_EWGEN_ISPHQ (CLK_ISPHQ_BASE + 0) |
| #define GATE_IS_ISPHQ_3AA (CLK_ISPHQ_BASE + 1) |
| #define GATE_IS_ISPHQ_ISPHQ (CLK_ISPHQ_BASE + 2) |
| #define GATE_IS_ISPHQ_QE_3AA (CLK_ISPHQ_BASE + 3) |
| #define GATE_IS_ISPHQ_QE_ISPHQ (CLK_ISPHQ_BASE + 4) |
| #define GATE_ISPHQ_CMU_ISPHQ (CLK_ISPHQ_BASE + 5) |
| #define GATE_PMU_ISPHQ (CLK_ISPHQ_BASE + 6) |
| #define GATE_SYSREG_ISPHQ (CLK_ISPHQ_BASE + 7) |
| #define UMUX_CLKCMU_ISPHQ_BUS (CLK_ISPHQ_BASE + 8) |
| |
| /* NUMBER FOR ISPLP DRIVER STARTS FROM 450 */ |
| #define CLK_ISPLP_BASE (450) |
| #define GATE_ISP_EWGEN_ISPLP (CLK_ISPLP_BASE + 0) |
| #define GATE_IS_ISPLP_3AAW (CLK_ISPLP_BASE + 1) |
| #define GATE_IS_ISPLP_ISPLP (CLK_ISPLP_BASE + 2) |
| #define GATE_IS_ISPLP_QE_3AAW (CLK_ISPLP_BASE + 3) |
| #define GATE_IS_ISPLP_QE_ISPLP (CLK_ISPLP_BASE + 4) |
| #define GATE_IS_ISPLP_SMMU_ISPLP (CLK_ISPLP_BASE + 5) |
| #define GATE_IS_ISPLP_BCM_ISPLP (CLK_ISPLP_BASE + 6) |
| #define GATE_BTM_ISPLP (CLK_ISPLP_BASE + 7) |
| #define GATE_ISPLP_CMU_ISPLP (CLK_ISPLP_BASE + 8) |
| #define GATE_PMU_ISPLP (CLK_ISPLP_BASE + 9) |
| #define GATE_SYSREG_ISPLP (CLK_ISPLP_BASE + 10) |
| #define UMUX_CLKCMU_ISPLP_BUS (CLK_ISPLP_BASE + 11) |
| |
| /* NUMBER FOR CAM DRIVER STARTS FROM 500 */ |
| #define CLK_CAM_BASE (500) |
| #define GATE_ISP_EWGEN_CAM (CLK_CAM_BASE + 0) |
| #define GATE_IS_CAM_CSIS0 (CLK_CAM_BASE + 1) |
| #define GATE_IS_CAM_CSIS1 (CLK_CAM_BASE + 2) |
| #define GATE_IS_CAM_CSIS2 (CLK_CAM_BASE + 3) |
| #define GATE_IS_CAM_CSIS3 (CLK_CAM_BASE + 4) |
| #define GATE_IS_CAM_MC_SCALER (CLK_CAM_BASE + 5) |
| #define GATE_IS_CAM_CSISX4_DMA (CLK_CAM_BASE + 6) |
| #define GATE_IS_CAM_SYSMMU_CAM0 (CLK_CAM_BASE + 7) |
| #define GATE_IS_CAM_SYSMMU_CAM1 (CLK_CAM_BASE + 8) |
| #define GATE_IS_CAM_BCM_CAM0 (CLK_CAM_BASE + 9) |
| #define GATE_IS_CAM_BCM_CAM1 (CLK_CAM_BASE + 10) |
| #define GATE_IS_CAM_TPU0 (CLK_CAM_BASE + 11) |
| #define GATE_IS_CAM_VRA (CLK_CAM_BASE + 12) |
| #define GATE_IS_CAM_QE_TPU0 (CLK_CAM_BASE + 13) |
| #define GATE_IS_CAM_QE_VRA (CLK_CAM_BASE + 14) |
| #define GATE_IS_CAM_BNS (CLK_CAM_BASE + 15) |
| #define GATE_IS_CAM_QE_CSISX4 (CLK_CAM_BASE + 16) |
| #define GATE_IS_CAM_QE_TPU1 (CLK_CAM_BASE + 17) |
| #define GATE_IS_CAM_TPU1 (CLK_CAM_BASE + 18) |
| #define GATE_BTM_CAMD0 (CLK_CAM_BASE + 19) |
| #define GATE_BTM_CAMD1 (CLK_CAM_BASE + 20) |
| #define GATE_CAM_CMU_CAM (CLK_CAM_BASE + 21) |
| #define GATE_PMU_CAM (CLK_CAM_BASE + 22) |
| #define GATE_SYSREG_CAM (CLK_CAM_BASE + 23) |
| #define UMUX_CLKCMU_CAM_BUS (CLK_CAM_BASE + 24) |
| #define UMUX_CLKCMU_CAM_TPU0 (CLK_CAM_BASE + 25) |
| #define UMUX_CLKCMU_CAM_VRA (CLK_CAM_BASE + 26) |
| #define UMUX_CLKCMU_CAM_TPU1 (CLK_CAM_BASE + 27) |
| |
| |
| /* NUMBER FOR DCAM DRIVER STARTS FROM 550 */ |
| #define CLK_DCAM_BASE (550) |
| #define GATE_DCP (CLK_DCAM_BASE + 0) |
| #define GATE_BTM_DCAM (CLK_DCAM_BASE + 1) |
| #define GATE_DCAM_CMU_DCAM (CLK_DCAM_BASE + 2) |
| #define GATE_PMU_DCAM (CLK_DCAM_BASE + 3) |
| #define GATE_BCM_DCAM (CLK_DCAM_BASE + 4) |
| #define GATE_SYSREG_DCAM (CLK_DCAM_BASE + 5) |
| #define UMUX_CLKCMU_DCAM_BUS (CLK_DCAM_BASE + 6) |
| #define UMUX_CLKCMU_DCAM_IMGD (CLK_DCAM_BASE + 7) |
| |
| /* NUMBER OF G2D DRIVER STARTS FROM 600 */ |
| #define CLK_G2D_BASE (600) |
| #define GATE_G2D (CLK_G2D_BASE + 0) |
| #define GATE_JPEG (CLK_G2D_BASE + 1) |
| #define GATE_M2MSCALER (CLK_G2D_BASE + 2) |
| #define GATE_BTM_G2DD0 (CLK_G2D_BASE + 3) |
| #define GATE_BTM_G2DD1 (CLK_G2D_BASE + 4) |
| #define GATE_BTM_G2DD2 (CLK_G2D_BASE + 5) |
| #define GATE_G2D_CMU_G2D (CLK_G2D_BASE + 6) |
| #define GATE_PMU_G2D (CLK_G2D_BASE + 7) |
| #define GATE_BCM_G2DD0 (CLK_G2D_BASE + 8) |
| #define GATE_BCM_G2DD1 (CLK_G2D_BASE + 9) |
| #define GATE_BCM_G2DD2 (CLK_G2D_BASE + 10) |
| #define GATE_QE_JPEG (CLK_G2D_BASE + 11) |
| #define GATE_QE_M2MSCALER (CLK_G2D_BASE + 12) |
| #define GATE_SMMU_G2DD0 (CLK_G2D_BASE + 13) |
| #define GATE_SMMU_G2DD1 (CLK_G2D_BASE + 14) |
| #define GATE_SMMU_G2DD2 (CLK_G2D_BASE + 15) |
| #define GATE_SYSREG_G2D (CLK_G2D_BASE + 16) |
| #define UMUX_CLKCMU_G2D_JPEG (CLK_G2D_BASE + 17) |
| #define UMUX_CLKCMU_G2D_G2D (CLK_G2D_BASE + 18) |
| |
| /* NUMBER FOR ABOX DRIVER STARTS FROM 650 */ |
| #define CLK_ABOX_BASE (650) |
| #define ABOX_CPU_PCLKDBG (CLK_ABOX_BASE + 0) |
| #define ABOX_UAIF0 (CLK_ABOX_BASE + 1) |
| #define ABOX_UAIF1 (CLK_ABOX_BASE + 2) |
| #define ABOX_UAIF2 (CLK_ABOX_BASE + 3) |
| #define ABOX_UAIF3 (CLK_ABOX_BASE + 4) |
| #define ABOX_UAIF4 (CLK_ABOX_BASE + 5) |
| #define ABOX_CPU_ACLK (CLK_ABOX_BASE + 6) |
| #define ABOX_DMIC (CLK_ABOX_BASE + 7) |
| #define GATE_ABOX_TOP (CLK_ABOX_BASE + 8) |
| #define GATE_ABOX_CMU_ABOX (CLK_ABOX_BASE + 9) |
| #define GATE_BTM_ABOX (CLK_ABOX_BASE + 10) |
| #define GATE_GPIO_ABOX (CLK_ABOX_BASE + 11) |
| #define GATE_PMU_ABOX (CLK_ABOX_BASE + 12) |
| #define GATE_BCM_ABOX (CLK_ABOX_BASE + 13) |
| #define GATE_SMMU_ABOX (CLK_ABOX_BASE + 14) |
| #define GATE_SYSREG_ABOX (CLK_ABOX_BASE + 15) |
| #define GATE_WDT_ABOXCPU (CLK_ABOX_BASE + 16) |
| #define DOUT_CLK_ABOX_AUDIF (CLK_ABOX_BASE + 17) |
| #define DOUT_CLK_ABOX_DSIF (CLK_ABOX_BASE + 18) |
| #define DOUT_CLK_ABOX_DMIC (CLK_ABOX_BASE + 19) |
| #define DOUT_CLK_ABOX_UAIF0 (CLK_ABOX_BASE + 20) |
| #define DOUT_CLK_ABOX_UAIF1 (CLK_ABOX_BASE + 21) |
| #define DOUT_CLK_ABOX_UAIF2 (CLK_ABOX_BASE + 22) |
| #define DOUT_CLK_ABOX_UAIF3 (CLK_ABOX_BASE + 23) |
| #define DOUT_CLK_ABOX_UAIF4 (CLK_ABOX_BASE + 24) |
| |
| /* NUMBER FOR FSYS0 DRIVER STARTS FROM 700 */ |
| #define CLK_FSYS0_BASE (700) |
| #define MMC_EMBD (CLK_FSYS0_BASE + 0) |
| #define DPGTC (CLK_FSYS0_BASE + 1) |
| #define UFS_EMBD (CLK_FSYS0_BASE + 2) |
| #define USBDRD30 (CLK_FSYS0_BASE + 3) |
| #define GATE_DP_LINK (CLK_FSYS0_BASE + 4) |
| #define GATE_FSYS0_CMU_FSYS0 (CLK_FSYS0_BASE + 5) |
| #define GATE_GPIO_FSYS0 (CLK_FSYS0_BASE + 6) |
| #define GATE_MMC_EMBD (CLK_FSYS0_BASE + 7) |
| #define GATE_BTM_FSYS0 (CLK_FSYS0_BASE + 8) |
| #define GATE_PMU_FSYS0 (CLK_FSYS0_BASE + 9) |
| #define GATE_BCM_FSYS0 (CLK_FSYS0_BASE + 10) |
| #define GATE_SYSREG_FSYS0 (CLK_FSYS0_BASE + 11) |
| #define GATE_UFS_EMBD (CLK_FSYS0_BASE + 12) |
| #define GATE_UFS_EMBD_FMP (CLK_FSYS0_BASE + 13) |
| #define GATE_USBTV_USB30DRD_LINK (CLK_FSYS0_BASE + 14) |
| #define GATE_USBTV_USBTV_HOST (CLK_FSYS0_BASE + 15) |
| #define GATE_ETR_MIU_PCLK (CLK_FSYS0_BASE + 16) |
| #define GATE_ETR_MIU_ACLK (CLK_FSYS0_BASE + 17) |
| #define UMUX_CLKCMU_FSYS0_BUS (CLK_FSYS0_BASE + 18) |
| #define UMUX_CLKCMU_FSYS0_DPGTC (CLK_FSYS0_BASE + 19) |
| #define UMUX_CLKCMU_FSYS0_UFS_EMBD (CLK_FSYS0_BASE + 20) |
| #define UMUX_CLKCMU_FSYS0_MMC_EMBD (CLK_FSYS0_BASE + 21) |
| #define UMUX_CLKCMU_FSYS0_USBDRD30 (CLK_FSYS0_BASE + 22) |
| #define GATE_MMC_CARD1 (CLK_FSYS0_BASE + 23) |
| |
| /* NUMBER FOR FSYS1 DRIVER STARTS FROM 750 */ |
| #define CLK_FSYS1_BASE (750) |
| #define MMC_CARD (CLK_FSYS1_BASE + 0) |
| #define UFS_CARD (CLK_FSYS1_BASE + 1) |
| #define PCIE (CLK_FSYS1_BASE + 2) |
| #define GATE_ADM_AHB_SSS (CLK_FSYS1_BASE + 3) |
| #define GATE_MMC_CARD (CLK_FSYS1_BASE + 4) |
| #define GATE_PCIE_PCIE0_MSTR (CLK_FSYS1_BASE + 5) |
| #define GATE_PCIE_PCIE_PCS (CLK_FSYS1_BASE + 6) |
| #define GATE_PCIE_PCIE_PHY (CLK_FSYS1_BASE + 7) |
| #define GATE_PCIE_PCIE0_DBI (CLK_FSYS1_BASE + 8) |
| #define GATE_PCIE_PCIE0_APB (CLK_FSYS1_BASE + 9) |
| #define GATE_PCIE_PCIE1_MSTR (CLK_FSYS1_BASE + 10) |
| #define GATE_PCIE_PCIE1_DBI (CLK_FSYS1_BASE + 11) |
| #define GATE_PCIE_PCIE1_APB (CLK_FSYS1_BASE + 12) |
| #define GATE_PCIE_PCIE_SOCPLL (CLK_FSYS1_BASE + 13) |
| #define GATE_FSYS1_CMU_FSYS1 (CLK_FSYS1_BASE + 14) |
| #define GATE_GPIO_FSYS1 (CLK_FSYS1_BASE + 15) |
| #define GATE_BTM_FSYS1 (CLK_FSYS1_BASE + 16) |
| #define GATE_PMU_FSYS1 (CLK_FSYS1_BASE + 17) |
| #define GATE_BCM_FSYS1 (CLK_FSYS1_BASE + 18) |
| #define GATE_RTIC (CLK_FSYS1_BASE + 19) |
| #define GATE_SSS (CLK_FSYS1_BASE + 20) |
| #define GATE_SYSREG_FSYS1 (CLK_FSYS1_BASE + 21) |
| #define GATE_TOE_WIFI0 (CLK_FSYS1_BASE + 22) |
| #define GATE_TOE_WIFI1 (CLK_FSYS1_BASE + 23) |
| #define GATE_UFS_CARD (CLK_FSYS1_BASE + 24) |
| #define GATE_UFS_CARD_FMP (CLK_FSYS1_BASE + 25) |
| #define UMUX_CLKCMU_FSYS1_BUS (CLK_FSYS1_BASE + 26) |
| #define UMUX_CLKCMU_FSYS1_MMC_CARD (CLK_FSYS1_BASE + 27) |
| #define UMUX_CLKCMU_FSYS1_UFS_CARD (CLK_FSYS1_BASE + 28) |
| #define UMUX_CLKCMU_FSYS1_PCIE (CLK_FSYS1_BASE + 29) |
| #define GATE_PCIE0_QCH_PCIE0_MSTR (GATE_PCIE_PCIE0_MSTR) |
| #define GATE_PCIE0_QCH_PCIE0_PHY (GATE_PCIE_PCIE_PHY) |
| #define GATE_PCIE0_QCH_PCIE0_DBI (GATE_PCIE_PCIE0_DBI) |
| #define GATE_PCIE0_QCH_PCIE0_APB (GATE_PCIE_PCIE0_APB) |
| #define GATE_PCIE0_QCH_PCIE0_PCS (GATE_PCIE_PCIE_PCS) |
| #define GATE_PCIE0_QCH_PCIE0_SOCPLL (GATE_PCIE_PCIE_SOCPLL) |
| #define GATE_PCIE1_QCH_PCIE1_MSTR (GATE_PCIE_PCIE1_MSTR) |
| #define GATE_PCIE1_QCH_PCIE1_DBI (GATE_PCIE_PCIE1_DBI) |
| #define GATE_PCIE1_QCH_PCIE1_APB (GATE_PCIE_PCIE1_APB) |
| #define GATE_PCIE1_QCH_PCIE1_PCS (CLK_FSYS1_BASE + 30) |
| #define GATE_PCIE1_QCH_PCIE1_PHY (CLK_FSYS1_BASE + 31) |
| #define GATE_PCIE1_QCH_PCIE1_OSCPLL (CLK_FSYS1_BASE + 32) |
| |
| /* NUMBER FOR G3D DRIVER STARTS FROM 800 */ |
| #define CLK_G3D_BASE (800) |
| #define GATE_AGPU_G3D (CLK_G3D_BASE + 0) |
| #define GATE_BUSIF_HPMG3D (CLK_G3D_BASE + 1) |
| #define GATE_G3D_CMU_G3D (CLK_G3D_BASE + 2) |
| #define GATE_PMU_G3D (CLK_G3D_BASE + 3) |
| #define GATE_SYSREG_G3D (CLK_G3D_BASE + 4) |
| |
| /* NUMBER FOR DPU0 DRIVER STARTS FROM 850 */ |
| #define CLK_DPU0_BASE (850) |
| #define GATE_DECON0 (CLK_DPU0_BASE + 0) |
| #define GATE_DPP_DPP_G0 (CLK_DPU0_BASE + 1) |
| #define GATE_DPP_DPP_G1 (CLK_DPU0_BASE + 2) |
| #define GATE_DPP_DPP_VGR (CLK_DPU0_BASE + 3) |
| #define GATE_DPU_DMA (CLK_DPU0_BASE + 4) |
| #define GATE_DPU_WB_MUX (CLK_DPU0_BASE + 5) |
| #define GATE_BTM_DPUD0 (CLK_DPU0_BASE + 6) |
| #define GATE_BTM_DPUD1 (CLK_DPU0_BASE + 7) |
| #define GATE_BTM_DPUD2 (CLK_DPU0_BASE + 8) |
| #define GATE_DPU0_CMU_DPU0 (CLK_DPU0_BASE + 9) |
| #define GATE_PMU_DPU0 (CLK_DPU0_BASE + 10) |
| #define GATE_BCM_DPUD0 (CLK_DPU0_BASE + 11) |
| #define GATE_BCM_DPUD1 (CLK_DPU0_BASE + 12) |
| #define GATE_BCM_DPUD2 (CLK_DPU0_BASE + 13) |
| #define GATE_SYSMMU_DPUD0 (CLK_DPU0_BASE + 14) |
| #define GATE_SYSMMU_DPUD1 (CLK_DPU0_BASE + 15) |
| #define GATE_SYSMMU_DPUD2 (CLK_DPU0_BASE + 16) |
| #define GATE_SYSREG_DPU0 (CLK_DPU0_BASE + 17) |
| #define UMUX_CLKCMU_DPU_BUS (CLK_DPU0_BASE + 18) |
| |
| /* NUMBER FOR DPU1 DRIVER STARTS FROM 900 */ |
| #define CLK_DPU1_BASE (900) |
| #define DECON2 (CLK_DPU1_BASE + 0) |
| #define GATE_DECON1 (CLK_DPU1_BASE + 1) |
| #define GATE_DECON2_ACLK (CLK_DPU1_BASE + 2) |
| #define GATE_DECON2_VCLK (CLK_DPU1_BASE + 3) |
| #define GATE_DPU1_CMU_DPU1 (CLK_DPU1_BASE + 4) |
| #define GATE_PMU_DPU1 (CLK_DPU1_BASE + 5) |
| #define GATE_SYSREG_DPU1 (CLK_DPU1_BASE + 6) |
| #define UMUX_CLKCMU_DPU1_BUSD (CLK_DPU1_BASE + 7) |
| #define UMUX_CLKCMU_DPU1_BUSP (CLK_DPU1_BASE + 8) |
| |
| /* NUMBER FOR CLKOUT PORT STARTS FROM 920 */ |
| #define CLK_CLKOUT_BASE (920) |
| #define OSCCLK_NFC (CLK_CLKOUT_BASE + 0) |
| #define OSCCLK_AUD (CLK_CLKOUT_BASE + 1) |
| |
| /* NUMBER FOR VTS DRIVER STARTS FROM 940 */ |
| #define CLK_VTS_BASE (940) |
| #define DMIC (CLK_VTS_BASE + 0) |
| #define GATE_CMU_VTS_CMUREF (CLK_VTS_BASE + 1) |
| #define GATE_DMIC_AHB (CLK_VTS_BASE + 2) |
| #define GATE_DMIC_AHB_HCLK (CLK_VTS_BASE + 3) |
| #define GATE_DMIC_IF (CLK_VTS_BASE + 4) |
| #define GATE_DMIC_IF_DMIC_CLK (CLK_VTS_BASE + 5) |
| #define GATE_GPIO_VTS (CLK_VTS_BASE + 6) |
| #define GATE_MAILBOX_VTS2AP (CLK_VTS_BASE + 7) |
| #define GATE_SYSREG_VTS (CLK_VTS_BASE + 8) |
| #define GATE_VTS_CPU (CLK_VTS_BASE + 9) |
| #define GATE_VTS_SYS (CLK_VTS_BASE + 10) |
| #define GATE_VTS_SYS_DMIC (CLK_VTS_BASE + 11) |
| #define GATE_VTS_CMU_VTS (CLK_VTS_BASE + 12) |
| #define GATE_WDT_VTS (CLK_VTS_BASE + 13) |
| #define DOUT_CLK_VTS_DMICIF (CLK_VTS_BASE + 14) |
| #define DOUT_CLK_VTS_DMIC (CLK_VTS_BASE + 15) |
| #define DOUT_CLK_VTS_DMIC_DIV2 (CLK_VTS_BASE + 16) |
| #define GATE_OSC_VTS (CLK_VTS_BASE + 17) |
| |
| /* NUMBER FOR APM DRIVER STARTS FROM 980 */ |
| #define CLK_APM_BASE (980) |
| #define GATE_APM_SYS (CLK_APM_BASE + 0) |
| #define GATE_APM_CPU (CLK_APM_BASE + 1) |
| #define GATE_APM_CMU_APM (CLK_APM_BASE + 2) |
| #define GATE_APM_OSCCLK (CLK_APM_BASE + 3) |
| #define GATE_MAILBOX_APM2AP (CLK_APM_BASE + 4) |
| #define GATE_MAILBOX_APM2CP (CLK_APM_BASE + 5) |
| #define GATE_MAILBOX_APM2GNSS (CLK_APM_BASE + 6) |
| #define GATE_SCAN2AXI (CLK_APM_BASE + 7) |
| #define GATE_SYSREG_APM (CLK_APM_BASE + 8) |
| #define GATE_WDT_APM (CLK_APM_BASE + 9) |
| #define UMUX_CLKCMU_APM_BUS (CLK_APM_BASE + 10) |
| |
| /* NUMBER FOR BUSC DRIVER STARTS FROM 1000 */ |
| #define CLK_BUSC_BASE (1000) |
| #define GATE_GNSSMBOX (CLK_BUSC_BASE + 0) |
| #define GATE_HSI2CDF (CLK_BUSC_BASE + 1) |
| #define GATE_MBOX (CLK_BUSC_BASE + 2) |
| #define GATE_PDMA0 (CLK_BUSC_BASE + 3) |
| #define GATE_SECMBOX (CLK_BUSC_BASE + 4) |
| #define GATE_SPDMA (CLK_BUSC_BASE + 5) |
| #define GATE_SPEEDY (CLK_BUSC_BASE + 6) |
| #define GATE_SPEEDY_BATCHER_WRAP_BATCHER_SPEEDY (CLK_BUSC_BASE + 7) |
| #define GATE_SPEEDY_BATCHER_WRAP_BATCHER_CP (CLK_BUSC_BASE + 8) |
| #define GATE_SPEEDY_BATCHER_WRAP_BATCHER_AP (CLK_BUSC_BASE + 9) |
| #define GATE_ADCIF_BUSC_S0 (CLK_BUSC_BASE + 10) |
| #define GATE_ADCIF_BUSC_S1 (CLK_BUSC_BASE + 11) |
| #define GATE_BUSC_CMU_BUSC (CLK_BUSC_BASE + 12) |
| #define GATE_PMU_BUSC (CLK_BUSC_BASE + 12) |
| #define GATE_BUSIF_CMUTOPC (CLK_BUSC_BASE + 13) |
| #define GATE_GPIO_BUSC (CLK_BUSC_BASE + 14) |
| #define GATE_SYSREG_BUSC (CLK_BUSC_BASE + 15) |
| #define UMUX_CLKCMU_BUSC_BUS (CLK_BUSC_BASE + 16) |
| #define UMUX_CLKCMU_BUSC_BUSPHSI2C (CLK_BUSC_BASE + 17) |
| |
| /* NUMBER FOR BUS1 DRIVER STARTS FROM 1080 */ |
| #define CLK_BUS1_BASE (1080) |
| #define GATE_BUS1_CMU_BUS1 (CLK_BUS1_BASE + 0) |
| #define GATE_PMU_BUS1 (CLK_BUS1_BASE + 1) |
| #define GATE_SYSREG_BUS1 (CLK_BUS1_BASE + 2) |
| #define UMUX_CLKCMU_BUS1_BUS (CLK_BUS1_BASE + 3) |
| |
| /* NUMBER FOR DSP DRIVER STARTS FROM 1100 */ |
| #define CLK_DSP_BASE (1100) |
| #define GATE_BTM_SCORE (CLK_DSP_BASE + 0) |
| #define GATE_DSP_CMU_DSP (CLK_DSP_BASE + 1) |
| #define GATE_PMU_DSP (CLK_DSP_BASE + 2) |
| #define GATE_BCM_SCORE (CLK_DSP_BASE + 3) |
| #define GATE_SCORE (CLK_DSP_BASE + 4) |
| #define GATE_SMMU_SCORE (CLK_DSP_BASE + 5) |
| #define GATE_SYSREG_DSP (CLK_DSP_BASE + 6) |
| #define UMUX_CLKCMU_DSP_BUS (CLK_DSP_BASE + 7) |
| |
| /* NUMBER OF IVA DRIVER STARTS FROM 1120 */ |
| #define CLK_IVA_BASE (1120) |
| #define GATE_IVA (CLK_IVA_BASE + 0) |
| #define GATE_IVA_INTMEM (CLK_IVA_BASE + 1) |
| #define GATE_BTM_IVA (CLK_IVA_BASE + 2) |
| #define GATE_IVA_CMU_IVA (CLK_IVA_BASE + 3) |
| #define GATE_PMU_IVA (CLK_IVA_BASE + 4) |
| #define GATE_BCM_IVA (CLK_IVA_BASE + 5) |
| #define GATE_SMMU_IVA (CLK_IVA_BASE + 6) |
| #define GATE_SYSREG_IVA (CLK_IVA_BASE + 7) |
| #define UMUX_CLKCMU_IVA_BUS (CLK_IVA_BASE + 8) |
| |
| /* NUMBER OF VPU DRIVER STARTS FROM 1140 */ |
| #define CLK_VPU_BASE (1140) |
| #define GATE_VPU (CLK_VPU_BASE + 0) |
| #define GATE_BTM_VPU (CLK_VPU_BASE + 1) |
| #define GATE_VPU_CMU_VPU (CLK_VPU_BASE + 2) |
| #define GATE_PMU_VPU (CLK_VPU_BASE + 3) |
| #define GATE_BCM_VPU (CLK_VPU_BASE + 4) |
| #define GATE_SMMU_VPU (CLK_VPU_BASE + 5) |
| #define GATE_SYSREG_VPU (CLK_VPU_BASE + 6) |
| #define UMUX_CLKCMU_VPU_BUS (CLK_VPU_BASE + 7) |
| |
| /* NUMBER OF SRDZ DRIVER STARTS FROM 1160 */ |
| #define CLK_SRDZ_BASE (1160) |
| #define GATE_SRDZ (CLK_SRDZ_BASE + 0) |
| #define GATE_BTM_SRDZ (CLK_SRDZ_BASE + 1) |
| #define GATE_PMU_SRDZ (CLK_SRDZ_BASE + 2) |
| #define GATE_BCM_SRDZ (CLK_SRDZ_BASE + 3) |
| #define GATE_SMMU_SRDZ (CLK_SRDZ_BASE + 4) |
| #define GATE_SRDZ_CMU_SRDZ (CLK_SRDZ_BASE + 5) |
| #define GATE_SYSREG_SRDZ (CLK_SRDZ_BASE + 6) |
| #define UMUX_CLKCMU_SRDZ_BUS (CLK_SRDZ_BASE + 7) |
| #define UMUX_CLKCMU_SRDZ_IMGD (CLK_SRDZ_BASE + 8) |
| |
| /* NUMBER FOR SYSMMU DRIVER STARTS FROM 1180 */ |
| #define CLK_SYSMMU_BASE (1180) |
| |
| /* NUMBER OF DVFS DRIVER STARTS FROM 1200 */ |
| #define CLK_DVFS_BASE (1200) |
| #define DVFS_INT (CLK_DVFS_BASE + 0) |
| #define DVFS_MIF (CLK_DVFS_BASE + 1) |
| #define DVFS_G3D (CLK_DVFS_BASE + 2) |
| #define DVFS_BIG (CLK_DVFS_BASE + 3) |
| #define DVFS_LITTLE (CLK_DVFS_BASE + 4) |
| #define DFS_ABOX (CLK_DVFS_BASE + 5) |
| |
| /* must be greater than maximal clock id */ |
| #define CLK_NR_CLKS (1205 + 1) |
| |
| #define ACPM_DVFS_MIF (0x0B040000) |
| #define ACPM_DVFS_INT (0x0B040001) |
| #define ACPM_DVFS_CPUCL0 (0x0B040002) |
| #define ACPM_DVFS_CPUCL1 (0x0B040003) |
| #define ACPM_DVFS_G3D (0x0B040004) |
| #define ACPM_DVFS_INTCAM (0x0B040005) |
| #define ACPM_DVFS_CAM (0x0B040006) |
| #define ACPM_DVFS_DISP (0x0B040007) |
| #define ACPM_DVFS_G3DM (0x0B040008) |
| #define ACPM_DVFS_CP (0x0B040009) |
| |
| #endif /* _DT_BINDINGS_CLOCK_EMULATOR_8895_H */ |