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LeafOS / LeafOS-Devices / android_kernel_samsung_gta4xl / fbef103fad5009827965b10aedbecb1786904f4d / . / arch / arm / mach-davinci / include / mach / mux.h
blob: 631655e68ae046601aabcad315d622e9d83c8331 [file] [log] [blame]
Vladimir Barinov83f53222007-07-10 13:10:04 +0100[diff] [blame]1/*
Kevin Hilman5526b3f2009-04-14 09:50:37 -0500[diff] [blame]2 * Table of the DAVINCI register configurations for the PINMUX combinations
Vladimir Barinov83f53222007-07-10 13:10:04 +0100[diff] [blame]3 *
4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
5 *
Kevin Hilman5526b3f2009-04-14 09:50:37 -0500[diff] [blame]6 * Based on linux/include/asm-arm/arch-omap/mux.h:
7 * Copyright (C) 2003 - 2005 Nokia Corporation
8 *
9 * Written by Tony Lindgren
10 *
Vladimir Barinov83f53222007-07-10 13:10:04 +0100[diff] [blame]11 * 2007 (c) MontaVista Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
Kevin Hilman5526b3f2009-04-14 09:50:37 -0500[diff] [blame]15 *
16 * Copyright (C) 2008 Texas Instruments.
Vladimir Barinov83f53222007-07-10 13:10:04 +0100[diff] [blame]17 */
Vladimir Barinov83f53222007-07-10 13:10:04 +0100[diff] [blame]18
Kevin Hilman5526b3f2009-04-14 09:50:37 -0500[diff] [blame]19#ifndef __INC_MACH_MUX_H
20#define __INC_MACH_MUX_H
Vladimir Barinov83f53222007-07-10 13:10:04 +0100[diff] [blame]21
Kevin Hilman5526b3f2009-04-14 09:50:37 -0500[diff] [blame]22struct mux_config {
23 const char *name;
24 const char *mux_reg_name;
25 const unsigned char mux_reg;
26 const unsigned char mask_offset;
27 const unsigned char mask;
28 const unsigned char mode;
29 bool debug;
30};
Vladimir Barinov83f53222007-07-10 13:10:04 +0100[diff] [blame]31
Kevin Hilman5526b3f2009-04-14 09:50:37 -0500[diff] [blame]32enum davinci_dm644x_index {
33 /* ATA and HDDIR functions */
34 DM644X_HDIREN,
35 DM644X_ATAEN,
36 DM644X_ATAEN_DISABLE,
37
38 /* HPI functions */
39 DM644X_HPIEN_DISABLE,
40
41 /* AEAW functions */
42 DM644X_AEAW,
Andrey Porodkoc16fe262009-11-13 19:16:51 +0500[diff] [blame]43 DM644X_AEAW0,
44 DM644X_AEAW1,
45 DM644X_AEAW2,
46 DM644X_AEAW3,
47 DM644X_AEAW4,
Kevin Hilman5526b3f2009-04-14 09:50:37 -0500[diff] [blame]48
49 /* Memory Stick */
50 DM644X_MSTK,
51
52 /* I2C */
53 DM644X_I2C,
54
55 /* ASP function */
56 DM644X_MCBSP,
57
58 /* UART1 */
59 DM644X_UART1,
60
61 /* UART2 */
62 DM644X_UART2,
63
64 /* PWM0 */
65 DM644X_PWM0,
66
67 /* PWM1 */
68 DM644X_PWM1,
69
70 /* PWM2 */
71 DM644X_PWM2,
72
73 /* VLYNQ function */
74 DM644X_VLYNQEN,
75 DM644X_VLSCREN,
76 DM644X_VLYNQWD,
77
78 /* EMAC and MDIO function */
79 DM644X_EMACEN,
80
81 /* GPIO3V[0:16] pins */
82 DM644X_GPIO3V,
83
84 /* GPIO pins */
85 DM644X_GPIO0,
86 DM644X_GPIO3,
87 DM644X_GPIO43_44,
88 DM644X_GPIO46_47,
89
90 /* VPBE */
91 DM644X_RGB666,
92
93 /* LCD */
94 DM644X_LOEEN,
95 DM644X_LFLDEN,
96};
97
98enum davinci_dm646x_index {
99 /* ATA function */
100 DM646X_ATAEN,
101
102 /* AUDIO Clock */
103 DM646X_AUDCK1,
104 DM646X_AUDCK0,
105
106 /* CRGEN Control */
107 DM646X_CRGMUX,
108
109 /* VPIF Control */
110 DM646X_STSOMUX_DISABLE,
111 DM646X_STSIMUX_DISABLE,
112 DM646X_PTSOMUX_DISABLE,
113 DM646X_PTSIMUX_DISABLE,
114
115 /* TSIF Control */
116 DM646X_STSOMUX,
117 DM646X_STSIMUX,
118 DM646X_PTSOMUX_PARALLEL,
119 DM646X_PTSIMUX_PARALLEL,
120 DM646X_PTSOMUX_SERIAL,
121 DM646X_PTSIMUX_SERIAL,
122};
123
124enum davinci_dm355_index {
125 /* MMC/SD 0 */
126 DM355_MMCSD0,
127
128 /* MMC/SD 1 */
129 DM355_SD1_CLK,
130 DM355_SD1_CMD,
131 DM355_SD1_DATA3,
132 DM355_SD1_DATA2,
133 DM355_SD1_DATA1,
134 DM355_SD1_DATA0,
135
136 /* I2C */
137 DM355_I2C_SDA,
138 DM355_I2C_SCL,
139
140 /* ASP0 function */
141 DM355_MCBSP0_BDX,
142 DM355_MCBSP0_X,
143 DM355_MCBSP0_BFSX,
144 DM355_MCBSP0_BDR,
145 DM355_MCBSP0_R,
146 DM355_MCBSP0_BFSR,
147
148 /* SPI0 */
149 DM355_SPI0_SDI,
150 DM355_SPI0_SDENA0,
151 DM355_SPI0_SDENA1,
152
153 /* IRQ muxing */
154 DM355_INT_EDMA_CC,
155 DM355_INT_EDMA_TC0_ERR,
156 DM355_INT_EDMA_TC1_ERR,
157
158 /* EDMA event muxing */
159 DM355_EVT8_ASP1_TX,
160 DM355_EVT9_ASP1_RX,
161 DM355_EVT26_MMC0_RX,
Sandeep Paulraj1aebb502009-08-21 12:38:11 -0400[diff] [blame]162
163 /* Video Out */
164 DM355_VOUT_FIELD,
165 DM355_VOUT_FIELD_G70,
166 DM355_VOUT_HVSYNC,
167 DM355_VOUT_COUTL_EN,
168 DM355_VOUT_COUTH_EN,
Muralidharan Karicheri51e68e22009-09-16 12:02:50 -0400[diff] [blame]169
170 /* Video In Pin Mux */
171 DM355_VIN_PCLK,
172 DM355_VIN_CAM_WEN,
173 DM355_VIN_CAM_VD,
174 DM355_VIN_CAM_HD,
175 DM355_VIN_YIN_EN,
176 DM355_VIN_CINL_EN,
177 DM355_VIN_CINH_EN,
Kevin Hilman5526b3f2009-04-14 09:50:37 -0500[diff] [blame]178};
179
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400[diff] [blame]180enum davinci_dm365_index {
181 /* MMC/SD 0 */
182 DM365_MMCSD0,
183
184 /* MMC/SD 1 */
185 DM365_SD1_CLK,
186 DM365_SD1_CMD,
187 DM365_SD1_DATA3,
188 DM365_SD1_DATA2,
189 DM365_SD1_DATA1,
190 DM365_SD1_DATA0,
191
192 /* I2C */
193 DM365_I2C_SDA,
194 DM365_I2C_SCL,
195
196 /* AEMIF */
Thomas Koeller77352272010-05-11 17:06:49 +0200[diff] [blame]197 DM365_AEMIF_AR_A14,
198 DM365_AEMIF_AR_BA0,
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400[diff] [blame]199 DM365_AEMIF_A3,
200 DM365_AEMIF_A7,
201 DM365_AEMIF_D15_8,
202 DM365_AEMIF_CE0,
Thomas Koeller77352272010-05-11 17:06:49 +0200[diff] [blame]203 DM365_AEMIF_CE1,
204 DM365_AEMIF_WE_OE,
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400[diff] [blame]205
206 /* ASP0 function */
207 DM365_MCBSP0_BDX,
208 DM365_MCBSP0_X,
209 DM365_MCBSP0_BFSX,
210 DM365_MCBSP0_BDR,
211 DM365_MCBSP0_R,
212 DM365_MCBSP0_BFSR,
213
214 /* SPI0 */
215 DM365_SPI0_SCLK,
216 DM365_SPI0_SDI,
217 DM365_SPI0_SDO,
218 DM365_SPI0_SDENA0,
219 DM365_SPI0_SDENA1,
220
221 /* UART */
222 DM365_UART0_RXD,
223 DM365_UART0_TXD,
224 DM365_UART1_RXD,
225 DM365_UART1_TXD,
226 DM365_UART1_RTS,
227 DM365_UART1_CTS,
228
229 /* EMAC */
230 DM365_EMAC_TX_EN,
231 DM365_EMAC_TX_CLK,
232 DM365_EMAC_COL,
233 DM365_EMAC_TXD3,
234 DM365_EMAC_TXD2,
235 DM365_EMAC_TXD1,
236 DM365_EMAC_TXD0,
237 DM365_EMAC_RXD3,
238 DM365_EMAC_RXD2,
239 DM365_EMAC_RXD1,
240 DM365_EMAC_RXD0,
241 DM365_EMAC_RX_CLK,
242 DM365_EMAC_RX_DV,
243 DM365_EMAC_RX_ER,
244 DM365_EMAC_CRS,
245 DM365_EMAC_MDIO,
246 DM365_EMAC_MDCLK,
247
Miguel Aguilar990c09d2009-10-13 13:57:07 -0600[diff] [blame]248 /* Key Scan */
249 DM365_KEYSCAN,
Sandeep Paulraj9f513152009-06-20 12:11:09 -0400[diff] [blame]250
Sandeep Paulrajaf5dbae2009-06-24 12:22:28 -0400[diff] [blame]251 /* PWM */
252 DM365_PWM0,
253 DM365_PWM0_G23,
254 DM365_PWM1,
255 DM365_PWM1_G25,
256 DM365_PWM2_G87,
257 DM365_PWM2_G88,
258 DM365_PWM2_G89,
259 DM365_PWM2_G90,
260 DM365_PWM3_G80,
261 DM365_PWM3_G81,
262 DM365_PWM3_G85,
263 DM365_PWM3_G86,
264
265 /* SPI1 */
266 DM365_SPI1_SCLK,
267 DM365_SPI1_SDO,
268 DM365_SPI1_SDI,
269 DM365_SPI1_SDENA0,
270 DM365_SPI1_SDENA1,
271
272 /* SPI2 */
273 DM365_SPI2_SCLK,
274 DM365_SPI2_SDO,
275 DM365_SPI2_SDI,
276 DM365_SPI2_SDENA0,
277 DM365_SPI2_SDENA1,
278
279 /* SPI3 */
280 DM365_SPI3_SCLK,
281 DM365_SPI3_SDO,
282 DM365_SPI3_SDI,
283 DM365_SPI3_SDENA0,
284 DM365_SPI3_SDENA1,
285
286 /* SPI4 */
287 DM365_SPI4_SCLK,
288 DM365_SPI4_SDO,
289 DM365_SPI4_SDI,
290 DM365_SPI4_SDENA0,
291 DM365_SPI4_SDENA1,
292
Thomas Koeller0efe2b72010-05-11 17:06:48 +0200[diff] [blame]293 /* Clock */
294 DM365_CLKOUT0,
295 DM365_CLKOUT1,
296 DM365_CLKOUT2,
297
Sandeep Paulrajaf5dbae2009-06-24 12:22:28 -0400[diff] [blame]298 /* GPIO */
299 DM365_GPIO20,
Thomas Koeller2168e762010-05-11 17:06:47 +0200[diff] [blame]300 DM365_GPIO30,
301 DM365_GPIO31,
302 DM365_GPIO32,
Sandeep Paulrajaf5dbae2009-06-24 12:22:28 -0400[diff] [blame]303 DM365_GPIO33,
304 DM365_GPIO40,
Thomas Koellerce100662010-04-08 17:01:56 +0200[diff] [blame]305 DM365_GPIO64_57,
Sandeep Paulrajaf5dbae2009-06-24 12:22:28 -0400[diff] [blame]306
307 /* Video */
308 DM365_VOUT_FIELD,
309 DM365_VOUT_FIELD_G81,
310 DM365_VOUT_HVSYNC,
311 DM365_VOUT_COUTL_EN,
312 DM365_VOUT_COUTH_EN,
313 DM365_VIN_CAM_WEN,
314 DM365_VIN_CAM_VD,
315 DM365_VIN_CAM_HD,
Sandeep Paulraj866d2862009-08-03 13:58:24 -0400[diff] [blame]316 DM365_VIN_YIN4_7_EN,
317 DM365_VIN_YIN0_3_EN,
Sandeep Paulrajaf5dbae2009-06-24 12:22:28 -0400[diff] [blame]318
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400[diff] [blame]319 /* IRQ muxing */
320 DM365_INT_EDMA_CC,
321 DM365_INT_EDMA_TC0_ERR,
322 DM365_INT_EDMA_TC1_ERR,
Sandeep Paulraj9f513152009-06-20 12:11:09 -0400[diff] [blame]323 DM365_INT_EDMA_TC2_ERR,
324 DM365_INT_EDMA_TC3_ERR,
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400[diff] [blame]325 DM365_INT_PRTCSS,
326 DM365_INT_EMAC_RXTHRESH,
327 DM365_INT_EMAC_RXPULSE,
328 DM365_INT_EMAC_TXPULSE,
329 DM365_INT_EMAC_MISCPULSE,
Sandeep Paulraj0c30e0d2009-08-18 11:08:27 -0400[diff] [blame]330 DM365_INT_IMX0_ENABLE,
331 DM365_INT_IMX0_DISABLE,
332 DM365_INT_HDVICP_ENABLE,
333 DM365_INT_HDVICP_DISABLE,
334 DM365_INT_IMX1_ENABLE,
335 DM365_INT_IMX1_DISABLE,
336 DM365_INT_NSF_ENABLE,
337 DM365_INT_NSF_DISABLE,
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400[diff] [blame]338
339 /* EDMA event muxing */
340 DM365_EVT2_ASP_TX,
341 DM365_EVT3_ASP_RX,
Miguel Aguilare89861e2010-01-21 11:41:51 -0600[diff] [blame]342 DM365_EVT2_VC_TX,
343 DM365_EVT3_VC_RX,
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400[diff] [blame]344 DM365_EVT26_MMC0_RX,
345};
346
Mark A. Greer55c79a42009-06-03 18:36:54 -0700[diff] [blame]347enum da830_index {
348 DA830_GPIO7_14,
349 DA830_RTCK,
350 DA830_GPIO7_15,
351 DA830_EMU_0,
352 DA830_EMB_SDCKE,
353 DA830_EMB_CLK_GLUE,
354 DA830_EMB_CLK,
355 DA830_NEMB_CS_0,
356 DA830_NEMB_CAS,
357 DA830_NEMB_RAS,
358 DA830_NEMB_WE,
359 DA830_EMB_BA_1,
360 DA830_EMB_BA_0,
361 DA830_EMB_A_0,
362 DA830_EMB_A_1,
363 DA830_EMB_A_2,
364 DA830_EMB_A_3,
365 DA830_EMB_A_4,
366 DA830_EMB_A_5,
367 DA830_GPIO7_0,
368 DA830_GPIO7_1,
369 DA830_GPIO7_2,
370 DA830_GPIO7_3,
371 DA830_GPIO7_4,
372 DA830_GPIO7_5,
373 DA830_GPIO7_6,
374 DA830_GPIO7_7,
375 DA830_EMB_A_6,
376 DA830_EMB_A_7,
377 DA830_EMB_A_8,
378 DA830_EMB_A_9,
379 DA830_EMB_A_10,
380 DA830_EMB_A_11,
381 DA830_EMB_A_12,
382 DA830_EMB_D_31,
383 DA830_GPIO7_8,
384 DA830_GPIO7_9,
385 DA830_GPIO7_10,
386 DA830_GPIO7_11,
387 DA830_GPIO7_12,
388 DA830_GPIO7_13,
389 DA830_GPIO3_13,
390 DA830_EMB_D_30,
391 DA830_EMB_D_29,
392 DA830_EMB_D_28,
393 DA830_EMB_D_27,
394 DA830_EMB_D_26,
395 DA830_EMB_D_25,
396 DA830_EMB_D_24,
397 DA830_EMB_D_23,
398 DA830_EMB_D_22,
399 DA830_EMB_D_21,
400 DA830_EMB_D_20,
401 DA830_EMB_D_19,
402 DA830_EMB_D_18,
403 DA830_EMB_D_17,
404 DA830_EMB_D_16,
405 DA830_NEMB_WE_DQM_3,
406 DA830_NEMB_WE_DQM_2,
407 DA830_EMB_D_0,
408 DA830_EMB_D_1,
409 DA830_EMB_D_2,
410 DA830_EMB_D_3,
411 DA830_EMB_D_4,
412 DA830_EMB_D_5,
413 DA830_EMB_D_6,
414 DA830_GPIO6_0,
415 DA830_GPIO6_1,
416 DA830_GPIO6_2,
417 DA830_GPIO6_3,
418 DA830_GPIO6_4,
419 DA830_GPIO6_5,
420 DA830_GPIO6_6,
421 DA830_EMB_D_7,
422 DA830_EMB_D_8,
423 DA830_EMB_D_9,
424 DA830_EMB_D_10,
425 DA830_EMB_D_11,
426 DA830_EMB_D_12,
427 DA830_EMB_D_13,
428 DA830_EMB_D_14,
429 DA830_GPIO6_7,
430 DA830_GPIO6_8,
431 DA830_GPIO6_9,
432 DA830_GPIO6_10,
433 DA830_GPIO6_11,
434 DA830_GPIO6_12,
435 DA830_GPIO6_13,
436 DA830_GPIO6_14,
437 DA830_EMB_D_15,
438 DA830_NEMB_WE_DQM_1,
439 DA830_NEMB_WE_DQM_0,
440 DA830_SPI0_SOMI_0,
441 DA830_SPI0_SIMO_0,
442 DA830_SPI0_CLK,
443 DA830_NSPI0_ENA,
444 DA830_NSPI0_SCS_0,
445 DA830_EQEP0I,
446 DA830_EQEP0S,
447 DA830_EQEP1I,
448 DA830_NUART0_CTS,
449 DA830_NUART0_RTS,
450 DA830_EQEP0A,
451 DA830_EQEP0B,
452 DA830_GPIO6_15,
453 DA830_GPIO5_14,
454 DA830_GPIO5_15,
455 DA830_GPIO5_0,
456 DA830_GPIO5_1,
457 DA830_GPIO5_2,
458 DA830_GPIO5_3,
459 DA830_GPIO5_4,
460 DA830_SPI1_SOMI_0,
461 DA830_SPI1_SIMO_0,
462 DA830_SPI1_CLK,
463 DA830_UART0_RXD,
464 DA830_UART0_TXD,
465 DA830_AXR1_10,
466 DA830_AXR1_11,
467 DA830_NSPI1_ENA,
468 DA830_I2C1_SCL,
469 DA830_I2C1_SDA,
470 DA830_EQEP1S,
471 DA830_I2C0_SDA,
472 DA830_I2C0_SCL,
473 DA830_UART2_RXD,
474 DA830_TM64P0_IN12,
475 DA830_TM64P0_OUT12,
476 DA830_GPIO5_5,
477 DA830_GPIO5_6,
478 DA830_GPIO5_7,
479 DA830_GPIO5_8,
480 DA830_GPIO5_9,
481 DA830_GPIO5_10,
482 DA830_GPIO5_11,
483 DA830_GPIO5_12,
484 DA830_NSPI1_SCS_0,
485 DA830_USB0_DRVVBUS,
486 DA830_AHCLKX0,
487 DA830_ACLKX0,
488 DA830_AFSX0,
489 DA830_AHCLKR0,
490 DA830_ACLKR0,
491 DA830_AFSR0,
492 DA830_UART2_TXD,
493 DA830_AHCLKX2,
494 DA830_ECAP0_APWM0,
495 DA830_RMII_MHZ_50_CLK,
496 DA830_ECAP1_APWM1,
497 DA830_USB_REFCLKIN,
498 DA830_GPIO5_13,
499 DA830_GPIO4_15,
500 DA830_GPIO2_11,
501 DA830_GPIO2_12,
502 DA830_GPIO2_13,
503 DA830_GPIO2_14,
504 DA830_GPIO2_15,
505 DA830_GPIO3_12,
506 DA830_AMUTE0,
507 DA830_AXR0_0,
508 DA830_AXR0_1,
509 DA830_AXR0_2,
510 DA830_AXR0_3,
511 DA830_AXR0_4,
512 DA830_AXR0_5,
513 DA830_AXR0_6,
514 DA830_RMII_TXD_0,
515 DA830_RMII_TXD_1,
516 DA830_RMII_TXEN,
517 DA830_RMII_CRS_DV,
518 DA830_RMII_RXD_0,
519 DA830_RMII_RXD_1,
520 DA830_RMII_RXER,
521 DA830_AFSR2,
522 DA830_ACLKX2,
523 DA830_AXR2_3,
524 DA830_AXR2_2,
525 DA830_AXR2_1,
526 DA830_AFSX2,
527 DA830_ACLKR2,
528 DA830_NRESETOUT,
529 DA830_GPIO3_0,
530 DA830_GPIO3_1,
531 DA830_GPIO3_2,
532 DA830_GPIO3_3,
533 DA830_GPIO3_4,
534 DA830_GPIO3_5,
535 DA830_GPIO3_6,
536 DA830_AXR0_7,
537 DA830_AXR0_8,
538 DA830_UART1_RXD,
539 DA830_UART1_TXD,
540 DA830_AXR0_11,
541 DA830_AHCLKX1,
542 DA830_ACLKX1,
543 DA830_AFSX1,
544 DA830_MDIO_CLK,
545 DA830_MDIO_D,
546 DA830_AXR0_9,
547 DA830_AXR0_10,
548 DA830_EPWM0B,
549 DA830_EPWM0A,
550 DA830_EPWMSYNCI,
551 DA830_AXR2_0,
552 DA830_EPWMSYNC0,
553 DA830_GPIO3_7,
554 DA830_GPIO3_8,
555 DA830_GPIO3_9,
556 DA830_GPIO3_10,
557 DA830_GPIO3_11,
558 DA830_GPIO3_14,
559 DA830_GPIO3_15,
560 DA830_GPIO4_10,
561 DA830_AHCLKR1,
562 DA830_ACLKR1,
563 DA830_AFSR1,
564 DA830_AMUTE1,
565 DA830_AXR1_0,
566 DA830_AXR1_1,
567 DA830_AXR1_2,
568 DA830_AXR1_3,
569 DA830_ECAP2_APWM2,
570 DA830_EHRPWMGLUETZ,
571 DA830_EQEP1A,
572 DA830_GPIO4_11,
573 DA830_GPIO4_12,
574 DA830_GPIO4_13,
575 DA830_GPIO4_14,
576 DA830_GPIO4_0,
577 DA830_GPIO4_1,
578 DA830_GPIO4_2,
579 DA830_GPIO4_3,
580 DA830_AXR1_4,
581 DA830_AXR1_5,
582 DA830_AXR1_6,
583 DA830_AXR1_7,
584 DA830_AXR1_8,
585 DA830_AXR1_9,
586 DA830_EMA_D_0,
587 DA830_EMA_D_1,
588 DA830_EQEP1B,
589 DA830_EPWM2B,
590 DA830_EPWM2A,
591 DA830_EPWM1B,
592 DA830_EPWM1A,
593 DA830_MMCSD_DAT_0,
594 DA830_MMCSD_DAT_1,
595 DA830_UHPI_HD_0,
596 DA830_UHPI_HD_1,
597 DA830_GPIO4_4,
598 DA830_GPIO4_5,
599 DA830_GPIO4_6,
600 DA830_GPIO4_7,
601 DA830_GPIO4_8,
602 DA830_GPIO4_9,
603 DA830_GPIO0_0,
604 DA830_GPIO0_1,
605 DA830_EMA_D_2,
606 DA830_EMA_D_3,
607 DA830_EMA_D_4,
608 DA830_EMA_D_5,
609 DA830_EMA_D_6,
610 DA830_EMA_D_7,
611 DA830_EMA_D_8,
612 DA830_EMA_D_9,
613 DA830_MMCSD_DAT_2,
614 DA830_MMCSD_DAT_3,
615 DA830_MMCSD_DAT_4,
616 DA830_MMCSD_DAT_5,
617 DA830_MMCSD_DAT_6,
618 DA830_MMCSD_DAT_7,
619 DA830_UHPI_HD_8,
620 DA830_UHPI_HD_9,
621 DA830_UHPI_HD_2,
622 DA830_UHPI_HD_3,
623 DA830_UHPI_HD_4,
624 DA830_UHPI_HD_5,
625 DA830_UHPI_HD_6,
626 DA830_UHPI_HD_7,
627 DA830_LCD_D_8,
628 DA830_LCD_D_9,
629 DA830_GPIO0_2,
630 DA830_GPIO0_3,
631 DA830_GPIO0_4,
632 DA830_GPIO0_5,
633 DA830_GPIO0_6,
634 DA830_GPIO0_7,
635 DA830_GPIO0_8,
636 DA830_GPIO0_9,
637 DA830_EMA_D_10,
638 DA830_EMA_D_11,
639 DA830_EMA_D_12,
640 DA830_EMA_D_13,
641 DA830_EMA_D_14,
642 DA830_EMA_D_15,
643 DA830_EMA_A_0,
644 DA830_EMA_A_1,
645 DA830_UHPI_HD_10,
646 DA830_UHPI_HD_11,
647 DA830_UHPI_HD_12,
648 DA830_UHPI_HD_13,
649 DA830_UHPI_HD_14,
650 DA830_UHPI_HD_15,
651 DA830_LCD_D_7,
652 DA830_MMCSD_CLK,
653 DA830_LCD_D_10,
654 DA830_LCD_D_11,
655 DA830_LCD_D_12,
656 DA830_LCD_D_13,
657 DA830_LCD_D_14,
658 DA830_LCD_D_15,
659 DA830_UHPI_HCNTL0,
660 DA830_GPIO0_10,
661 DA830_GPIO0_11,
662 DA830_GPIO0_12,
663 DA830_GPIO0_13,
664 DA830_GPIO0_14,
665 DA830_GPIO0_15,
666 DA830_GPIO1_0,
667 DA830_GPIO1_1,
668 DA830_EMA_A_2,
669 DA830_EMA_A_3,
670 DA830_EMA_A_4,
671 DA830_EMA_A_5,
672 DA830_EMA_A_6,
673 DA830_EMA_A_7,
674 DA830_EMA_A_8,
675 DA830_EMA_A_9,
676 DA830_MMCSD_CMD,
677 DA830_LCD_D_6,
678 DA830_LCD_D_3,
679 DA830_LCD_D_2,
680 DA830_LCD_D_1,
681 DA830_LCD_D_0,
682 DA830_LCD_PCLK,
683 DA830_LCD_HSYNC,
684 DA830_UHPI_HCNTL1,
685 DA830_GPIO1_2,
686 DA830_GPIO1_3,
687 DA830_GPIO1_4,
688 DA830_GPIO1_5,
689 DA830_GPIO1_6,
690 DA830_GPIO1_7,
691 DA830_GPIO1_8,
692 DA830_GPIO1_9,
693 DA830_EMA_A_10,
694 DA830_EMA_A_11,
695 DA830_EMA_A_12,
696 DA830_EMA_BA_1,
697 DA830_EMA_BA_0,
698 DA830_EMA_CLK,
699 DA830_EMA_SDCKE,
700 DA830_NEMA_CAS,
701 DA830_LCD_VSYNC,
702 DA830_NLCD_AC_ENB_CS,
703 DA830_LCD_MCLK,
704 DA830_LCD_D_5,
705 DA830_LCD_D_4,
706 DA830_OBSCLK,
707 DA830_NEMA_CS_4,
708 DA830_UHPI_HHWIL,
709 DA830_AHCLKR2,
710 DA830_GPIO1_10,
711 DA830_GPIO1_11,
712 DA830_GPIO1_12,
713 DA830_GPIO1_13,
714 DA830_GPIO1_14,
715 DA830_GPIO1_15,
716 DA830_GPIO2_0,
717 DA830_GPIO2_1,
718 DA830_NEMA_RAS,
719 DA830_NEMA_WE,
720 DA830_NEMA_CS_0,
721 DA830_NEMA_CS_2,
722 DA830_NEMA_CS_3,
723 DA830_NEMA_OE,
724 DA830_NEMA_WE_DQM_1,
725 DA830_NEMA_WE_DQM_0,
726 DA830_NEMA_CS_5,
727 DA830_UHPI_HRNW,
728 DA830_NUHPI_HAS,
729 DA830_NUHPI_HCS,
730 DA830_NUHPI_HDS1,
731 DA830_NUHPI_HDS2,
732 DA830_NUHPI_HINT,
733 DA830_AXR0_12,
734 DA830_AMUTE2,
735 DA830_AXR0_13,
736 DA830_AXR0_14,
737 DA830_AXR0_15,
738 DA830_GPIO2_2,
739 DA830_GPIO2_3,
740 DA830_GPIO2_4,
741 DA830_GPIO2_5,
742 DA830_GPIO2_6,
743 DA830_GPIO2_7,
744 DA830_GPIO2_8,
745 DA830_GPIO2_9,
746 DA830_EMA_WAIT_0,
747 DA830_NUHPI_HRDY,
748 DA830_GPIO2_10,
749};
750
Sudhakar Rajashekharae1a8d7e2009-07-16 06:41:54 -0400[diff] [blame]751enum davinci_da850_index {
752 /* UART0 function */
753 DA850_NUART0_CTS,
754 DA850_NUART0_RTS,
755 DA850_UART0_RXD,
756 DA850_UART0_TXD,
757
758 /* UART1 function */
759 DA850_NUART1_CTS,
760 DA850_NUART1_RTS,
761 DA850_UART1_RXD,
762 DA850_UART1_TXD,
763
764 /* UART2 function */
765 DA850_NUART2_CTS,
766 DA850_NUART2_RTS,
767 DA850_UART2_RXD,
768 DA850_UART2_TXD,
769
770 /* I2C1 function */
771 DA850_I2C1_SCL,
772 DA850_I2C1_SDA,
773
774 /* I2C0 function */
775 DA850_I2C0_SDA,
776 DA850_I2C0_SCL,
Sudhakar Rajashekhara5a4b1312009-07-17 04:47:10 -0400[diff] [blame]777
778 /* EMAC function */
779 DA850_MII_TXEN,
780 DA850_MII_TXCLK,
781 DA850_MII_COL,
782 DA850_MII_TXD_3,
783 DA850_MII_TXD_2,
784 DA850_MII_TXD_1,
785 DA850_MII_TXD_0,
786 DA850_MII_RXER,
787 DA850_MII_CRS,
788 DA850_MII_RXCLK,
789 DA850_MII_RXDV,
790 DA850_MII_RXD_3,
791 DA850_MII_RXD_2,
792 DA850_MII_RXD_1,
793 DA850_MII_RXD_0,
Sudhakar Rajashekhara53ca5c92009-08-11 11:10:50 -0400[diff] [blame]794 DA850_MDIO_CLK,
795 DA850_MDIO_D,
Chaithrika U S22067712009-09-30 17:00:53 -0400[diff] [blame]796 DA850_RMII_TXD_0,
797 DA850_RMII_TXD_1,
798 DA850_RMII_TXEN,
799 DA850_RMII_CRS_DV,
800 DA850_RMII_RXD_0,
801 DA850_RMII_RXD_1,
802 DA850_RMII_RXER,
803 DA850_RMII_MHZ_50_CLK,
Chaithrika U S491214e2009-08-11 17:03:25 -0400[diff] [blame]804
805 /* McASP function */
806 DA850_ACLKR,
807 DA850_ACLKX,
808 DA850_AFSR,
809 DA850_AFSX,
810 DA850_AHCLKR,
811 DA850_AHCLKX,
812 DA850_AMUTE,
813 DA850_AXR_15,
814 DA850_AXR_14,
815 DA850_AXR_13,
816 DA850_AXR_12,
817 DA850_AXR_11,
818 DA850_AXR_10,
819 DA850_AXR_9,
820 DA850_AXR_8,
821 DA850_AXR_7,
822 DA850_AXR_6,
823 DA850_AXR_5,
824 DA850_AXR_4,
825 DA850_AXR_3,
826 DA850_AXR_2,
827 DA850_AXR_1,
828 DA850_AXR_0,
Sudhakar Rajashekhara5cbdf272009-08-13 14:33:14 -0400[diff] [blame]829
830 /* LCD function */
831 DA850_LCD_D_7,
832 DA850_LCD_D_6,
833 DA850_LCD_D_5,
834 DA850_LCD_D_4,
835 DA850_LCD_D_3,
836 DA850_LCD_D_2,
837 DA850_LCD_D_1,
838 DA850_LCD_D_0,
839 DA850_LCD_D_15,
840 DA850_LCD_D_14,
841 DA850_LCD_D_13,
842 DA850_LCD_D_12,
843 DA850_LCD_D_11,
844 DA850_LCD_D_10,
845 DA850_LCD_D_9,
846 DA850_LCD_D_8,
847 DA850_LCD_PCLK,
848 DA850_LCD_HSYNC,
849 DA850_LCD_VSYNC,
850 DA850_NLCD_AC_ENB_CS,
851
Sudhakar Rajashekhara700691f2009-08-13 15:16:23 -0400[diff] [blame]852 /* MMC/SD0 function */
853 DA850_MMCSD0_DAT_0,
854 DA850_MMCSD0_DAT_1,
855 DA850_MMCSD0_DAT_2,
856 DA850_MMCSD0_DAT_3,
857 DA850_MMCSD0_CLK,
858 DA850_MMCSD0_CMD,
859
Ido Yariv5c4d11b2011-07-10 16:14:37 +0300[diff] [blame]860 /* MMC/SD1 function */
861 DA850_MMCSD1_DAT_0,
862 DA850_MMCSD1_DAT_1,
863 DA850_MMCSD1_DAT_2,
864 DA850_MMCSD1_DAT_3,
865 DA850_MMCSD1_CLK,
866 DA850_MMCSD1_CMD,
867
Sudhakar Rajashekhara38beb922009-08-13 16:21:11 -0400[diff] [blame]868 /* EMIF2.5/EMIFA function */
869 DA850_EMA_D_7,
870 DA850_EMA_D_6,
871 DA850_EMA_D_5,
872 DA850_EMA_D_4,
873 DA850_EMA_D_3,
874 DA850_EMA_D_2,
875 DA850_EMA_D_1,
876 DA850_EMA_D_0,
877 DA850_EMA_A_1,
878 DA850_EMA_A_2,
879 DA850_NEMA_CS_3,
880 DA850_NEMA_CS_4,
881 DA850_NEMA_WE,
882 DA850_NEMA_OE,
Sudhakar Rajashekhara7c5ec602009-08-13 17:36:25 -0400[diff] [blame]883 DA850_EMA_D_15,
884 DA850_EMA_D_14,
885 DA850_EMA_D_13,
886 DA850_EMA_D_12,
887 DA850_EMA_D_11,
888 DA850_EMA_D_10,
889 DA850_EMA_D_9,
890 DA850_EMA_D_8,
891 DA850_EMA_A_0,
892 DA850_EMA_A_3,
893 DA850_EMA_A_4,
894 DA850_EMA_A_5,
895 DA850_EMA_A_6,
896 DA850_EMA_A_7,
897 DA850_EMA_A_8,
898 DA850_EMA_A_9,
899 DA850_EMA_A_10,
900 DA850_EMA_A_11,
901 DA850_EMA_A_12,
902 DA850_EMA_A_13,
903 DA850_EMA_A_14,
904 DA850_EMA_A_15,
905 DA850_EMA_A_16,
906 DA850_EMA_A_17,
907 DA850_EMA_A_18,
908 DA850_EMA_A_19,
909 DA850_EMA_A_20,
910 DA850_EMA_A_21,
911 DA850_EMA_A_22,
912 DA850_EMA_A_23,
913 DA850_EMA_BA_1,
914 DA850_EMA_CLK,
915 DA850_EMA_WAIT_1,
916 DA850_NEMA_CS_2,
Sudhakar Rajashekhara38beb922009-08-13 16:21:11 -0400[diff] [blame]917
Sudhakar Rajashekhara5cbdf272009-08-13 14:33:14 -0400[diff] [blame]918 /* GPIO function */
Victor Rodriguezfe358d62010-12-27 16:43:10 -0600[diff] [blame]919 DA850_GPIO2_4,
Chaithrika U S22067712009-09-30 17:00:53 -0400[diff] [blame]920 DA850_GPIO2_6,
Sudhakar Rajashekhara7761ef62009-09-15 17:46:14 -0400[diff] [blame]921 DA850_GPIO2_8,
Sudhakar Rajashekhara5cbdf272009-08-13 14:33:14 -0400[diff] [blame]922 DA850_GPIO2_15,
Victor Rodriguezfe358d62010-12-27 16:43:10 -0600[diff] [blame]923 DA850_GPIO3_12,
924 DA850_GPIO3_13,
Sudhakar Rajashekhara700691f2009-08-13 15:16:23 -0400[diff] [blame]925 DA850_GPIO4_0,
926 DA850_GPIO4_1,
Ido Yariv68369892011-07-10 16:14:38 +0300[diff] [blame]927 DA850_GPIO6_9,
928 DA850_GPIO6_10,
Victor Rodriguezfe358d62010-12-27 16:43:10 -0600[diff] [blame]929 DA850_GPIO6_13,
Sekhar Nori044ca012009-12-17 18:29:32 +0530[diff] [blame]930 DA850_RTC_ALARM,
Manjunath Hadli154d54a2012-01-23 06:17:24 -0300[diff] [blame]931
932 /* VPIF Capture */
933 DA850_VPIF_DIN0,
934 DA850_VPIF_DIN1,
935 DA850_VPIF_DIN2,
936 DA850_VPIF_DIN3,
937 DA850_VPIF_DIN4,
938 DA850_VPIF_DIN5,
939 DA850_VPIF_DIN6,
940 DA850_VPIF_DIN7,
941 DA850_VPIF_DIN8,
942 DA850_VPIF_DIN9,
943 DA850_VPIF_DIN10,
944 DA850_VPIF_DIN11,
945 DA850_VPIF_DIN12,
946 DA850_VPIF_DIN13,
947 DA850_VPIF_DIN14,
948 DA850_VPIF_DIN15,
949 DA850_VPIF_CLKIN0,
950 DA850_VPIF_CLKIN1,
951 DA850_VPIF_CLKIN2,
952 DA850_VPIF_CLKIN3,
953
954 /* VPIF Display */
955 DA850_VPIF_DOUT0,
956 DA850_VPIF_DOUT1,
957 DA850_VPIF_DOUT2,
958 DA850_VPIF_DOUT3,
959 DA850_VPIF_DOUT4,
960 DA850_VPIF_DOUT5,
961 DA850_VPIF_DOUT6,
962 DA850_VPIF_DOUT7,
963 DA850_VPIF_DOUT8,
964 DA850_VPIF_DOUT9,
965 DA850_VPIF_DOUT10,
966 DA850_VPIF_DOUT11,
967 DA850_VPIF_DOUT12,
968 DA850_VPIF_DOUT13,
969 DA850_VPIF_DOUT14,
970 DA850_VPIF_DOUT15,
971 DA850_VPIF_CLKO2,
972 DA850_VPIF_CLKO3,
Sudhakar Rajashekharae1a8d7e2009-07-16 06:41:54 -0400[diff] [blame]973};
974
Cyril Chemparathy5b3a05c2010-05-01 18:38:27 -0400[diff] [blame]975#define PINMUX(x) (4 * (x))
976
Kevin Hilman5526b3f2009-04-14 09:50:37 -0500[diff] [blame]977#ifdef CONFIG_DAVINCI_MUX
978/* setup pin muxing */
Kevin Hilman5526b3f2009-04-14 09:50:37 -0500[diff] [blame]979extern int davinci_cfg_reg(unsigned long reg_cfg);
Cyril Chemparathy3821d102010-03-25 17:43:48 -0400[diff] [blame]980extern int davinci_cfg_reg_list(const short pins[]);
Kevin Hilman5526b3f2009-04-14 09:50:37 -0500[diff] [blame]981#else
982/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
Kevin Hilman5526b3f2009-04-14 09:50:37 -0500[diff] [blame]983static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
Cyril Chemparathy3821d102010-03-25 17:43:48 -0400[diff] [blame]984static inline int davinci_cfg_reg_list(const short pins[])
985{
986 return 0;
987}
Kevin Hilman5526b3f2009-04-14 09:50:37 -0500[diff] [blame]988#endif
989
990#endif /* __INC_MACH_MUX_H */