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Sangbeom Kim172a4532011-06-20 16:36:18 +09001/*
2 * linux/sound/soc/samsung/i2s-regs.h
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung I2S driver's register header
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#ifndef __SND_SOC_SAMSUNG_I2S_REGS_H
16#define __SND_SOC_SAMSUNG_I2S_REGS_H
17
18#define I2SCON 0x0
19#define I2SMOD 0x4
20#define I2SFIC 0x8
21#define I2SPSR 0xc
22#define I2STXD 0x10
23#define I2SRXD 0x14
24#define I2SFICS 0x18
25#define I2STXDS 0x1c
Sangbeom Kim766705e2011-06-20 16:36:19 +090026#define I2SAHB 0x20
27#define I2SSTR0 0x24
28#define I2SSIZE 0x28
29#define I2STRNCNT 0x2c
30#define I2SLVL0ADDR 0x30
31#define I2SLVL1ADDR 0x34
32#define I2SLVL2ADDR 0x38
33#define I2SLVL3ADDR 0x3c
Padmavathi Venna4ca0c0d2013-08-12 15:19:52 +053034#define I2SSTR1 0x40
35#define I2SVER 0x44
Padmavathi Vennaa5a56872014-11-07 12:24:40 +053036#define I2SFIC1 0x48
Padmavathi Venna4ca0c0d2013-08-12 15:19:52 +053037#define I2STDM 0x4c
Padmavathi Vennaa5a56872014-11-07 12:24:40 +053038#define I2SFSTA 0x50
Sangbeom Kim172a4532011-06-20 16:36:18 +090039
40#define CON_RSTCLR (1 << 31)
41#define CON_FRXOFSTATUS (1 << 26)
42#define CON_FRXORINTEN (1 << 25)
43#define CON_FTXSURSTAT (1 << 24)
44#define CON_FTXSURINTEN (1 << 23)
45#define CON_TXSDMA_PAUSE (1 << 20)
46#define CON_TXSDMA_ACTIVE (1 << 18)
47
48#define CON_FTXURSTATUS (1 << 17)
49#define CON_FTXURINTEN (1 << 16)
50#define CON_TXFIFO2_EMPTY (1 << 15)
51#define CON_TXFIFO1_EMPTY (1 << 14)
52#define CON_TXFIFO2_FULL (1 << 13)
53#define CON_TXFIFO1_FULL (1 << 12)
54
55#define CON_LRINDEX (1 << 11)
56#define CON_TXFIFO_EMPTY (1 << 10)
57#define CON_RXFIFO_EMPTY (1 << 9)
58#define CON_TXFIFO_FULL (1 << 8)
59#define CON_RXFIFO_FULL (1 << 7)
60#define CON_TXDMA_PAUSE (1 << 6)
61#define CON_RXDMA_PAUSE (1 << 5)
62#define CON_TXCH_PAUSE (1 << 4)
63#define CON_RXCH_PAUSE (1 << 3)
64#define CON_TXDMA_ACTIVE (1 << 2)
65#define CON_RXDMA_ACTIVE (1 << 1)
66#define CON_ACTIVE (1 << 0)
67
68#define MOD_OPCLK_CDCLK_OUT (0 << 30)
69#define MOD_OPCLK_CDCLK_IN (1 << 30)
70#define MOD_OPCLK_BCLK_OUT (2 << 30)
71#define MOD_OPCLK_PCLK (3 << 30)
72#define MOD_OPCLK_MASK (3 << 30)
73#define MOD_TXS_IDMA (1 << 28) /* Sec_TXFIFO use I-DMA */
74
75#define MOD_BLCS_SHIFT 26
76#define MOD_BLCS_16BIT (0 << MOD_BLCS_SHIFT)
77#define MOD_BLCS_8BIT (1 << MOD_BLCS_SHIFT)
78#define MOD_BLCS_24BIT (2 << MOD_BLCS_SHIFT)
79#define MOD_BLCS_MASK (3 << MOD_BLCS_SHIFT)
80#define MOD_BLCP_SHIFT 24
81#define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT)
82#define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT)
83#define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT)
84#define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT)
85
86#define MOD_C2DD_HHALF (1 << 21) /* Discard Higher-half */
87#define MOD_C2DD_LHALF (1 << 20) /* Discard Lower-half */
88#define MOD_C1DD_HHALF (1 << 19)
89#define MOD_C1DD_LHALF (1 << 18)
90#define MOD_DC2_EN (1 << 17)
91#define MOD_DC1_EN (1 << 16)
92#define MOD_BLC_16BIT (0 << 13)
93#define MOD_BLC_8BIT (1 << 13)
94#define MOD_BLC_24BIT (2 << 13)
95#define MOD_BLC_MASK (3 << 13)
96
Sangbeom Kim172a4532011-06-20 16:36:18 +090097#define MOD_TXONLY (0 << 8)
98#define MOD_RXONLY (1 << 8)
99#define MOD_TXRX (2 << 8)
100#define MOD_MASK (3 << 8)
Padmavathi Vennab60be4a2013-07-26 19:06:48 +0530101#define MOD_LRP_SHIFT 7
102#define MOD_LR_LLOW 0
103#define MOD_LR_RLOW 1
104#define MOD_SDF_SHIFT 5
105#define MOD_SDF_IIS 0
106#define MOD_SDF_MSB 1
107#define MOD_SDF_LSB 2
108#define MOD_SDF_MASK 3
109#define MOD_RCLK_SHIFT 3
110#define MOD_RCLK_256FS 0
111#define MOD_RCLK_512FS 1
112#define MOD_RCLK_384FS 2
113#define MOD_RCLK_768FS 3
114#define MOD_RCLK_MASK 3
115#define MOD_BCLK_SHIFT 1
116#define MOD_BCLK_32FS 0
117#define MOD_BCLK_48FS 1
118#define MOD_BCLK_16FS 2
119#define MOD_BCLK_24FS 3
120#define MOD_BCLK_MASK 3
Sangbeom Kim172a4532011-06-20 16:36:18 +0900121#define MOD_8BIT (1 << 0)
122
Padmavathi Venna4ca0c0d2013-08-12 15:19:52 +0530123#define EXYNOS5420_MOD_LRP_SHIFT 15
124#define EXYNOS5420_MOD_SDF_SHIFT 6
125#define EXYNOS5420_MOD_RCLK_SHIFT 4
126#define EXYNOS5420_MOD_BCLK_SHIFT 0
127#define EXYNOS5420_MOD_BCLK_64FS 4
128#define EXYNOS5420_MOD_BCLK_96FS 5
129#define EXYNOS5420_MOD_BCLK_128FS 6
130#define EXYNOS5420_MOD_BCLK_192FS 7
131#define EXYNOS5420_MOD_BCLK_256FS 8
132#define EXYNOS5420_MOD_BCLK_MASK 0xf
133
Padmavathi Vennaa5a56872014-11-07 12:24:40 +0530134#define EXYNOS7_MOD_RCLK_64FS 4
135#define EXYNOS7_MOD_RCLK_128FS 5
136#define EXYNOS7_MOD_RCLK_96FS 6
137#define EXYNOS7_MOD_RCLK_192FS 7
Sangbeom Kim172a4532011-06-20 16:36:18 +0900138
139#define PSR_PSREN (1 << 15)
140
141#define FIC_TX2COUNT(x) (((x) >> 24) & 0xf)
142#define FIC_TX1COUNT(x) (((x) >> 16) & 0xf)
143
144#define FIC_TXFLUSH (1 << 15)
145#define FIC_RXFLUSH (1 << 7)
Sangbeom Kim766705e2011-06-20 16:36:19 +0900146
Sangbeom Kim172a4532011-06-20 16:36:18 +0900147#define FIC_TXCOUNT(x) (((x) >> 8) & 0xf)
148#define FIC_RXCOUNT(x) (((x) >> 0) & 0xf)
149#define FICS_TXCOUNT(x) (((x) >> 8) & 0x7f)
150
Sangbeom Kim766705e2011-06-20 16:36:19 +0900151#define AHB_INTENLVL0 (1 << 24)
152#define AHB_LVL0INT (1 << 20)
153#define AHB_CLRLVL0INT (1 << 16)
154#define AHB_DMARLD (1 << 5)
155#define AHB_INTMASK (1 << 3)
156#define AHB_DMAEN (1 << 0)
157#define AHB_LVLINTMASK (0xf << 20)
158
159#define I2SSIZE_TRNMSK (0xffff)
160#define I2SSIZE_SHIFT (16)
161
Sangbeom Kim172a4532011-06-20 16:36:18 +0900162#endif /* __SND_SOC_SAMSUNG_I2S_REGS_H */
163
164