Blame - arch/powerpc/kernel/cpu_setup_power.S - LeafOS-Devices/android_kernel_samsung_gta4xl

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Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	1	/*
				2	* This file contains low level CPU setup functions.
				3	* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
				4	*
				5	* This program is free software; you can redistribute it and/or
				6	* modify it under the terms of the GNU General Public License
				7	* as published by the Free Software Foundation; either version
				8	* 2 of the License, or (at your option) any later version.
				9	*
				10	*/
				11
				12	#include <asm/processor.h>
				13	#include <asm/page.h>
				14	#include <asm/cputable.h>
				15	#include <asm/ppc_asm.h>
				16	#include <asm/asm-offsets.h>
				17	#include <asm/cache.h>
				18
				19	/* Entry: r3 = crap, r4 = ptr to cputable entry
				20	*
				21	* Note that we can be called twice for pseudo-PVRs
				22	*/
				23	_GLOBAL(__setup_cpu_power7)
				24	mflr r11
				25	bl __init_hvmode_206
				26	mtlr r11
				27	beqlr
Benjamin Herrenschmidt	b144871	2011-03-01 15:46:09 +1100	[diff] [blame]	28	li r0,0
				29	mtspr SPRN_LPID,r0
Michael Neuling	f7c32c2	2012-11-05 14:40:18 +1100	[diff] [blame]	30	mfspr r3,SPRN_LPCR
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	31	bl __init_LPCR
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	32	bl __init_tlb_power7
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	33	mtlr r11
				34	blr
				35
				36	_GLOBAL(__restore_cpu_power7)
				37	mflr r11
				38	mfmsr r3
				39	rldicl. r0,r3,4,63
				40	beqlr
Benjamin Herrenschmidt	b144871	2011-03-01 15:46:09 +1100	[diff] [blame]	41	li r0,0
				42	mtspr SPRN_LPID,r0
Michael Neuling	f7c32c2	2012-11-05 14:40:18 +1100	[diff] [blame]	43	mfspr r3,SPRN_LPCR
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	44	bl __init_LPCR
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	45	bl __init_tlb_power7
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	46	mtlr r11
				47	blr
				48
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	49	_GLOBAL(__setup_cpu_power8)
				50	mflr r11
Michael Neuling	57d2316	2013-03-04 19:45:50 +0000	[diff] [blame]	51	bl __init_FSCR
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	52	bl __init_PMU
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	53	bl __init_hvmode_206
				54	mtlr r11
				55	beqlr
				56	li r0,0
				57	mtspr SPRN_LPID,r0
Michael Neuling	f7c32c2	2012-11-05 14:40:18 +1100	[diff] [blame]	58	mfspr r3,SPRN_LPCR
Michael Neuling	d4e58e5	2014-06-11 15:59:28 +1000	[diff] [blame]	59	ori r3, r3, LPCR_PECEDH
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	60	bl __init_LPCR
Michael Neuling	2a3563b	2013-03-05 17:35:24 +0000	[diff] [blame]	61	bl __init_HFSCR
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	62	bl __init_tlb_power8
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	63	bl __init_PMU_HV
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	64	mtlr r11
				65	blr
				66
				67	_GLOBAL(__restore_cpu_power8)
				68	mflr r11
Michael Neuling	57d2316	2013-03-04 19:45:50 +0000	[diff] [blame]	69	bl __init_FSCR
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	70	bl __init_PMU
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	71	mfmsr r3
				72	rldicl. r0,r3,4,63
Michael Neuling	8c2a381	2013-04-24 21:00:37 +0000	[diff] [blame]	73	mtlr r11
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	74	beqlr
				75	li r0,0
				76	mtspr SPRN_LPID,r0
Michael Neuling	f7c32c2	2012-11-05 14:40:18 +1100	[diff] [blame]	77	mfspr r3,SPRN_LPCR
Michael Neuling	d4e58e5	2014-06-11 15:59:28 +1000	[diff] [blame]	78	ori r3, r3, LPCR_PECEDH
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	79	bl __init_LPCR
Michael Neuling	2a3563b	2013-03-05 17:35:24 +0000	[diff] [blame]	80	bl __init_HFSCR
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	81	bl __init_tlb_power8
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	82	bl __init_PMU_HV
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	83	mtlr r11
				84	blr
				85
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	86	__init_hvmode_206:
Paul Mackerras	969391c	2011-06-29 00:26:11 +0000	[diff] [blame]	87	/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	88	mfmsr r3
				89	rldicl. r0,r3,4,63
				90	bnelr
				91	ld r5,CPU_SPEC_FEATURES(r4)
Paul Mackerras	969391c	2011-06-29 00:26:11 +0000	[diff] [blame]	92	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	93	xor r5,r5,r6
				94	std r5,CPU_SPEC_FEATURES(r4)
				95	blr
				96
				97	__init_LPCR:
				98	/* Setup a sane LPCR:
Michael Neuling	f7c32c2	2012-11-05 14:40:18 +1100	[diff] [blame]	99	* Called with initial LPCR in R3
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	100	*
Benjamin Herrenschmidt	a5d4f3a	2011-04-05 14:20:31 +1000	[diff] [blame]	101	* LPES = 0b01 (HSRR0/1 used for 0x500)
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	102	* PECE = 0b111
Benjamin Herrenschmidt	895796a	2011-01-24 13:25:55 +1100	[diff] [blame]	103	* DPFD = 4
Paul Mackerras	923c53c	2011-06-29 00:20:24 +0000	[diff] [blame]	104	* HDICE = 0
				105	* VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
				106	* VRMASD = 0b10000 (L=1, LP=00)
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	107	*
				108	* Other bits untouched for now
				109	*/
Paul Mackerras	923c53c	2011-06-29 00:20:24 +0000	[diff] [blame]	110	li r5,1
				111	rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	112	ori r3,r3,(LPCR_PECE0\|LPCR_PECE1\|LPCR_PECE2)
Benjamin Herrenschmidt	895796a	2011-01-24 13:25:55 +1100	[diff] [blame]	113	li r5,4
Paul Mackerras	923c53c	2011-06-29 00:20:24 +0000	[diff] [blame]	114	rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
				115	clrrdi r3,r3,1 /* clear HDICE */
				116	li r5,4
				117	rldimi r3,r5, LPCR_VC_SH, 0
				118	li r5,0x10
				119	rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	120	mtspr SPRN_LPCR,r3
				121	isync
				122	blr
Benjamin Herrenschmidt	b144871	2011-03-01 15:46:09 +1100	[diff] [blame]	123
Ian Munsie	2468dcf	2013-02-07 15:46:58 +0000	[diff] [blame]	124	__init_FSCR:
				125	mfspr r3,SPRN_FSCR
Michael Neuling	1ddf499	2013-04-30 20:17:03 +0000	[diff] [blame]	126	ori r3,r3,FSCR_TAR\|FSCR_DSCR\|FSCR_EBB
Ian Munsie	2468dcf	2013-02-07 15:46:58 +0000	[diff] [blame]	127	mtspr SPRN_FSCR,r3
				128	blr
				129
Michael Neuling	2a3563b	2013-03-05 17:35:24 +0000	[diff] [blame]	130	__init_HFSCR:
				131	mfspr r3,SPRN_HFSCR
Anshuman Khandual	53b56ca	2013-04-25 20:54:55 +0000	[diff] [blame]	132	ori r3,r3,HFSCR_TAR\|HFSCR_TM\|HFSCR_BHRB\|HFSCR_PM\|\
Michael Neuling	1ddf499	2013-04-30 20:17:03 +0000	[diff] [blame]	133	HFSCR_DSCR\|HFSCR_VECVSX\|HFSCR_FP\|HFSCR_EBB
Michael Neuling	2a3563b	2013-03-05 17:35:24 +0000	[diff] [blame]	134	mtspr SPRN_HFSCR,r3
				135	blr
				136
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	137	/*
				138	* Clear the TLB using the specified IS form of tlbiel instruction
				139	* (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	140	*/
				141	__init_tlb_power7:
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	142	li r6,128
				143	mtctr r6
Mahesh Salgaonkar	45706bb	2014-12-19 08:41:05 +0530	[diff] [blame]	144	li r7,0xc00 /* IS field = 0b11 */
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	145	ptesync
				146	2: tlbiel r7
				147	addi r7,r7,0x1000
				148	bdnz 2b
				149	ptesync
				150	1: blr
				151
				152	__init_tlb_power8:
Benjamin Herrenschmidt	8fc1f5d	2013-05-20 17:23:22 +0000	[diff] [blame]	153	li r6,512
Benjamin Herrenschmidt	b144871	2011-03-01 15:46:09 +1100	[diff] [blame]	154	mtctr r6
Mahesh Salgaonkar	45706bb	2014-12-19 08:41:05 +0530	[diff] [blame]	155	li r7,0xc00 /* IS field = 0b11 */
Benjamin Herrenschmidt	b144871	2011-03-01 15:46:09 +1100	[diff] [blame]	156	ptesync
				157	2: tlbiel r7
				158	addi r7,r7,0x1000
				159	bdnz 2b
				160	ptesync
				161	1: blr
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	162
				163	__init_PMU_HV:
				164	li r5,0
				165	mtspr SPRN_MMCRC,r5
				166	mtspr SPRN_MMCRH,r5
				167	blr
				168
				169	__init_PMU:
				170	li r5,0
				171	mtspr SPRN_MMCRS,r5
				172	mtspr SPRN_MMCRA,r5
				173	mtspr SPRN_MMCR0,r5
				174	mtspr SPRN_MMCR1,r5
				175	mtspr SPRN_MMCR2,r5
				176	blr