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Bryan Wud24ecfc2007-05-01 23:26:32 +02001/*
Mike Frysingerbd584992008-04-22 22:16:48 +02002 * Blackfin On-Chip Two Wire Interface Driver
Bryan Wud24ecfc2007-05-01 23:26:32 +02003 *
Mike Frysingerbd584992008-04-22 22:16:48 +02004 * Copyright 2005-2007 Analog Devices Inc.
Bryan Wud24ecfc2007-05-01 23:26:32 +02005 *
Mike Frysingerbd584992008-04-22 22:16:48 +02006 * Enter bugs at http://blackfin.uclinux.org/
Bryan Wud24ecfc2007-05-01 23:26:32 +02007 *
Mike Frysingerbd584992008-04-22 22:16:48 +02008 * Licensed under the GPL-2 or later.
Bryan Wud24ecfc2007-05-01 23:26:32 +02009 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/i2c.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090015#include <linux/slab.h>
Mike Frysinger6df263c2009-06-14 01:55:37 -040016#include <linux/io.h>
Bryan Wud24ecfc2007-05-01 23:26:32 +020017#include <linux/mm.h>
18#include <linux/timer.h>
19#include <linux/spinlock.h>
20#include <linux/completion.h>
21#include <linux/interrupt.h>
22#include <linux/platform_device.h>
23
24#include <asm/blackfin.h>
Bryan Wu74d362e2008-04-22 22:16:48 +020025#include <asm/portmux.h>
Bryan Wud24ecfc2007-05-01 23:26:32 +020026#include <asm/irq.h>
27
Bryan Wud24ecfc2007-05-01 23:26:32 +020028/* SMBus mode*/
Sonic Zhang4dd39bb2008-04-22 22:16:47 +020029#define TWI_I2C_MODE_STANDARD 1
30#define TWI_I2C_MODE_STANDARDSUB 2
31#define TWI_I2C_MODE_COMBINED 3
32#define TWI_I2C_MODE_REPEAT 4
Bryan Wud24ecfc2007-05-01 23:26:32 +020033
34struct bfin_twi_iface {
Bryan Wud24ecfc2007-05-01 23:26:32 +020035 int irq;
36 spinlock_t lock;
37 char read_write;
38 u8 command;
39 u8 *transPtr;
40 int readNum;
41 int writeNum;
42 int cur_mode;
43 int manual_stop;
44 int result;
Bryan Wud24ecfc2007-05-01 23:26:32 +020045 struct i2c_adapter adap;
46 struct completion complete;
Sonic Zhang4dd39bb2008-04-22 22:16:47 +020047 struct i2c_msg *pmsg;
48 int msg_num;
49 int cur_msg;
Michael Hennerich958585f2008-07-27 14:41:54 +080050 u16 saved_clkdiv;
51 u16 saved_control;
Bryan Wuaa3d0202008-04-22 22:16:48 +020052 void __iomem *regs_base;
Bryan Wud24ecfc2007-05-01 23:26:32 +020053};
54
Bryan Wuaa3d0202008-04-22 22:16:48 +020055
56#define DEFINE_TWI_REG(reg, off) \
57static inline u16 read_##reg(struct bfin_twi_iface *iface) \
58 { return bfin_read16(iface->regs_base + (off)); } \
59static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
60 { bfin_write16(iface->regs_base + (off), v); }
61
62DEFINE_TWI_REG(CLKDIV, 0x00)
63DEFINE_TWI_REG(CONTROL, 0x04)
64DEFINE_TWI_REG(SLAVE_CTL, 0x08)
65DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
66DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
67DEFINE_TWI_REG(MASTER_CTL, 0x14)
68DEFINE_TWI_REG(MASTER_STAT, 0x18)
69DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
70DEFINE_TWI_REG(INT_STAT, 0x20)
71DEFINE_TWI_REG(INT_MASK, 0x24)
72DEFINE_TWI_REG(FIFO_CTL, 0x28)
73DEFINE_TWI_REG(FIFO_STAT, 0x2C)
74DEFINE_TWI_REG(XMT_DATA8, 0x80)
75DEFINE_TWI_REG(XMT_DATA16, 0x84)
76DEFINE_TWI_REG(RCV_DATA8, 0x88)
77DEFINE_TWI_REG(RCV_DATA16, 0x8C)
Bryan Wud24ecfc2007-05-01 23:26:32 +020078
Bryan Wu74d362e2008-04-22 22:16:48 +020079static const u16 pin_req[2][3] = {
80 {P_TWI0_SCL, P_TWI0_SDA, 0},
81 {P_TWI1_SCL, P_TWI1_SDA, 0},
82};
83
Sonic Zhang5481d072010-03-22 03:23:18 -040084static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
85 unsigned short twi_int_status)
Bryan Wud24ecfc2007-05-01 23:26:32 +020086{
Bryan Wuaa3d0202008-04-22 22:16:48 +020087 unsigned short mast_stat = read_MASTER_STAT(iface);
Bryan Wud24ecfc2007-05-01 23:26:32 +020088
89 if (twi_int_status & XMTSERV) {
90 /* Transmit next data */
91 if (iface->writeNum > 0) {
Sonic Zhang5481d072010-03-22 03:23:18 -040092 SSYNC();
Bryan Wuaa3d0202008-04-22 22:16:48 +020093 write_XMT_DATA8(iface, *(iface->transPtr++));
Bryan Wud24ecfc2007-05-01 23:26:32 +020094 iface->writeNum--;
95 }
96 /* start receive immediately after complete sending in
97 * combine mode.
98 */
Sonic Zhang4dd39bb2008-04-22 22:16:47 +020099 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
Bryan Wuaa3d0202008-04-22 22:16:48 +0200100 write_MASTER_CTL(iface,
101 read_MASTER_CTL(iface) | MDIR | RSTART);
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200102 else if (iface->manual_stop)
Bryan Wuaa3d0202008-04-22 22:16:48 +0200103 write_MASTER_CTL(iface,
104 read_MASTER_CTL(iface) | STOP);
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200105 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
Frank Shew94327d02009-05-19 07:23:49 -0400106 iface->cur_msg + 1 < iface->msg_num) {
107 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
108 write_MASTER_CTL(iface,
109 read_MASTER_CTL(iface) | RSTART | MDIR);
110 else
111 write_MASTER_CTL(iface,
112 (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
113 }
Bryan Wud24ecfc2007-05-01 23:26:32 +0200114 }
115 if (twi_int_status & RCVSERV) {
116 if (iface->readNum > 0) {
117 /* Receive next data */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200118 *(iface->transPtr) = read_RCV_DATA8(iface);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200119 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
120 /* Change combine mode into sub mode after
121 * read first data.
122 */
123 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
124 /* Get read number from first byte in block
125 * combine mode.
126 */
127 if (iface->readNum == 1 && iface->manual_stop)
128 iface->readNum = *iface->transPtr + 1;
129 }
130 iface->transPtr++;
131 iface->readNum--;
132 } else if (iface->manual_stop) {
Bryan Wuaa3d0202008-04-22 22:16:48 +0200133 write_MASTER_CTL(iface,
134 read_MASTER_CTL(iface) | STOP);
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200135 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
Frank Shew94327d02009-05-19 07:23:49 -0400136 iface->cur_msg + 1 < iface->msg_num) {
137 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
138 write_MASTER_CTL(iface,
139 read_MASTER_CTL(iface) | RSTART | MDIR);
140 else
141 write_MASTER_CTL(iface,
142 (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200143 }
Bryan Wud24ecfc2007-05-01 23:26:32 +0200144 }
145 if (twi_int_status & MERR) {
Bryan Wuaa3d0202008-04-22 22:16:48 +0200146 write_INT_MASK(iface, 0);
147 write_MASTER_STAT(iface, 0x3e);
148 write_MASTER_CTL(iface, 0);
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200149 iface->result = -EIO;
Michael Hennerich5cfafc12010-03-22 03:23:17 -0400150
151 if (mast_stat & LOSTARB)
152 dev_dbg(&iface->adap.dev, "Lost Arbitration\n");
153 if (mast_stat & ANAK)
154 dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n");
155 if (mast_stat & DNAK)
156 dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n");
157 if (mast_stat & BUFRDERR)
158 dev_dbg(&iface->adap.dev, "Buffer Read Error\n");
159 if (mast_stat & BUFWRERR)
160 dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
161
Sonic Zhangf0ac1312010-03-22 03:23:20 -0400162 /* If it is a quick transfer, only address without data,
163 * not an err, return 1.
Bryan Wud24ecfc2007-05-01 23:26:32 +0200164 */
Sonic Zhangf0ac1312010-03-22 03:23:20 -0400165 if (iface->cur_mode == TWI_I2C_MODE_STANDARD &&
166 iface->transPtr == NULL &&
167 (twi_int_status & MCOMP) && (mast_stat & DNAK))
168 iface->result = 1;
169
Bryan Wud24ecfc2007-05-01 23:26:32 +0200170 complete(&iface->complete);
171 return;
172 }
173 if (twi_int_status & MCOMP) {
Bryan Wud24ecfc2007-05-01 23:26:32 +0200174 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
175 if (iface->readNum == 0) {
176 /* set the read number to 1 and ask for manual
177 * stop in block combine mode
178 */
179 iface->readNum = 1;
180 iface->manual_stop = 1;
Bryan Wuaa3d0202008-04-22 22:16:48 +0200181 write_MASTER_CTL(iface,
182 read_MASTER_CTL(iface) | (0xff << 6));
Bryan Wud24ecfc2007-05-01 23:26:32 +0200183 } else {
184 /* set the readd number in other
185 * combine mode.
186 */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200187 write_MASTER_CTL(iface,
188 (read_MASTER_CTL(iface) &
Bryan Wud24ecfc2007-05-01 23:26:32 +0200189 (~(0xff << 6))) |
Bryan Wuaa3d0202008-04-22 22:16:48 +0200190 (iface->readNum << 6));
Bryan Wud24ecfc2007-05-01 23:26:32 +0200191 }
192 /* remove restart bit and enable master receive */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200193 write_MASTER_CTL(iface,
194 read_MASTER_CTL(iface) & ~RSTART);
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200195 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
196 iface->cur_msg+1 < iface->msg_num) {
197 iface->cur_msg++;
198 iface->transPtr = iface->pmsg[iface->cur_msg].buf;
199 iface->writeNum = iface->readNum =
200 iface->pmsg[iface->cur_msg].len;
201 /* Set Transmit device address */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200202 write_MASTER_ADDR(iface,
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200203 iface->pmsg[iface->cur_msg].addr);
204 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
205 iface->read_write = I2C_SMBUS_READ;
206 else {
207 iface->read_write = I2C_SMBUS_WRITE;
208 /* Transmit first data */
209 if (iface->writeNum > 0) {
Bryan Wuaa3d0202008-04-22 22:16:48 +0200210 write_XMT_DATA8(iface,
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200211 *(iface->transPtr++));
212 iface->writeNum--;
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200213 }
214 }
215
216 if (iface->pmsg[iface->cur_msg].len <= 255)
Sonic Zhang57a8f322009-05-19 07:21:58 -0400217 write_MASTER_CTL(iface,
218 (read_MASTER_CTL(iface) &
219 (~(0xff << 6))) |
220 (iface->pmsg[iface->cur_msg].len << 6));
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200221 else {
Sonic Zhang57a8f322009-05-19 07:21:58 -0400222 write_MASTER_CTL(iface,
223 (read_MASTER_CTL(iface) |
224 (0xff << 6)));
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200225 iface->manual_stop = 1;
226 }
227 /* remove restart bit and enable master receive */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200228 write_MASTER_CTL(iface,
229 read_MASTER_CTL(iface) & ~RSTART);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200230 } else {
231 iface->result = 1;
Bryan Wuaa3d0202008-04-22 22:16:48 +0200232 write_INT_MASK(iface, 0);
233 write_MASTER_CTL(iface, 0);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200234 }
235 }
Sonic Zhangdd7319a2010-03-22 03:23:16 -0400236 complete(&iface->complete);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200237}
238
239/* Interrupt handler */
240static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
241{
242 struct bfin_twi_iface *iface = dev_id;
243 unsigned long flags;
Sonic Zhang5481d072010-03-22 03:23:18 -0400244 unsigned short twi_int_status;
Bryan Wud24ecfc2007-05-01 23:26:32 +0200245
246 spin_lock_irqsave(&iface->lock, flags);
Sonic Zhang5481d072010-03-22 03:23:18 -0400247 while (1) {
248 twi_int_status = read_INT_STAT(iface);
249 if (!twi_int_status)
250 break;
251 /* Clear interrupt status */
252 write_INT_STAT(iface, twi_int_status);
253 bfin_twi_handle_interrupt(iface, twi_int_status);
254 SSYNC();
255 }
Bryan Wud24ecfc2007-05-01 23:26:32 +0200256 spin_unlock_irqrestore(&iface->lock, flags);
257 return IRQ_HANDLED;
258}
259
Bryan Wud24ecfc2007-05-01 23:26:32 +0200260/*
Sonic Zhangdd7319a2010-03-22 03:23:16 -0400261 * One i2c master transfer
Bryan Wud24ecfc2007-05-01 23:26:32 +0200262 */
Sonic Zhangdd7319a2010-03-22 03:23:16 -0400263static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
Bryan Wud24ecfc2007-05-01 23:26:32 +0200264 struct i2c_msg *msgs, int num)
265{
266 struct bfin_twi_iface *iface = adap->algo_data;
267 struct i2c_msg *pmsg;
Bryan Wud24ecfc2007-05-01 23:26:32 +0200268 int rc = 0;
269
Bryan Wuaa3d0202008-04-22 22:16:48 +0200270 if (!(read_CONTROL(iface) & TWI_ENA))
Bryan Wud24ecfc2007-05-01 23:26:32 +0200271 return -ENXIO;
272
Bryan Wuaa3d0202008-04-22 22:16:48 +0200273 while (read_MASTER_STAT(iface) & BUSBUSY)
Bryan Wud24ecfc2007-05-01 23:26:32 +0200274 yield();
Bryan Wud24ecfc2007-05-01 23:26:32 +0200275
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200276 iface->pmsg = msgs;
277 iface->msg_num = num;
278 iface->cur_msg = 0;
Bryan Wud24ecfc2007-05-01 23:26:32 +0200279
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200280 pmsg = &msgs[0];
281 if (pmsg->flags & I2C_M_TEN) {
282 dev_err(&adap->dev, "10 bits addr not supported!\n");
283 return -EINVAL;
Bryan Wud24ecfc2007-05-01 23:26:32 +0200284 }
285
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200286 iface->cur_mode = TWI_I2C_MODE_REPEAT;
287 iface->manual_stop = 0;
288 iface->transPtr = pmsg->buf;
289 iface->writeNum = iface->readNum = pmsg->len;
290 iface->result = 0;
Hans Schillstromafc13b72008-04-22 22:16:48 +0200291 init_completion(&(iface->complete));
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200292 /* Set Transmit device address */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200293 write_MASTER_ADDR(iface, pmsg->addr);
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200294
295 /* FIFO Initiation. Data in FIFO should be
296 * discarded before start a new operation.
297 */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200298 write_FIFO_CTL(iface, 0x3);
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200299 SSYNC();
Bryan Wuaa3d0202008-04-22 22:16:48 +0200300 write_FIFO_CTL(iface, 0);
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200301 SSYNC();
302
303 if (pmsg->flags & I2C_M_RD)
304 iface->read_write = I2C_SMBUS_READ;
305 else {
306 iface->read_write = I2C_SMBUS_WRITE;
307 /* Transmit first data */
308 if (iface->writeNum > 0) {
Bryan Wuaa3d0202008-04-22 22:16:48 +0200309 write_XMT_DATA8(iface, *(iface->transPtr++));
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200310 iface->writeNum--;
311 SSYNC();
312 }
313 }
314
315 /* clear int stat */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200316 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200317
318 /* Interrupt mask . Enable XMT, RCV interrupt */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200319 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200320 SSYNC();
321
322 if (pmsg->len <= 255)
Bryan Wuaa3d0202008-04-22 22:16:48 +0200323 write_MASTER_CTL(iface, pmsg->len << 6);
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200324 else {
Bryan Wuaa3d0202008-04-22 22:16:48 +0200325 write_MASTER_CTL(iface, 0xff << 6);
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200326 iface->manual_stop = 1;
327 }
328
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200329 /* Master enable */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200330 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200331 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
332 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
333 SSYNC();
334
Sonic Zhangdd7319a2010-03-22 03:23:16 -0400335 while (!iface->result) {
336 if (!wait_for_completion_timeout(&iface->complete,
337 adap->timeout)) {
338 iface->result = -1;
339 dev_err(&adap->dev, "master transfer timeout\n");
340 }
341 }
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200342
Sonic Zhangdd7319a2010-03-22 03:23:16 -0400343 if (iface->result == 1)
344 rc = iface->cur_msg + 1;
Sonic Zhang4dd39bb2008-04-22 22:16:47 +0200345 else
Sonic Zhangdd7319a2010-03-22 03:23:16 -0400346 rc = iface->result;
347
348 return rc;
Bryan Wud24ecfc2007-05-01 23:26:32 +0200349}
350
351/*
Sonic Zhangdd7319a2010-03-22 03:23:16 -0400352 * Generic i2c master transfer entrypoint
Bryan Wud24ecfc2007-05-01 23:26:32 +0200353 */
Sonic Zhangdd7319a2010-03-22 03:23:16 -0400354static int bfin_twi_master_xfer(struct i2c_adapter *adap,
355 struct i2c_msg *msgs, int num)
356{
Sonic Zhangbe2f80f2010-03-22 03:23:19 -0400357 return bfin_twi_do_master_xfer(adap, msgs, num);
Sonic Zhangdd7319a2010-03-22 03:23:16 -0400358}
359
360/*
361 * One I2C SMBus transfer
362 */
363int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
Bryan Wud24ecfc2007-05-01 23:26:32 +0200364 unsigned short flags, char read_write,
365 u8 command, int size, union i2c_smbus_data *data)
366{
367 struct bfin_twi_iface *iface = adap->algo_data;
368 int rc = 0;
369
Bryan Wuaa3d0202008-04-22 22:16:48 +0200370 if (!(read_CONTROL(iface) & TWI_ENA))
Bryan Wud24ecfc2007-05-01 23:26:32 +0200371 return -ENXIO;
372
Bryan Wuaa3d0202008-04-22 22:16:48 +0200373 while (read_MASTER_STAT(iface) & BUSBUSY)
Bryan Wud24ecfc2007-05-01 23:26:32 +0200374 yield();
Bryan Wud24ecfc2007-05-01 23:26:32 +0200375
376 iface->writeNum = 0;
377 iface->readNum = 0;
378
379 /* Prepare datas & select mode */
380 switch (size) {
381 case I2C_SMBUS_QUICK:
382 iface->transPtr = NULL;
383 iface->cur_mode = TWI_I2C_MODE_STANDARD;
384 break;
385 case I2C_SMBUS_BYTE:
386 if (data == NULL)
387 iface->transPtr = NULL;
388 else {
389 if (read_write == I2C_SMBUS_READ)
390 iface->readNum = 1;
391 else
392 iface->writeNum = 1;
393 iface->transPtr = &data->byte;
394 }
395 iface->cur_mode = TWI_I2C_MODE_STANDARD;
396 break;
397 case I2C_SMBUS_BYTE_DATA:
398 if (read_write == I2C_SMBUS_READ) {
399 iface->readNum = 1;
400 iface->cur_mode = TWI_I2C_MODE_COMBINED;
401 } else {
402 iface->writeNum = 1;
403 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
404 }
405 iface->transPtr = &data->byte;
406 break;
407 case I2C_SMBUS_WORD_DATA:
408 if (read_write == I2C_SMBUS_READ) {
409 iface->readNum = 2;
410 iface->cur_mode = TWI_I2C_MODE_COMBINED;
411 } else {
412 iface->writeNum = 2;
413 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
414 }
415 iface->transPtr = (u8 *)&data->word;
416 break;
417 case I2C_SMBUS_PROC_CALL:
418 iface->writeNum = 2;
419 iface->readNum = 2;
420 iface->cur_mode = TWI_I2C_MODE_COMBINED;
421 iface->transPtr = (u8 *)&data->word;
422 break;
423 case I2C_SMBUS_BLOCK_DATA:
424 if (read_write == I2C_SMBUS_READ) {
425 iface->readNum = 0;
426 iface->cur_mode = TWI_I2C_MODE_COMBINED;
427 } else {
428 iface->writeNum = data->block[0] + 1;
429 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
430 }
431 iface->transPtr = data->block;
432 break;
Michael Henneriche0cd2dd2009-05-27 09:24:10 +0000433 case I2C_SMBUS_I2C_BLOCK_DATA:
434 if (read_write == I2C_SMBUS_READ) {
435 iface->readNum = data->block[0];
436 iface->cur_mode = TWI_I2C_MODE_COMBINED;
437 } else {
438 iface->writeNum = data->block[0];
439 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
440 }
441 iface->transPtr = (u8 *)&data->block[1];
442 break;
Bryan Wud24ecfc2007-05-01 23:26:32 +0200443 default:
444 return -1;
445 }
446
447 iface->result = 0;
448 iface->manual_stop = 0;
449 iface->read_write = read_write;
450 iface->command = command;
Hans Schillstromafc13b72008-04-22 22:16:48 +0200451 init_completion(&(iface->complete));
Bryan Wud24ecfc2007-05-01 23:26:32 +0200452
453 /* FIFO Initiation. Data in FIFO should be discarded before
454 * start a new operation.
455 */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200456 write_FIFO_CTL(iface, 0x3);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200457 SSYNC();
Bryan Wuaa3d0202008-04-22 22:16:48 +0200458 write_FIFO_CTL(iface, 0);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200459
460 /* clear int stat */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200461 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200462
463 /* Set Transmit device address */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200464 write_MASTER_ADDR(iface, addr);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200465 SSYNC();
466
Bryan Wud24ecfc2007-05-01 23:26:32 +0200467 switch (iface->cur_mode) {
468 case TWI_I2C_MODE_STANDARDSUB:
Bryan Wuaa3d0202008-04-22 22:16:48 +0200469 write_XMT_DATA8(iface, iface->command);
470 write_INT_MASK(iface, MCOMP | MERR |
Bryan Wud24ecfc2007-05-01 23:26:32 +0200471 ((iface->read_write == I2C_SMBUS_READ) ?
472 RCVSERV : XMTSERV));
473 SSYNC();
474
475 if (iface->writeNum + 1 <= 255)
Bryan Wuaa3d0202008-04-22 22:16:48 +0200476 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200477 else {
Bryan Wuaa3d0202008-04-22 22:16:48 +0200478 write_MASTER_CTL(iface, 0xff << 6);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200479 iface->manual_stop = 1;
480 }
481 /* Master enable */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200482 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
Bryan Wud24ecfc2007-05-01 23:26:32 +0200483 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
484 break;
485 case TWI_I2C_MODE_COMBINED:
Bryan Wuaa3d0202008-04-22 22:16:48 +0200486 write_XMT_DATA8(iface, iface->command);
487 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200488 SSYNC();
489
490 if (iface->writeNum > 0)
Bryan Wuaa3d0202008-04-22 22:16:48 +0200491 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200492 else
Bryan Wuaa3d0202008-04-22 22:16:48 +0200493 write_MASTER_CTL(iface, 0x1 << 6);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200494 /* Master enable */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200495 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
Bryan Wud24ecfc2007-05-01 23:26:32 +0200496 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
497 break;
498 default:
Bryan Wuaa3d0202008-04-22 22:16:48 +0200499 write_MASTER_CTL(iface, 0);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200500 if (size != I2C_SMBUS_QUICK) {
501 /* Don't access xmit data register when this is a
502 * read operation.
503 */
504 if (iface->read_write != I2C_SMBUS_READ) {
505 if (iface->writeNum > 0) {
Bryan Wuaa3d0202008-04-22 22:16:48 +0200506 write_XMT_DATA8(iface,
507 *(iface->transPtr++));
Bryan Wud24ecfc2007-05-01 23:26:32 +0200508 if (iface->writeNum <= 255)
Bryan Wuaa3d0202008-04-22 22:16:48 +0200509 write_MASTER_CTL(iface,
510 iface->writeNum << 6);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200511 else {
Bryan Wuaa3d0202008-04-22 22:16:48 +0200512 write_MASTER_CTL(iface,
513 0xff << 6);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200514 iface->manual_stop = 1;
515 }
516 iface->writeNum--;
517 } else {
Bryan Wuaa3d0202008-04-22 22:16:48 +0200518 write_XMT_DATA8(iface, iface->command);
519 write_MASTER_CTL(iface, 1 << 6);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200520 }
521 } else {
522 if (iface->readNum > 0 && iface->readNum <= 255)
Bryan Wuaa3d0202008-04-22 22:16:48 +0200523 write_MASTER_CTL(iface,
524 iface->readNum << 6);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200525 else if (iface->readNum > 255) {
Bryan Wuaa3d0202008-04-22 22:16:48 +0200526 write_MASTER_CTL(iface, 0xff << 6);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200527 iface->manual_stop = 1;
Sonic Zhangdd7319a2010-03-22 03:23:16 -0400528 } else
Bryan Wud24ecfc2007-05-01 23:26:32 +0200529 break;
Bryan Wud24ecfc2007-05-01 23:26:32 +0200530 }
531 }
Bryan Wuaa3d0202008-04-22 22:16:48 +0200532 write_INT_MASK(iface, MCOMP | MERR |
Bryan Wud24ecfc2007-05-01 23:26:32 +0200533 ((iface->read_write == I2C_SMBUS_READ) ?
534 RCVSERV : XMTSERV));
535 SSYNC();
536
537 /* Master enable */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200538 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
Bryan Wud24ecfc2007-05-01 23:26:32 +0200539 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
540 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
541 break;
542 }
543 SSYNC();
544
Sonic Zhangdd7319a2010-03-22 03:23:16 -0400545 while (!iface->result) {
546 if (!wait_for_completion_timeout(&iface->complete,
547 adap->timeout)) {
548 iface->result = -1;
549 dev_err(&adap->dev, "smbus transfer timeout\n");
550 }
551 }
Bryan Wud24ecfc2007-05-01 23:26:32 +0200552
553 rc = (iface->result >= 0) ? 0 : -1;
554
Bryan Wud24ecfc2007-05-01 23:26:32 +0200555 return rc;
556}
557
558/*
Sonic Zhangdd7319a2010-03-22 03:23:16 -0400559 * Generic I2C SMBus transfer entrypoint
560 */
561int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
562 unsigned short flags, char read_write,
563 u8 command, int size, union i2c_smbus_data *data)
564{
Sonic Zhangbe2f80f2010-03-22 03:23:19 -0400565 return bfin_twi_do_smbus_xfer(adap, addr, flags,
Sonic Zhangdd7319a2010-03-22 03:23:16 -0400566 read_write, command, size, data);
Sonic Zhangdd7319a2010-03-22 03:23:16 -0400567}
568
569/*
Bryan Wud24ecfc2007-05-01 23:26:32 +0200570 * Return what the adapter supports
571 */
572static u32 bfin_twi_functionality(struct i2c_adapter *adap)
573{
574 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
575 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
576 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
Michael Henneriche0cd2dd2009-05-27 09:24:10 +0000577 I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
Bryan Wud24ecfc2007-05-01 23:26:32 +0200578}
579
Bryan Wud24ecfc2007-05-01 23:26:32 +0200580static struct i2c_algorithm bfin_twi_algorithm = {
581 .master_xfer = bfin_twi_master_xfer,
582 .smbus_xfer = bfin_twi_smbus_xfer,
583 .functionality = bfin_twi_functionality,
584};
585
Michael Hennerich958585f2008-07-27 14:41:54 +0800586static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
Bryan Wud24ecfc2007-05-01 23:26:32 +0200587{
Michael Hennerich958585f2008-07-27 14:41:54 +0800588 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
589
590 iface->saved_clkdiv = read_CLKDIV(iface);
591 iface->saved_control = read_CONTROL(iface);
592
593 free_irq(iface->irq, iface);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200594
595 /* Disable TWI */
Michael Hennerich958585f2008-07-27 14:41:54 +0800596 write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200597
598 return 0;
599}
600
Michael Hennerich958585f2008-07-27 14:41:54 +0800601static int i2c_bfin_twi_resume(struct platform_device *pdev)
Bryan Wud24ecfc2007-05-01 23:26:32 +0200602{
Michael Hennerich958585f2008-07-27 14:41:54 +0800603 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200604
Michael Hennerich958585f2008-07-27 14:41:54 +0800605 int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
606 IRQF_DISABLED, pdev->name, iface);
607 if (rc) {
608 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
609 return -ENODEV;
610 }
611
612 /* Resume TWI interface clock as specified */
613 write_CLKDIV(iface, iface->saved_clkdiv);
614
615 /* Resume TWI */
616 write_CONTROL(iface, iface->saved_control);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200617
618 return 0;
619}
620
Bryan Wuaa3d0202008-04-22 22:16:48 +0200621static int i2c_bfin_twi_probe(struct platform_device *pdev)
Bryan Wud24ecfc2007-05-01 23:26:32 +0200622{
Bryan Wuaa3d0202008-04-22 22:16:48 +0200623 struct bfin_twi_iface *iface;
Bryan Wud24ecfc2007-05-01 23:26:32 +0200624 struct i2c_adapter *p_adap;
Bryan Wuaa3d0202008-04-22 22:16:48 +0200625 struct resource *res;
Bryan Wud24ecfc2007-05-01 23:26:32 +0200626 int rc;
Michael Hennerich9528d1c2009-05-18 08:14:41 -0400627 unsigned int clkhilow;
Bryan Wud24ecfc2007-05-01 23:26:32 +0200628
Bryan Wuaa3d0202008-04-22 22:16:48 +0200629 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
630 if (!iface) {
631 dev_err(&pdev->dev, "Cannot allocate memory\n");
632 rc = -ENOMEM;
633 goto out_error_nomem;
634 }
635
Bryan Wud24ecfc2007-05-01 23:26:32 +0200636 spin_lock_init(&(iface->lock));
Bryan Wuaa3d0202008-04-22 22:16:48 +0200637
638 /* Find and map our resources */
639 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
640 if (res == NULL) {
641 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
642 rc = -ENOENT;
643 goto out_error_get_res;
644 }
645
Linus Walleijc6ffdde2009-06-14 00:20:36 +0200646 iface->regs_base = ioremap(res->start, resource_size(res));
Bryan Wuaa3d0202008-04-22 22:16:48 +0200647 if (iface->regs_base == NULL) {
648 dev_err(&pdev->dev, "Cannot map IO\n");
649 rc = -ENXIO;
650 goto out_error_ioremap;
651 }
652
653 iface->irq = platform_get_irq(pdev, 0);
654 if (iface->irq < 0) {
655 dev_err(&pdev->dev, "No IRQ specified\n");
656 rc = -ENOENT;
657 goto out_error_no_irq;
658 }
Bryan Wud24ecfc2007-05-01 23:26:32 +0200659
Bryan Wud24ecfc2007-05-01 23:26:32 +0200660 p_adap = &iface->adap;
Bryan Wuaa3d0202008-04-22 22:16:48 +0200661 p_adap->nr = pdev->id;
662 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
Bryan Wud24ecfc2007-05-01 23:26:32 +0200663 p_adap->algo = &bfin_twi_algorithm;
664 p_adap->algo_data = iface;
Jean Delvaree1995f62009-01-07 14:29:16 +0100665 p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
Bryan Wuaa3d0202008-04-22 22:16:48 +0200666 p_adap->dev.parent = &pdev->dev;
Sonic Zhangdd7319a2010-03-22 03:23:16 -0400667 p_adap->timeout = 5 * HZ;
668 p_adap->retries = 3;
Bryan Wud24ecfc2007-05-01 23:26:32 +0200669
Bryan Wu74d362e2008-04-22 22:16:48 +0200670 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
671 if (rc) {
672 dev_err(&pdev->dev, "Can't setup pin mux!\n");
673 goto out_error_pin_mux;
674 }
675
Bryan Wud24ecfc2007-05-01 23:26:32 +0200676 rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
Bryan Wuaa3d0202008-04-22 22:16:48 +0200677 IRQF_DISABLED, pdev->name, iface);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200678 if (rc) {
Bryan Wuaa3d0202008-04-22 22:16:48 +0200679 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
680 rc = -ENODEV;
681 goto out_error_req_irq;
Bryan Wud24ecfc2007-05-01 23:26:32 +0200682 }
683
684 /* Set TWI internal clock as 10MHz */
Sonic Zhangac07fb42009-12-21 09:28:30 -0500685 write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200686
Michael Hennerich9528d1c2009-05-18 08:14:41 -0400687 /*
688 * We will not end up with a CLKDIV=0 because no one will specify
Sonic Zhangac07fb42009-12-21 09:28:30 -0500689 * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
Michael Hennerich9528d1c2009-05-18 08:14:41 -0400690 */
Sonic Zhangac07fb42009-12-21 09:28:30 -0500691 clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
Michael Hennerich9528d1c2009-05-18 08:14:41 -0400692
Bryan Wud24ecfc2007-05-01 23:26:32 +0200693 /* Set Twi interface clock as specified */
Michael Hennerich9528d1c2009-05-18 08:14:41 -0400694 write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200695
696 /* Enable TWI */
Bryan Wuaa3d0202008-04-22 22:16:48 +0200697 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200698 SSYNC();
699
Kalle Pokki991dee52008-01-27 18:14:52 +0100700 rc = i2c_add_numbered_adapter(p_adap);
Bryan Wuaa3d0202008-04-22 22:16:48 +0200701 if (rc < 0) {
702 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
703 goto out_error_add_adapter;
704 }
Bryan Wud24ecfc2007-05-01 23:26:32 +0200705
Bryan Wuaa3d0202008-04-22 22:16:48 +0200706 platform_set_drvdata(pdev, iface);
707
Bryan Wufa6ad222008-04-22 22:16:48 +0200708 dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
709 "regs_base@%p\n", iface->regs_base);
Bryan Wuaa3d0202008-04-22 22:16:48 +0200710
711 return 0;
712
713out_error_add_adapter:
714 free_irq(iface->irq, iface);
715out_error_req_irq:
716out_error_no_irq:
Bryan Wu74d362e2008-04-22 22:16:48 +0200717 peripheral_free_list(pin_req[pdev->id]);
718out_error_pin_mux:
Bryan Wuaa3d0202008-04-22 22:16:48 +0200719 iounmap(iface->regs_base);
720out_error_ioremap:
721out_error_get_res:
722 kfree(iface);
723out_error_nomem:
Bryan Wud24ecfc2007-05-01 23:26:32 +0200724 return rc;
725}
726
727static int i2c_bfin_twi_remove(struct platform_device *pdev)
728{
729 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
730
731 platform_set_drvdata(pdev, NULL);
732
733 i2c_del_adapter(&(iface->adap));
734 free_irq(iface->irq, iface);
Bryan Wu74d362e2008-04-22 22:16:48 +0200735 peripheral_free_list(pin_req[pdev->id]);
Bryan Wuaa3d0202008-04-22 22:16:48 +0200736 iounmap(iface->regs_base);
737 kfree(iface);
Bryan Wud24ecfc2007-05-01 23:26:32 +0200738
739 return 0;
740}
741
742static struct platform_driver i2c_bfin_twi_driver = {
743 .probe = i2c_bfin_twi_probe,
744 .remove = i2c_bfin_twi_remove,
745 .suspend = i2c_bfin_twi_suspend,
746 .resume = i2c_bfin_twi_resume,
747 .driver = {
748 .name = "i2c-bfin-twi",
749 .owner = THIS_MODULE,
750 },
751};
752
753static int __init i2c_bfin_twi_init(void)
754{
Bryan Wud24ecfc2007-05-01 23:26:32 +0200755 return platform_driver_register(&i2c_bfin_twi_driver);
756}
757
758static void __exit i2c_bfin_twi_exit(void)
759{
760 platform_driver_unregister(&i2c_bfin_twi_driver);
761}
762
Bryan Wud24ecfc2007-05-01 23:26:32 +0200763module_init(i2c_bfin_twi_init);
764module_exit(i2c_bfin_twi_exit);
Bryan Wufa6ad222008-04-22 22:16:48 +0200765
766MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
767MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
768MODULE_LICENSE("GPL");
Kay Sieversadd8eda2008-04-22 22:16:49 +0200769MODULE_ALIAS("platform:i2c-bfin-twi");