Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 2 | config MMU |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 3 | def_bool n |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 4 | |
| 5 | config FPU |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 6 | def_bool n |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 7 | |
| 8 | config RWSEM_GENERIC_SPINLOCK |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 9 | def_bool y |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 10 | |
| 11 | config RWSEM_XCHGADD_ALGORITHM |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 12 | def_bool n |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 13 | |
| 14 | config BLACKFIN |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 15 | def_bool y |
Mike Frysinger | 652afdc | 2010-01-25 22:12:32 +0000 | [diff] [blame] | 16 | select HAVE_ARCH_KGDB |
Mike Frysinger | e8f263d | 2010-01-26 07:33:53 +0000 | [diff] [blame] | 17 | select HAVE_ARCH_TRACEHOOK |
Mike Frysinger | f507442 | 2010-07-21 09:13:02 -0400 | [diff] [blame] | 18 | select HAVE_DYNAMIC_FTRACE |
| 19 | select HAVE_FTRACE_MCOUNT_RECORD |
Mike Frysinger | 1ee76d7 | 2009-06-10 04:45:29 -0400 | [diff] [blame] | 20 | select HAVE_FUNCTION_GRAPH_TRACER |
Mike Frysinger | 1c873be | 2009-06-09 07:25:09 -0400 | [diff] [blame] | 21 | select HAVE_FUNCTION_TRACER |
Sam Ravnborg | ec7748b | 2008-02-09 10:46:40 +0100 | [diff] [blame] | 22 | select HAVE_IDE |
Barry Song | d86bfb1 | 2010-01-07 04:11:17 +0000 | [diff] [blame] | 23 | select HAVE_KERNEL_GZIP if RAMKERNEL |
| 24 | select HAVE_KERNEL_BZIP2 if RAMKERNEL |
| 25 | select HAVE_KERNEL_LZMA if RAMKERNEL |
Mike Frysinger | 67df6cc | 2010-07-19 05:37:54 +0000 | [diff] [blame] | 26 | select HAVE_KERNEL_LZO if RAMKERNEL |
Mathieu Desnoyers | 42d4b83 | 2008-02-02 15:10:34 -0500 | [diff] [blame] | 27 | select HAVE_OPROFILE |
Mike Frysinger | 7db7917 | 2011-05-06 11:47:52 -0400 | [diff] [blame] | 28 | select HAVE_PERF_EVENTS |
Mark Brown | 7563bbf | 2012-04-15 10:52:54 +0100 | [diff] [blame] | 29 | select ARCH_HAVE_CUSTOM_GPIO_H |
Linus Walleij | e8919e9 | 2016-04-19 11:12:36 +0200 | [diff] [blame] | 30 | select GPIOLIB |
Catalin Marinas | af1839e | 2012-10-08 16:28:08 -0700 | [diff] [blame] | 31 | select HAVE_UID16 |
Rusty Russell | b92021b | 2013-03-15 15:04:17 +1030 | [diff] [blame] | 32 | select HAVE_UNDERSCORE_SYMBOL_PREFIX |
Stephen Rothwell | 4febd95 | 2013-03-07 15:48:16 +1100 | [diff] [blame] | 33 | select VIRT_TO_BUS |
Will Deacon | c1d7e01 | 2012-07-30 14:42:46 -0700 | [diff] [blame] | 34 | select ARCH_WANT_IPC_PARSE_VERSION |
Mike Frysinger | bee18be | 2011-03-21 02:39:10 -0400 | [diff] [blame] | 35 | select GENERIC_ATOMIC64 |
Thomas Gleixner | 7b02886 | 2011-01-19 20:29:58 +0100 | [diff] [blame] | 36 | select GENERIC_IRQ_PROBE |
Thomas Gleixner | e8fac63 | 2014-02-23 21:40:13 +0000 | [diff] [blame] | 37 | select GENERIC_IRQ_SHOW |
Cong Wang | d314d74 | 2012-03-23 15:01:51 -0700 | [diff] [blame] | 38 | select HAVE_NMI_WATCHDOG if NMI_WATCHDOG |
Thomas Gleixner | 6bba268 | 2012-04-20 13:05:53 +0000 | [diff] [blame] | 39 | select GENERIC_SMP_IDLE_THREAD |
Anna-Maria Gleixner | dfbaec0 | 2012-05-18 16:45:45 +0000 | [diff] [blame] | 40 | select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS |
David Howells | 786d35d | 2012-09-28 14:31:03 +0930 | [diff] [blame] | 41 | select HAVE_MOD_ARCH_SPECIFIC |
| 42 | select MODULES_USE_ELF_RELA |
Dave Hansen | d1a1dc0 | 2013-07-01 13:04:42 -0700 | [diff] [blame] | 43 | select HAVE_DEBUG_STACKOVERFLOW |
Petr Mladek | 42a0bb3 | 2016-05-20 17:00:33 -0700 | [diff] [blame] | 44 | select HAVE_NMI |
Vladimir Murzin | 07c75d7 | 2017-06-28 10:16:57 +0100 | [diff] [blame] | 45 | select ARCH_NO_COHERENT_DMA_MMAP |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 46 | |
Mike Frysinger | ddf9dda | 2009-06-13 07:42:58 -0400 | [diff] [blame] | 47 | config GENERIC_CSUM |
| 48 | def_bool y |
| 49 | |
Mike Frysinger | 70f1256 | 2009-06-07 17:18:25 -0400 | [diff] [blame] | 50 | config GENERIC_BUG |
| 51 | def_bool y |
| 52 | depends on BUG |
| 53 | |
Aubrey Li | e3defff | 2007-05-21 18:09:11 +0800 | [diff] [blame] | 54 | config ZONE_DMA |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 55 | def_bool y |
Aubrey Li | e3defff | 2007-05-21 18:09:11 +0800 | [diff] [blame] | 56 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 57 | config FORCE_MAX_ZONEORDER |
| 58 | int |
| 59 | default "14" |
| 60 | |
| 61 | config GENERIC_CALIBRATE_DELAY |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 62 | def_bool y |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 63 | |
Mike Frysinger | 6fa68e7 | 2009-06-08 18:45:01 -0400 | [diff] [blame] | 64 | config LOCKDEP_SUPPORT |
| 65 | def_bool y |
| 66 | |
Mike Frysinger | c7b412f | 2009-06-08 18:44:45 -0400 | [diff] [blame] | 67 | config STACKTRACE_SUPPORT |
| 68 | def_bool y |
| 69 | |
Mike Frysinger | 8f86001 | 2009-06-08 12:49:48 -0400 | [diff] [blame] | 70 | config TRACE_IRQFLAGS_SUPPORT |
| 71 | def_bool y |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 72 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 73 | source "init/Kconfig" |
Matt Helsley | dc52ddc | 2008-10-18 20:27:21 -0700 | [diff] [blame] | 74 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 75 | source "kernel/Kconfig.preempt" |
| 76 | |
Matt Helsley | dc52ddc | 2008-10-18 20:27:21 -0700 | [diff] [blame] | 77 | source "kernel/Kconfig.freezer" |
| 78 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 79 | menu "Blackfin Processor Options" |
| 80 | |
| 81 | comment "Processor and Board Settings" |
| 82 | |
| 83 | choice |
| 84 | prompt "CPU" |
| 85 | default BF533 |
| 86 | |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 87 | config BF512 |
| 88 | bool "BF512" |
| 89 | help |
| 90 | BF512 Processor Support. |
| 91 | |
| 92 | config BF514 |
| 93 | bool "BF514" |
| 94 | help |
| 95 | BF514 Processor Support. |
| 96 | |
| 97 | config BF516 |
| 98 | bool "BF516" |
| 99 | help |
| 100 | BF516 Processor Support. |
| 101 | |
| 102 | config BF518 |
| 103 | bool "BF518" |
| 104 | help |
| 105 | BF518 Processor Support. |
| 106 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 107 | config BF522 |
| 108 | bool "BF522" |
| 109 | help |
| 110 | BF522 Processor Support. |
| 111 | |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 112 | config BF523 |
| 113 | bool "BF523" |
| 114 | help |
| 115 | BF523 Processor Support. |
| 116 | |
| 117 | config BF524 |
| 118 | bool "BF524" |
| 119 | help |
| 120 | BF524 Processor Support. |
| 121 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 122 | config BF525 |
| 123 | bool "BF525" |
| 124 | help |
| 125 | BF525 Processor Support. |
| 126 | |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 127 | config BF526 |
| 128 | bool "BF526" |
| 129 | help |
| 130 | BF526 Processor Support. |
| 131 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 132 | config BF527 |
| 133 | bool "BF527" |
| 134 | help |
| 135 | BF527 Processor Support. |
| 136 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 137 | config BF531 |
| 138 | bool "BF531" |
| 139 | help |
| 140 | BF531 Processor Support. |
| 141 | |
| 142 | config BF532 |
| 143 | bool "BF532" |
| 144 | help |
| 145 | BF532 Processor Support. |
| 146 | |
| 147 | config BF533 |
| 148 | bool "BF533" |
| 149 | help |
| 150 | BF533 Processor Support. |
| 151 | |
| 152 | config BF534 |
| 153 | bool "BF534" |
| 154 | help |
| 155 | BF534 Processor Support. |
| 156 | |
| 157 | config BF536 |
| 158 | bool "BF536" |
| 159 | help |
| 160 | BF536 Processor Support. |
| 161 | |
| 162 | config BF537 |
| 163 | bool "BF537" |
| 164 | help |
| 165 | BF537 Processor Support. |
| 166 | |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 167 | config BF538 |
| 168 | bool "BF538" |
| 169 | help |
| 170 | BF538 Processor Support. |
| 171 | |
| 172 | config BF539 |
| 173 | bool "BF539" |
| 174 | help |
| 175 | BF539 Processor Support. |
| 176 | |
Mike Frysinger | 5df326a | 2009-11-16 23:49:41 +0000 | [diff] [blame] | 177 | config BF542_std |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 178 | bool "BF542" |
| 179 | help |
| 180 | BF542 Processor Support. |
| 181 | |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 182 | config BF542M |
| 183 | bool "BF542m" |
| 184 | help |
| 185 | BF542 Processor Support. |
| 186 | |
Mike Frysinger | 5df326a | 2009-11-16 23:49:41 +0000 | [diff] [blame] | 187 | config BF544_std |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 188 | bool "BF544" |
| 189 | help |
| 190 | BF544 Processor Support. |
| 191 | |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 192 | config BF544M |
| 193 | bool "BF544m" |
| 194 | help |
| 195 | BF544 Processor Support. |
| 196 | |
Mike Frysinger | 5df326a | 2009-11-16 23:49:41 +0000 | [diff] [blame] | 197 | config BF547_std |
Mike Frysinger | 7c7fd17 | 2007-11-15 21:10:21 +0800 | [diff] [blame] | 198 | bool "BF547" |
| 199 | help |
| 200 | BF547 Processor Support. |
| 201 | |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 202 | config BF547M |
| 203 | bool "BF547m" |
| 204 | help |
| 205 | BF547 Processor Support. |
| 206 | |
Mike Frysinger | 5df326a | 2009-11-16 23:49:41 +0000 | [diff] [blame] | 207 | config BF548_std |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 208 | bool "BF548" |
| 209 | help |
| 210 | BF548 Processor Support. |
| 211 | |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 212 | config BF548M |
| 213 | bool "BF548m" |
| 214 | help |
| 215 | BF548 Processor Support. |
| 216 | |
Mike Frysinger | 5df326a | 2009-11-16 23:49:41 +0000 | [diff] [blame] | 217 | config BF549_std |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 218 | bool "BF549" |
| 219 | help |
| 220 | BF549 Processor Support. |
| 221 | |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 222 | config BF549M |
| 223 | bool "BF549m" |
| 224 | help |
| 225 | BF549 Processor Support. |
| 226 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 227 | config BF561 |
| 228 | bool "BF561" |
| 229 | help |
Mike Frysinger | cd88b4d | 2008-10-09 12:03:22 +0800 | [diff] [blame] | 230 | BF561 Processor Support. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 231 | |
Bob Liu | b5affb0 | 2012-05-16 17:37:24 +0800 | [diff] [blame] | 232 | config BF609 |
| 233 | bool "BF609" |
| 234 | select CLKDEV_LOOKUP |
| 235 | help |
| 236 | BF609 Processor Support. |
| 237 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 238 | endchoice |
| 239 | |
Graf Yang | 46fa5ee | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 240 | config SMP |
| 241 | depends on BF561 |
Yi Li | 0d152c2 | 2009-12-28 10:21:49 +0000 | [diff] [blame] | 242 | select TICKSOURCE_CORETMR |
Graf Yang | 46fa5ee | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 243 | bool "Symmetric multi-processing support" |
| 244 | ---help--- |
| 245 | This enables support for systems with more than one CPU, |
| 246 | like the dual core BF561. If you have a system with only one |
| 247 | CPU, say N. If you have a system with more than one CPU, say Y. |
| 248 | |
| 249 | If you don't know what to do here, say N. |
| 250 | |
| 251 | config NR_CPUS |
| 252 | int |
| 253 | depends on SMP |
| 254 | default 2 if BF561 |
| 255 | |
Graf Yang | 0b39db2 | 2009-12-28 11:13:51 +0000 | [diff] [blame] | 256 | config HOTPLUG_CPU |
| 257 | bool "Support for hot-pluggable CPUs" |
Stephen Rothwell | 40b3136 | 2013-05-21 13:49:35 +1000 | [diff] [blame] | 258 | depends on SMP |
Graf Yang | 0b39db2 | 2009-12-28 11:13:51 +0000 | [diff] [blame] | 259 | default y |
| 260 | |
Mike Frysinger | 0c0497c | 2008-10-09 17:32:28 +0800 | [diff] [blame] | 261 | config BF_REV_MIN |
| 262 | int |
Bob Liu | b5affb0 | 2012-05-16 17:37:24 +0800 | [diff] [blame] | 263 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x |
Mike Frysinger | 0c0497c | 2008-10-09 17:32:28 +0800 | [diff] [blame] | 264 | default 2 if (BF537 || BF536 || BF534) |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 265 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 266 | default 4 if (BF538 || BF539) |
Mike Frysinger | 0c0497c | 2008-10-09 17:32:28 +0800 | [diff] [blame] | 267 | |
| 268 | config BF_REV_MAX |
| 269 | int |
Bob Liu | b5affb0 | 2012-05-16 17:37:24 +0800 | [diff] [blame] | 270 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 271 | default 3 if (BF537 || BF536 || BF534 || BF54xM) |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 272 | default 5 if (BF561 || BF538 || BF539) |
Mike Frysinger | 0c0497c | 2008-10-09 17:32:28 +0800 | [diff] [blame] | 273 | default 6 if (BF533 || BF532 || BF531) |
| 274 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 275 | choice |
| 276 | prompt "Silicon Rev" |
Bob Liu | b5affb0 | 2012-05-16 17:37:24 +0800 | [diff] [blame] | 277 | default BF_REV_0_0 if (BF51x || BF52x || BF60x) |
Mike Frysinger | f8b5565 | 2009-04-13 21:58:34 +0000 | [diff] [blame] | 278 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 279 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 280 | |
| 281 | config BF_REV_0_0 |
| 282 | bool "0.0" |
Bob Liu | b5affb0 | 2012-05-16 17:37:24 +0800 | [diff] [blame] | 283 | depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 284 | |
| 285 | config BF_REV_0_1 |
Mike Frysinger | d07f438 | 2007-11-15 15:49:17 +0800 | [diff] [blame] | 286 | bool "0.1" |
Sonic Zhang | 67c0b1b | 2013-06-07 16:45:12 +0800 | [diff] [blame] | 287 | depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 288 | |
| 289 | config BF_REV_0_2 |
| 290 | bool "0.2" |
Mike Frysinger | 8060bb6 | 2010-08-16 16:18:12 +0000 | [diff] [blame] | 291 | depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 292 | |
| 293 | config BF_REV_0_3 |
| 294 | bool "0.3" |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 295 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 296 | |
| 297 | config BF_REV_0_4 |
| 298 | bool "0.4" |
Sonic Zhang | ee5124e3 | 2012-08-31 11:13:31 +0800 | [diff] [blame] | 299 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 300 | |
| 301 | config BF_REV_0_5 |
| 302 | bool "0.5" |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 303 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 304 | |
Mike Frysinger | 49f7253 | 2008-10-09 12:06:27 +0800 | [diff] [blame] | 305 | config BF_REV_0_6 |
| 306 | bool "0.6" |
| 307 | depends on (BF533 || BF532 || BF531) |
| 308 | |
Jie Zhang | de3025f | 2007-06-25 18:04:12 +0800 | [diff] [blame] | 309 | config BF_REV_ANY |
| 310 | bool "any" |
| 311 | |
| 312 | config BF_REV_NONE |
| 313 | bool "none" |
| 314 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 315 | endchoice |
| 316 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 317 | config BF53x |
| 318 | bool |
| 319 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) |
| 320 | default y |
| 321 | |
Sonic Zhang | ffb7fc0 | 2013-09-03 16:29:00 +0800 | [diff] [blame] | 322 | config GPIO_ADI |
| 323 | def_bool y |
Linus Walleij | 57db94d | 2017-10-11 11:57:15 +0200 | [diff] [blame] | 324 | depends on !PINCTRL |
Sonic Zhang | ffb7fc0 | 2013-09-03 16:29:00 +0800 | [diff] [blame] | 325 | depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561) |
| 326 | |
Linus Walleij | 57db94d | 2017-10-11 11:57:15 +0200 | [diff] [blame] | 327 | config PINCTRL_BLACKFIN_ADI2 |
Sonic Zhang | 741ecef | 2013-09-03 16:29:01 +0800 | [diff] [blame] | 328 | def_bool y |
Linus Walleij | 57db94d | 2017-10-11 11:57:15 +0200 | [diff] [blame] | 329 | depends on (BF54x || BF60x) |
| 330 | select PINCTRL |
| 331 | select PINCTRL_ADI2 |
Sonic Zhang | 741ecef | 2013-09-03 16:29:01 +0800 | [diff] [blame] | 332 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 333 | config MEM_MT48LC64M4A2FB_7E |
| 334 | bool |
| 335 | depends on (BFIN533_STAMP) |
| 336 | default y |
| 337 | |
| 338 | config MEM_MT48LC16M16A2TG_75 |
| 339 | bool |
| 340 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ |
Harald Krapfenbauer | 6058434 | 2009-09-10 15:12:08 +0000 | [diff] [blame] | 341 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ |
| 342 | || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ |
| 343 | || BFIN527_BLUETECHNIX_CM) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 344 | default y |
| 345 | |
| 346 | config MEM_MT48LC32M8A2_75 |
| 347 | bool |
Mike Frysinger | 084f9eb | 2010-05-20 04:26:54 +0000 | [diff] [blame] | 348 | depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 349 | default y |
| 350 | |
| 351 | config MEM_MT48LC8M32B2B5_7 |
| 352 | bool |
| 353 | depends on (BFIN561_BLUETECHNIX_CM) |
| 354 | default y |
| 355 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 356 | config MEM_MT48LC32M16A2TG_75 |
| 357 | bool |
Michael Hennerich | 8effc4a | 2010-06-15 09:51:05 +0000 | [diff] [blame] | 358 | depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 359 | default y |
| 360 | |
Graf Yang | ee48efb | 2009-06-18 04:32:04 +0000 | [diff] [blame] | 361 | config MEM_MT48H32M16LFCJ_75 |
| 362 | bool |
| 363 | depends on (BFIN526_EZBRD) |
| 364 | default y |
| 365 | |
Bob Liu | f82f16d | 2012-07-23 10:47:48 +0800 | [diff] [blame] | 366 | config MEM_MT47H64M16 |
| 367 | bool |
| 368 | depends on (BFIN609_EZKIT) |
| 369 | default y |
| 370 | |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 371 | source "arch/blackfin/mach-bf518/Kconfig" |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 372 | source "arch/blackfin/mach-bf527/Kconfig" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 373 | source "arch/blackfin/mach-bf533/Kconfig" |
| 374 | source "arch/blackfin/mach-bf561/Kconfig" |
| 375 | source "arch/blackfin/mach-bf537/Kconfig" |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 376 | source "arch/blackfin/mach-bf538/Kconfig" |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 377 | source "arch/blackfin/mach-bf548/Kconfig" |
Bob Liu | b5affb0 | 2012-05-16 17:37:24 +0800 | [diff] [blame] | 378 | source "arch/blackfin/mach-bf609/Kconfig" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 379 | |
| 380 | menu "Board customizations" |
| 381 | |
| 382 | config CMDLINE_BOOL |
| 383 | bool "Default bootloader kernel arguments" |
| 384 | |
| 385 | config CMDLINE |
| 386 | string "Initial kernel command string" |
| 387 | depends on CMDLINE_BOOL |
| 388 | default "console=ttyBF0,57600" |
| 389 | help |
| 390 | If you don't have a boot loader capable of passing a command line string |
| 391 | to the kernel, you may specify one here. As a minimum, you should specify |
| 392 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). |
| 393 | |
Mike Frysinger | 5f004c2 | 2008-04-25 02:11:24 +0800 | [diff] [blame] | 394 | config BOOT_LOAD |
| 395 | hex "Kernel load address for booting" |
| 396 | default "0x1000" |
| 397 | range 0x1000 0x20000000 |
| 398 | help |
| 399 | This option allows you to set the load address of the kernel. |
| 400 | This can be useful if you are on a board which has a small amount |
| 401 | of memory or you wish to reserve some memory at the beginning of |
| 402 | the address space. |
| 403 | |
| 404 | Note that you need to keep this value above 4k (0x1000) as this |
| 405 | memory region is used to capture NULL pointer references as well |
| 406 | as some core kernel functions. |
| 407 | |
Bob Liu | b5affb0 | 2012-05-16 17:37:24 +0800 | [diff] [blame] | 408 | config PHY_RAM_BASE_ADDRESS |
| 409 | hex "Physical RAM Base" |
| 410 | default 0x0 |
| 411 | help |
| 412 | set BF609 FPGA physical SRAM base address |
| 413 | |
Michael Hennerich | 8cc7117 | 2008-10-13 14:45:06 +0800 | [diff] [blame] | 414 | config ROM_BASE |
| 415 | hex "Kernel ROM Base" |
Mike Frysinger | 8624991 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 416 | depends on ROMKERNEL |
Barry Song | d86bfb1 | 2010-01-07 04:11:17 +0000 | [diff] [blame] | 417 | default "0x20040040" |
Bob Liu | 3003668 | 2012-05-30 15:30:27 +0800 | [diff] [blame] | 418 | range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x) |
Michael Hennerich | 8cc7117 | 2008-10-13 14:45:06 +0800 | [diff] [blame] | 419 | range 0x20000000 0x30000000 if (BF54x || BF561) |
Bob Liu | 3003668 | 2012-05-30 15:30:27 +0800 | [diff] [blame] | 420 | range 0xB0000000 0xC0000000 if (BF60x) |
Michael Hennerich | 8cc7117 | 2008-10-13 14:45:06 +0800 | [diff] [blame] | 421 | help |
Barry Song | d86bfb1 | 2010-01-07 04:11:17 +0000 | [diff] [blame] | 422 | Make sure your ROM base does not include any file-header |
| 423 | information that is prepended to the kernel. |
| 424 | |
| 425 | For example, the bootable U-Boot format (created with |
| 426 | mkimage) has a 64 byte header (0x40). So while the image |
| 427 | you write to flash might start at say 0x20080000, you have |
| 428 | to add 0x40 to get the kernel's ROM base as it will come |
| 429 | after the header. |
Michael Hennerich | 8cc7117 | 2008-10-13 14:45:06 +0800 | [diff] [blame] | 430 | |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 431 | comment "Clock/PLL Setup" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 432 | |
| 433 | config CLKIN_HZ |
Sonic Zhang | 2fb6cb4 | 2008-04-25 04:39:28 +0800 | [diff] [blame] | 434 | int "Frequency of the crystal on the board in Hz" |
Mike Frysinger | 5d1617b | 2008-04-24 05:03:26 +0800 | [diff] [blame] | 435 | default "10000000" if BFIN532_IP0X |
Mike Frysinger | d0cb9b4 | 2009-06-11 21:52:35 +0000 | [diff] [blame] | 436 | default "11059200" if BFIN533_STAMP |
| 437 | default "24576000" if PNAV10 |
| 438 | default "25000000" # most people use this |
| 439 | default "27000000" if BFIN533_EZKIT |
| 440 | default "30000000" if BFIN561_EZKIT |
Michael Hennerich | 8effc4a | 2010-06-15 09:51:05 +0000 | [diff] [blame] | 441 | default "24000000" if BFIN527_AD7160EVAL |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 442 | help |
| 443 | The frequency of CLKIN crystal oscillator on the board in Hz. |
Sonic Zhang | 2fb6cb4 | 2008-04-25 04:39:28 +0800 | [diff] [blame] | 444 | Warning: This value should match the crystal on the board. Otherwise, |
| 445 | peripherals won't work properly. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 446 | |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 447 | config BFIN_KERNEL_CLOCK |
| 448 | bool "Re-program Clocks while Kernel boots?" |
| 449 | default n |
| 450 | help |
| 451 | This option decides if kernel clocks are re-programed from the |
| 452 | bootloader settings. If the clocks are not set, the SDRAM settings |
| 453 | are also not changed, and the Bootloader does 100% of the hardware |
| 454 | configuration. |
| 455 | |
| 456 | config PLL_BYPASS |
Mike Frysinger | e4e9a7a | 2007-11-15 20:39:34 +0800 | [diff] [blame] | 457 | bool "Bypass PLL" |
Bob Liu | 7c141c1 | 2012-05-17 17:15:40 +0800 | [diff] [blame] | 458 | depends on BFIN_KERNEL_CLOCK && (!BF60x) |
Mike Frysinger | e4e9a7a | 2007-11-15 20:39:34 +0800 | [diff] [blame] | 459 | default n |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 460 | |
| 461 | config CLKIN_HALF |
| 462 | bool "Half Clock In" |
| 463 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) |
| 464 | default n |
| 465 | help |
| 466 | If this is set the clock will be divided by 2, before it goes to the PLL. |
| 467 | |
| 468 | config VCO_MULT |
| 469 | int "VCO Multiplier" |
| 470 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) |
| 471 | range 1 64 |
| 472 | default "22" if BFIN533_EZKIT |
| 473 | default "45" if BFIN533_STAMP |
Michael Hennerich | 6924dfb | 2009-12-07 13:41:28 +0000 | [diff] [blame] | 474 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 475 | default "22" if BFIN533_BLUETECHNIX_CM |
Harald Krapfenbauer | 6058434 | 2009-09-10 15:12:08 +0000 | [diff] [blame] | 476 | default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
Bob Liu | 7c141c1 | 2012-05-17 17:15:40 +0800 | [diff] [blame] | 477 | default "20" if (BFIN561_EZKIT || BF609) |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 478 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
Michael Hennerich | 8effc4a | 2010-06-15 09:51:05 +0000 | [diff] [blame] | 479 | default "25" if BFIN527_AD7160EVAL |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 480 | help |
| 481 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. |
| 482 | PLL Frequency = (Crystal Frequency) * (this setting) |
| 483 | |
| 484 | choice |
| 485 | prompt "Core Clock Divider" |
| 486 | depends on BFIN_KERNEL_CLOCK |
| 487 | default CCLK_DIV_1 |
| 488 | help |
| 489 | This sets the frequency of the core. It can be 1, 2, 4 or 8 |
| 490 | Core Frequency = (PLL frequency) / (this setting) |
| 491 | |
| 492 | config CCLK_DIV_1 |
| 493 | bool "1" |
| 494 | |
| 495 | config CCLK_DIV_2 |
| 496 | bool "2" |
| 497 | |
| 498 | config CCLK_DIV_4 |
| 499 | bool "4" |
| 500 | |
| 501 | config CCLK_DIV_8 |
| 502 | bool "8" |
| 503 | endchoice |
| 504 | |
| 505 | config SCLK_DIV |
| 506 | int "System Clock Divider" |
| 507 | depends on BFIN_KERNEL_CLOCK |
| 508 | range 1 15 |
Bob Liu | 7c141c1 | 2012-05-17 17:15:40 +0800 | [diff] [blame] | 509 | default 4 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 510 | help |
Bob Liu | 7c141c1 | 2012-05-17 17:15:40 +0800 | [diff] [blame] | 511 | This sets the frequency of the system clock (including SDRAM or DDR) on |
| 512 | !BF60x else it set the clock for system buses and provides the |
| 513 | source from which SCLK0 and SCLK1 are derived. |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 514 | This can be between 1 and 15 |
| 515 | System Clock = (PLL frequency) / (this setting) |
| 516 | |
Bob Liu | 7c141c1 | 2012-05-17 17:15:40 +0800 | [diff] [blame] | 517 | config SCLK0_DIV |
| 518 | int "System Clock0 Divider" |
| 519 | depends on BFIN_KERNEL_CLOCK && BF60x |
| 520 | range 1 15 |
| 521 | default 1 |
| 522 | help |
| 523 | This sets the frequency of the system clock0 for PVP and all other |
| 524 | peripherals not clocked by SCLK1. |
| 525 | This can be between 1 and 15 |
| 526 | System Clock0 = (System Clock) / (this setting) |
| 527 | |
| 528 | config SCLK1_DIV |
| 529 | int "System Clock1 Divider" |
| 530 | depends on BFIN_KERNEL_CLOCK && BF60x |
| 531 | range 1 15 |
| 532 | default 1 |
| 533 | help |
| 534 | This sets the frequency of the system clock1 (including SPORT, SPI and ACM). |
| 535 | This can be between 1 and 15 |
| 536 | System Clock1 = (System Clock) / (this setting) |
| 537 | |
| 538 | config DCLK_DIV |
| 539 | int "DDR Clock Divider" |
| 540 | depends on BFIN_KERNEL_CLOCK && BF60x |
| 541 | range 1 15 |
| 542 | default 2 |
| 543 | help |
| 544 | This sets the frequency of the DDR memory. |
| 545 | This can be between 1 and 15 |
| 546 | DDR Clock = (PLL frequency) / (this setting) |
| 547 | |
Mike Frysinger | 5f004c2 | 2008-04-25 02:11:24 +0800 | [diff] [blame] | 548 | choice |
| 549 | prompt "DDR SDRAM Chip Type" |
| 550 | depends on BFIN_KERNEL_CLOCK |
| 551 | depends on BF54x |
| 552 | default MEM_MT46V32M16_5B |
| 553 | |
| 554 | config MEM_MT46V32M16_6T |
| 555 | bool "MT46V32M16_6T" |
| 556 | |
| 557 | config MEM_MT46V32M16_5B |
| 558 | bool "MT46V32M16_5B" |
| 559 | endchoice |
| 560 | |
Michael Hennerich | 73feb5c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 561 | choice |
| 562 | prompt "DDR/SDRAM Timing" |
Bob Liu | 7c141c1 | 2012-05-17 17:15:40 +0800 | [diff] [blame] | 563 | depends on BFIN_KERNEL_CLOCK && !BF60x |
Michael Hennerich | 73feb5c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 564 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC |
| 565 | help |
| 566 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters |
| 567 | The calculated SDRAM timing parameters may not be 100% |
| 568 | accurate - This option is therefore marked experimental. |
| 569 | |
| 570 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC |
Kees Cook | 89a0677 | 2013-01-16 18:53:16 -0800 | [diff] [blame] | 571 | bool "Calculate Timings" |
Michael Hennerich | 73feb5c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 572 | |
| 573 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC |
| 574 | bool "Provide accurate Timings based on target SCLK" |
| 575 | help |
| 576 | Please consult the Blackfin Hardware Reference Manuals as well |
| 577 | as the memory device datasheet. |
| 578 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram |
| 579 | endchoice |
| 580 | |
| 581 | menu "Memory Init Control" |
| 582 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC |
| 583 | |
| 584 | config MEM_DDRCTL0 |
| 585 | depends on BF54x |
| 586 | hex "DDRCTL0" |
| 587 | default 0x0 |
| 588 | |
| 589 | config MEM_DDRCTL1 |
| 590 | depends on BF54x |
| 591 | hex "DDRCTL1" |
| 592 | default 0x0 |
| 593 | |
| 594 | config MEM_DDRCTL2 |
| 595 | depends on BF54x |
| 596 | hex "DDRCTL2" |
| 597 | default 0x0 |
| 598 | |
| 599 | config MEM_EBIU_DDRQUE |
| 600 | depends on BF54x |
| 601 | hex "DDRQUE" |
| 602 | default 0x0 |
| 603 | |
| 604 | config MEM_SDRRC |
| 605 | depends on !BF54x |
| 606 | hex "SDRRC" |
| 607 | default 0x0 |
| 608 | |
| 609 | config MEM_SDGCTL |
| 610 | depends on !BF54x |
| 611 | hex "SDGCTL" |
| 612 | default 0x0 |
| 613 | endmenu |
| 614 | |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 615 | # |
| 616 | # Max & Min Speeds for various Chips |
| 617 | # |
| 618 | config MAX_VCO_HZ |
| 619 | int |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 620 | default 400000000 if BF512 |
| 621 | default 400000000 if BF514 |
| 622 | default 400000000 if BF516 |
| 623 | default 400000000 if BF518 |
Mike Frysinger | 7b06263b | 2009-08-11 21:27:09 +0000 | [diff] [blame] | 624 | default 400000000 if BF522 |
| 625 | default 600000000 if BF523 |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 626 | default 400000000 if BF524 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 627 | default 600000000 if BF525 |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 628 | default 400000000 if BF526 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 629 | default 600000000 if BF527 |
| 630 | default 400000000 if BF531 |
| 631 | default 400000000 if BF532 |
| 632 | default 750000000 if BF533 |
| 633 | default 500000000 if BF534 |
| 634 | default 400000000 if BF536 |
| 635 | default 600000000 if BF537 |
Robin Getz | f72eecb | 2007-11-21 16:29:20 +0800 | [diff] [blame] | 636 | default 533333333 if BF538 |
| 637 | default 533333333 if BF539 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 638 | default 600000000 if BF542 |
Robin Getz | f72eecb | 2007-11-21 16:29:20 +0800 | [diff] [blame] | 639 | default 533333333 if BF544 |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 640 | default 600000000 if BF547 |
| 641 | default 600000000 if BF548 |
Robin Getz | f72eecb | 2007-11-21 16:29:20 +0800 | [diff] [blame] | 642 | default 533333333 if BF549 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 643 | default 600000000 if BF561 |
Bob Liu | 7c141c1 | 2012-05-17 17:15:40 +0800 | [diff] [blame] | 644 | default 800000000 if BF609 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 645 | |
| 646 | config MIN_VCO_HZ |
| 647 | int |
| 648 | default 50000000 |
| 649 | |
| 650 | config MAX_SCLK_HZ |
| 651 | int |
Bob Liu | 7c141c1 | 2012-05-17 17:15:40 +0800 | [diff] [blame] | 652 | default 200000000 if BF609 |
Robin Getz | f72eecb | 2007-11-21 16:29:20 +0800 | [diff] [blame] | 653 | default 133333333 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 654 | |
| 655 | config MIN_SCLK_HZ |
| 656 | int |
| 657 | default 27000000 |
| 658 | |
| 659 | comment "Kernel Timer/Scheduler" |
| 660 | |
| 661 | source kernel/Kconfig.hz |
| 662 | |
Anna-Maria Gleixner | dfbaec0 | 2012-05-18 16:45:45 +0000 | [diff] [blame] | 663 | config SET_GENERIC_CLOCKEVENTS |
Vitja Makarov | 8b5f79f | 2008-02-29 12:24:23 +0800 | [diff] [blame] | 664 | bool "Generic clock events" |
Vitja Makarov | 8b5f79f | 2008-02-29 12:24:23 +0800 | [diff] [blame] | 665 | default y |
Anna-Maria Gleixner | dfbaec0 | 2012-05-18 16:45:45 +0000 | [diff] [blame] | 666 | select GENERIC_CLOCKEVENTS |
Vitja Makarov | 8b5f79f | 2008-02-29 12:24:23 +0800 | [diff] [blame] | 667 | |
Yi Li | 0d152c2 | 2009-12-28 10:21:49 +0000 | [diff] [blame] | 668 | menu "Clock event device" |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 669 | depends on GENERIC_CLOCKEVENTS |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 670 | config TICKSOURCE_GPTMR0 |
Yi Li | 0d152c2 | 2009-12-28 10:21:49 +0000 | [diff] [blame] | 671 | bool "GPTimer0" |
| 672 | depends on !SMP |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 673 | select BFIN_GPTIMERS |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 674 | |
| 675 | config TICKSOURCE_CORETMR |
Yi Li | 0d152c2 | 2009-12-28 10:21:49 +0000 | [diff] [blame] | 676 | bool "Core timer" |
| 677 | default y |
| 678 | endmenu |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 679 | |
Masanari Iida | f54619f | 2014-09-18 12:09:42 +0900 | [diff] [blame] | 680 | menu "Clock source" |
Vitja Makarov | 8b5f79f | 2008-02-29 12:24:23 +0800 | [diff] [blame] | 681 | depends on GENERIC_CLOCKEVENTS |
Yi Li | 0d152c2 | 2009-12-28 10:21:49 +0000 | [diff] [blame] | 682 | config CYCLES_CLOCKSOURCE |
| 683 | bool "CYCLES" |
| 684 | default y |
Vitja Makarov | 8b5f79f | 2008-02-29 12:24:23 +0800 | [diff] [blame] | 685 | depends on !BFIN_SCRATCH_REG_CYCLES |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 686 | depends on !SMP |
Vitja Makarov | 8b5f79f | 2008-02-29 12:24:23 +0800 | [diff] [blame] | 687 | help |
| 688 | If you say Y here, you will enable support for using the 'cycles' |
| 689 | registers as a clock source. Doing so means you will be unable to |
| 690 | safely write to the 'cycles' register during runtime. You will |
| 691 | still be able to read it (such as for performance monitoring), but |
| 692 | writing the registers will most likely crash the kernel. |
| 693 | |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 694 | config GPTMR0_CLOCKSOURCE |
Yi Li | 0d152c2 | 2009-12-28 10:21:49 +0000 | [diff] [blame] | 695 | bool "GPTimer0" |
Mike Frysinger | 3aca47c | 2009-06-18 19:40:47 +0000 | [diff] [blame] | 696 | select BFIN_GPTIMERS |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 697 | depends on !TICKSOURCE_GPTMR0 |
Yi Li | 0d152c2 | 2009-12-28 10:21:49 +0000 | [diff] [blame] | 698 | endmenu |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 699 | |
Mike Frysinger | 5f004c2 | 2008-04-25 02:11:24 +0800 | [diff] [blame] | 700 | comment "Misc" |
Sonic Zhang | 971d5bc | 2008-01-27 16:32:31 +0800 | [diff] [blame] | 701 | |
Mike Frysinger | f0b5d12 | 2007-08-05 17:03:59 +0800 | [diff] [blame] | 702 | choice |
| 703 | prompt "Blackfin Exception Scratch Register" |
| 704 | default BFIN_SCRATCH_REG_RETN |
| 705 | help |
| 706 | Select the resource to reserve for the Exception handler: |
| 707 | - RETN: Non-Maskable Interrupt (NMI) |
| 708 | - RETE: Exception Return (JTAG/ICE) |
| 709 | - CYCLES: Performance counter |
| 710 | |
| 711 | If you are unsure, please select "RETN". |
| 712 | |
| 713 | config BFIN_SCRATCH_REG_RETN |
| 714 | bool "RETN" |
| 715 | help |
| 716 | Use the RETN register in the Blackfin exception handler |
| 717 | as a stack scratch register. This means you cannot |
| 718 | safely use NMI on the Blackfin while running Linux, but |
| 719 | you can debug the system with a JTAG ICE and use the |
| 720 | CYCLES performance registers. |
| 721 | |
| 722 | If you are unsure, please select "RETN". |
| 723 | |
| 724 | config BFIN_SCRATCH_REG_RETE |
| 725 | bool "RETE" |
| 726 | help |
| 727 | Use the RETE register in the Blackfin exception handler |
| 728 | as a stack scratch register. This means you cannot |
| 729 | safely use a JTAG ICE while debugging a Blackfin board, |
| 730 | but you can safely use the CYCLES performance registers |
| 731 | and the NMI. |
| 732 | |
| 733 | If you are unsure, please select "RETN". |
| 734 | |
| 735 | config BFIN_SCRATCH_REG_CYCLES |
| 736 | bool "CYCLES" |
| 737 | help |
| 738 | Use the CYCLES register in the Blackfin exception handler |
| 739 | as a stack scratch register. This means you cannot |
| 740 | safely use the CYCLES performance registers on a Blackfin |
| 741 | board at anytime, but you can debug the system with a JTAG |
| 742 | ICE and use the NMI. |
| 743 | |
| 744 | If you are unsure, please select "RETN". |
| 745 | |
| 746 | endchoice |
| 747 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 748 | endmenu |
| 749 | |
| 750 | |
| 751 | menu "Blackfin Kernel Optimizations" |
| 752 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 753 | comment "Memory Optimizations" |
| 754 | |
| 755 | config I_ENTRY_L1 |
| 756 | bool "Locate interrupt entry code in L1 Memory" |
| 757 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 758 | depends on !SMP |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 759 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 760 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
| 761 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 762 | |
| 763 | config EXCPT_IRQ_SYSC_L1 |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 764 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 765 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 766 | depends on !SMP |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 767 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 768 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 769 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 770 | (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 771 | |
| 772 | config DO_IRQ_L1 |
| 773 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" |
| 774 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 775 | depends on !SMP |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 776 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 777 | If enabled, the frequently called do_irq dispatcher function is linked |
| 778 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 779 | |
| 780 | config CORE_TIMER_IRQ_L1 |
| 781 | bool "Locate frequently called timer_interrupt() function in L1 Memory" |
| 782 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 783 | depends on !SMP |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 784 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 785 | If enabled, the frequently called timer_interrupt() function is linked |
| 786 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 787 | |
| 788 | config IDLE_L1 |
| 789 | bool "Locate frequently idle function in L1 Memory" |
| 790 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 791 | depends on !SMP |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 792 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 793 | If enabled, the frequently called idle function is linked |
| 794 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 795 | |
| 796 | config SCHEDULE_L1 |
| 797 | bool "Locate kernel schedule function in L1 Memory" |
| 798 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 799 | depends on !SMP |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 800 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 801 | If enabled, the frequently called kernel schedule is linked |
| 802 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 803 | |
| 804 | config ARITHMETIC_OPS_L1 |
| 805 | bool "Locate kernel owned arithmetic functions in L1 Memory" |
| 806 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 807 | depends on !SMP |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 808 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 809 | If enabled, arithmetic functions are linked |
| 810 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 811 | |
| 812 | config ACCESS_OK_L1 |
| 813 | bool "Locate access_ok function in L1 Memory" |
| 814 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 815 | depends on !SMP |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 816 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 817 | If enabled, the access_ok function is linked |
| 818 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 819 | |
| 820 | config MEMSET_L1 |
| 821 | bool "Locate memset function in L1 Memory" |
| 822 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 823 | depends on !SMP |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 824 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 825 | If enabled, the memset function is linked |
| 826 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 827 | |
| 828 | config MEMCPY_L1 |
| 829 | bool "Locate memcpy function in L1 Memory" |
| 830 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 831 | depends on !SMP |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 832 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 833 | If enabled, the memcpy function is linked |
| 834 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 835 | |
Robin Getz | 479ba60 | 2010-05-03 17:23:20 +0000 | [diff] [blame] | 836 | config STRCMP_L1 |
| 837 | bool "locate strcmp function in L1 Memory" |
| 838 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 839 | depends on !SMP |
Robin Getz | 479ba60 | 2010-05-03 17:23:20 +0000 | [diff] [blame] | 840 | help |
| 841 | If enabled, the strcmp function is linked |
| 842 | into L1 instruction memory (less latency). |
| 843 | |
| 844 | config STRNCMP_L1 |
| 845 | bool "locate strncmp function in L1 Memory" |
| 846 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 847 | depends on !SMP |
Robin Getz | 479ba60 | 2010-05-03 17:23:20 +0000 | [diff] [blame] | 848 | help |
| 849 | If enabled, the strncmp function is linked |
| 850 | into L1 instruction memory (less latency). |
| 851 | |
| 852 | config STRCPY_L1 |
| 853 | bool "locate strcpy function in L1 Memory" |
| 854 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 855 | depends on !SMP |
Robin Getz | 479ba60 | 2010-05-03 17:23:20 +0000 | [diff] [blame] | 856 | help |
| 857 | If enabled, the strcpy function is linked |
| 858 | into L1 instruction memory (less latency). |
| 859 | |
| 860 | config STRNCPY_L1 |
| 861 | bool "locate strncpy function in L1 Memory" |
| 862 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 863 | depends on !SMP |
Robin Getz | 479ba60 | 2010-05-03 17:23:20 +0000 | [diff] [blame] | 864 | help |
| 865 | If enabled, the strncpy function is linked |
| 866 | into L1 instruction memory (less latency). |
| 867 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 868 | config SYS_BFIN_SPINLOCK_L1 |
| 869 | bool "Locate sys_bfin_spinlock function in L1 Memory" |
| 870 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 871 | depends on !SMP |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 872 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 873 | If enabled, sys_bfin_spinlock function is linked |
| 874 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 875 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 876 | config CACHELINE_ALIGNED_L1 |
| 877 | bool "Locate cacheline_aligned data to L1 Data Memory" |
Michael Hennerich | 157cc5a | 2007-07-12 16:20:21 +0800 | [diff] [blame] | 878 | default y if !BF54x |
| 879 | default n if BF54x |
Mike Frysinger | 95fc2d8 | 2012-03-28 11:43:02 +0800 | [diff] [blame] | 880 | depends on !SMP && !BF531 && !CRC32 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 881 | help |
Matt LaPlante | 692105b | 2009-01-26 11:12:25 +0100 | [diff] [blame] | 882 | If enabled, cacheline_aligned data is linked |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 883 | into L1 data memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 884 | |
| 885 | config SYSCALL_TAB_L1 |
| 886 | bool "Locate Syscall Table L1 Data Memory" |
| 887 | default n |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 888 | depends on !SMP && !BF531 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 889 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 890 | If enabled, the Syscall LUT is linked |
| 891 | into L1 data memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 892 | |
| 893 | config CPLB_SWITCH_TAB_L1 |
| 894 | bool "Locate CPLB Switch Tables L1 Data Memory" |
| 895 | default n |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 896 | depends on !SMP && !BF531 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 897 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 898 | If enabled, the CPLB Switch Tables are linked |
| 899 | into L1 data memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 900 | |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 901 | config ICACHE_FLUSH_L1 |
| 902 | bool "Locate icache flush funcs in L1 Inst Memory" |
Mike Frysinger | 7418129 | 2010-05-27 22:46:46 +0000 | [diff] [blame] | 903 | default y |
| 904 | help |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 905 | If enabled, the Blackfin icache flushing functions are linked |
Mike Frysinger | 7418129 | 2010-05-27 22:46:46 +0000 | [diff] [blame] | 906 | into L1 instruction memory. |
| 907 | |
| 908 | Note that this might be required to address anomalies, but |
| 909 | these functions are pretty small, so it shouldn't be too bad. |
| 910 | If you are using a processor affected by an anomaly, the build |
| 911 | system will double check for you and prevent it. |
| 912 | |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 913 | config DCACHE_FLUSH_L1 |
| 914 | bool "Locate dcache flush funcs in L1 Inst Memory" |
| 915 | default y |
| 916 | depends on !SMP |
| 917 | help |
| 918 | If enabled, the Blackfin dcache flushing functions are linked |
| 919 | into L1 instruction memory. |
| 920 | |
Graf Yang | ca87b7a | 2008-10-08 17:30:01 +0800 | [diff] [blame] | 921 | config APP_STACK_L1 |
| 922 | bool "Support locating application stack in L1 Scratch Memory" |
| 923 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 924 | depends on !SMP |
Graf Yang | ca87b7a | 2008-10-08 17:30:01 +0800 | [diff] [blame] | 925 | help |
| 926 | If enabled the application stack can be located in L1 |
| 927 | scratch memory (less latency). |
| 928 | |
| 929 | Currently only works with FLAT binaries. |
| 930 | |
Mike Frysinger | 6ad2b84 | 2008-10-28 11:03:09 +0800 | [diff] [blame] | 931 | config EXCEPTION_L1_SCRATCH |
| 932 | bool "Locate exception stack in L1 Scratch Memory" |
| 933 | default n |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 934 | depends on !SMP && !APP_STACK_L1 |
Mike Frysinger | 6ad2b84 | 2008-10-28 11:03:09 +0800 | [diff] [blame] | 935 | help |
| 936 | Whenever an exception occurs, use the L1 Scratch memory for |
| 937 | stack storage. You cannot place the stacks of FLAT binaries |
| 938 | in L1 when using this option. |
| 939 | |
| 940 | If you don't use L1 Scratch, then you should say Y here. |
| 941 | |
Robin Getz | 251383c | 2008-08-14 15:12:55 +0800 | [diff] [blame] | 942 | comment "Speed Optimizations" |
| 943 | config BFIN_INS_LOWOVERHEAD |
| 944 | bool "ins[bwl] low overhead, higher interrupt latency" |
| 945 | default y |
Mike Frysinger | 820b127 | 2011-02-02 22:31:42 -0500 | [diff] [blame] | 946 | depends on !SMP |
Robin Getz | 251383c | 2008-08-14 15:12:55 +0800 | [diff] [blame] | 947 | help |
| 948 | Reads on the Blackfin are speculative. In Blackfin terms, this means |
| 949 | they can be interrupted at any time (even after they have been issued |
| 950 | on to the external bus), and re-issued after the interrupt occurs. |
| 951 | For memory - this is not a big deal, since memory does not change if |
| 952 | it sees a read. |
| 953 | |
| 954 | If a FIFO is sitting on the end of the read, it will see two reads, |
| 955 | when the core only sees one since the FIFO receives both the read |
| 956 | which is cancelled (and not delivered to the core) and the one which |
| 957 | is re-issued (which is delivered to the core). |
| 958 | |
| 959 | To solve this, interrupts are turned off before reads occur to |
| 960 | I/O space. This option controls which the overhead/latency of |
| 961 | controlling interrupts during this time |
| 962 | "n" turns interrupts off every read |
| 963 | (higher overhead, but lower interrupt latency) |
| 964 | "y" turns interrupts off every loop |
| 965 | (low overhead, but longer interrupt latency) |
| 966 | |
| 967 | default behavior is to leave this set to on (type "Y"). If you are experiencing |
| 968 | interrupt latency issues, it is safe and OK to turn this off. |
| 969 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 970 | endmenu |
| 971 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 972 | choice |
| 973 | prompt "Kernel executes from" |
| 974 | help |
| 975 | Choose the memory type that the kernel will be running in. |
| 976 | |
| 977 | config RAMKERNEL |
| 978 | bool "RAM" |
| 979 | help |
| 980 | The kernel will be resident in RAM when running. |
| 981 | |
| 982 | config ROMKERNEL |
| 983 | bool "ROM" |
| 984 | help |
| 985 | The kernel will be resident in FLASH/ROM when running. |
| 986 | |
| 987 | endchoice |
| 988 | |
Mike Frysinger | 56b4f07 | 2010-10-16 19:46:21 -0400 | [diff] [blame] | 989 | # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both |
| 990 | config XIP_KERNEL |
| 991 | bool |
| 992 | default y |
| 993 | depends on ROMKERNEL |
| 994 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 995 | source "mm/Kconfig" |
| 996 | |
Mike Frysinger | 780431e | 2007-10-21 23:37:54 +0800 | [diff] [blame] | 997 | config BFIN_GPTIMERS |
| 998 | tristate "Enable Blackfin General Purpose Timers API" |
| 999 | default n |
| 1000 | help |
| 1001 | Enable support for the General Purpose Timers API. If you |
| 1002 | are unsure, say N. |
| 1003 | |
| 1004 | To compile this driver as a module, choose M here: the module |
Pavel Machek | 4737f09 | 2009-06-05 00:44:53 +0200 | [diff] [blame] | 1005 | will be called gptimers. |
Mike Frysinger | 780431e | 2007-10-21 23:37:54 +0800 | [diff] [blame] | 1006 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1007 | choice |
Mike Frysinger | d292b00 | 2008-10-28 11:15:36 +0800 | [diff] [blame] | 1008 | prompt "Uncached DMA region" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1009 | default DMA_UNCACHED_1M |
Scott Jiang | c8d11a0 | 2012-05-18 16:27:22 -0400 | [diff] [blame] | 1010 | config DMA_UNCACHED_32M |
| 1011 | bool "Enable 32M DMA region" |
| 1012 | config DMA_UNCACHED_16M |
| 1013 | bool "Enable 16M DMA region" |
| 1014 | config DMA_UNCACHED_8M |
| 1015 | bool "Enable 8M DMA region" |
Cliff Cai | 86ad793 | 2008-05-17 16:36:52 +0800 | [diff] [blame] | 1016 | config DMA_UNCACHED_4M |
| 1017 | bool "Enable 4M DMA region" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1018 | config DMA_UNCACHED_2M |
| 1019 | bool "Enable 2M DMA region" |
| 1020 | config DMA_UNCACHED_1M |
| 1021 | bool "Enable 1M DMA region" |
Barry Song | c45c065 | 2009-12-02 09:13:36 +0000 | [diff] [blame] | 1022 | config DMA_UNCACHED_512K |
| 1023 | bool "Enable 512K DMA region" |
| 1024 | config DMA_UNCACHED_256K |
| 1025 | bool "Enable 256K DMA region" |
| 1026 | config DMA_UNCACHED_128K |
| 1027 | bool "Enable 128K DMA region" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1028 | config DMA_UNCACHED_NONE |
| 1029 | bool "Disable DMA region" |
| 1030 | endchoice |
| 1031 | |
| 1032 | |
| 1033 | comment "Cache Support" |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 1034 | |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 1035 | config BFIN_ICACHE |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1036 | bool "Enable ICACHE" |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 1037 | default y |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 1038 | config BFIN_EXTMEM_ICACHEABLE |
| 1039 | bool "Enable ICACHE for external memory" |
| 1040 | depends on BFIN_ICACHE |
| 1041 | default y |
| 1042 | config BFIN_L2_ICACHEABLE |
| 1043 | bool "Enable ICACHE for L2 SRAM" |
| 1044 | depends on BFIN_ICACHE |
Steven Miao | b0ce61d | 2012-06-01 10:29:42 +0800 | [diff] [blame] | 1045 | depends on (BF54x || BF561 || BF60x) && !SMP |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 1046 | default n |
| 1047 | |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 1048 | config BFIN_DCACHE |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1049 | bool "Enable DCACHE" |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 1050 | default y |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 1051 | config BFIN_DCACHE_BANKA |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1052 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 1053 | depends on BFIN_DCACHE && !BF531 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1054 | default n |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 1055 | config BFIN_EXTMEM_DCACHEABLE |
| 1056 | bool "Enable DCACHE for external memory" |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 1057 | depends on BFIN_DCACHE |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 1058 | default y |
Graf Yang | 5ba7667 | 2009-05-07 04:09:15 +0000 | [diff] [blame] | 1059 | choice |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 1060 | prompt "External memory DCACHE policy" |
| 1061 | depends on BFIN_EXTMEM_DCACHEABLE |
| 1062 | default BFIN_EXTMEM_WRITEBACK if !SMP |
| 1063 | default BFIN_EXTMEM_WRITETHROUGH if SMP |
| 1064 | config BFIN_EXTMEM_WRITEBACK |
Graf Yang | 5ba7667 | 2009-05-07 04:09:15 +0000 | [diff] [blame] | 1065 | bool "Write back" |
| 1066 | depends on !SMP |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 1067 | help |
| 1068 | Write Back Policy: |
| 1069 | Cached data will be written back to SDRAM only when needed. |
| 1070 | This can give a nice increase in performance, but beware of |
| 1071 | broken drivers that do not properly invalidate/flush their |
| 1072 | cache. |
Graf Yang | 5ba7667 | 2009-05-07 04:09:15 +0000 | [diff] [blame] | 1073 | |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 1074 | Write Through Policy: |
| 1075 | Cached data will always be written back to SDRAM when the |
| 1076 | cache is updated. This is a completely safe setting, but |
| 1077 | performance is worse than Write Back. |
| 1078 | |
| 1079 | If you are unsure of the options and you want to be safe, |
| 1080 | then go with Write Through. |
| 1081 | |
| 1082 | config BFIN_EXTMEM_WRITETHROUGH |
Graf Yang | 5ba7667 | 2009-05-07 04:09:15 +0000 | [diff] [blame] | 1083 | bool "Write through" |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 1084 | help |
| 1085 | Write Back Policy: |
| 1086 | Cached data will be written back to SDRAM only when needed. |
| 1087 | This can give a nice increase in performance, but beware of |
| 1088 | broken drivers that do not properly invalidate/flush their |
| 1089 | cache. |
Graf Yang | 5ba7667 | 2009-05-07 04:09:15 +0000 | [diff] [blame] | 1090 | |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 1091 | Write Through Policy: |
| 1092 | Cached data will always be written back to SDRAM when the |
| 1093 | cache is updated. This is a completely safe setting, but |
| 1094 | performance is worse than Write Back. |
| 1095 | |
| 1096 | If you are unsure of the options and you want to be safe, |
| 1097 | then go with Write Through. |
Graf Yang | 5ba7667 | 2009-05-07 04:09:15 +0000 | [diff] [blame] | 1098 | |
| 1099 | endchoice |
Sonic Zhang | f099f39 | 2008-10-09 14:11:57 +0800 | [diff] [blame] | 1100 | |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 1101 | config BFIN_L2_DCACHEABLE |
| 1102 | bool "Enable DCACHE for L2 SRAM" |
| 1103 | depends on BFIN_DCACHE |
Bob Liu | b5affb0 | 2012-05-16 17:37:24 +0800 | [diff] [blame] | 1104 | depends on (BF54x || BF561 || BF60x) && !SMP |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 1105 | default n |
| 1106 | choice |
| 1107 | prompt "L2 SRAM DCACHE policy" |
| 1108 | depends on BFIN_L2_DCACHEABLE |
| 1109 | default BFIN_L2_WRITEBACK |
| 1110 | config BFIN_L2_WRITEBACK |
| 1111 | bool "Write back" |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 1112 | |
| 1113 | config BFIN_L2_WRITETHROUGH |
| 1114 | bool "Write through" |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 1115 | endchoice |
| 1116 | |
| 1117 | |
| 1118 | comment "Memory Protection Unit" |
Bernd Schmidt | b97b8a9 | 2008-01-27 18:39:16 +0800 | [diff] [blame] | 1119 | config MPU |
Kees Cook | 89a0677 | 2013-01-16 18:53:16 -0800 | [diff] [blame] | 1120 | bool "Enable the memory protection unit" |
Bernd Schmidt | b97b8a9 | 2008-01-27 18:39:16 +0800 | [diff] [blame] | 1121 | default n |
| 1122 | help |
| 1123 | Use the processor's MPU to protect applications from accessing |
| 1124 | memory they do not own. This comes at a performance penalty |
| 1125 | and is recommended only for debugging. |
| 1126 | |
Matt LaPlante | 692105b | 2009-01-26 11:12:25 +0100 | [diff] [blame] | 1127 | comment "Asynchronous Memory Configuration" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1128 | |
Mike Frysinger | ddf416b | 2007-10-10 18:06:47 +0800 | [diff] [blame] | 1129 | menu "EBIU_AMGCTL Global Control" |
Bob Liu | b5affb0 | 2012-05-16 17:37:24 +0800 | [diff] [blame] | 1130 | depends on !BF60x |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1131 | config C_AMCKEN |
| 1132 | bool "Enable CLKOUT" |
| 1133 | default y |
| 1134 | |
| 1135 | config C_CDPRIO |
| 1136 | bool "DMA has priority over core for ext. accesses" |
| 1137 | default n |
| 1138 | |
| 1139 | config C_B0PEN |
| 1140 | depends on BF561 |
| 1141 | bool "Bank 0 16 bit packing enable" |
| 1142 | default y |
| 1143 | |
| 1144 | config C_B1PEN |
| 1145 | depends on BF561 |
| 1146 | bool "Bank 1 16 bit packing enable" |
| 1147 | default y |
| 1148 | |
| 1149 | config C_B2PEN |
| 1150 | depends on BF561 |
| 1151 | bool "Bank 2 16 bit packing enable" |
| 1152 | default y |
| 1153 | |
| 1154 | config C_B3PEN |
| 1155 | depends on BF561 |
| 1156 | bool "Bank 3 16 bit packing enable" |
| 1157 | default n |
| 1158 | |
| 1159 | choice |
Matt LaPlante | 692105b | 2009-01-26 11:12:25 +0100 | [diff] [blame] | 1160 | prompt "Enable Asynchronous Memory Banks" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1161 | default C_AMBEN_ALL |
| 1162 | |
| 1163 | config C_AMBEN |
| 1164 | bool "Disable All Banks" |
| 1165 | |
| 1166 | config C_AMBEN_B0 |
| 1167 | bool "Enable Bank 0" |
| 1168 | |
| 1169 | config C_AMBEN_B0_B1 |
| 1170 | bool "Enable Bank 0 & 1" |
| 1171 | |
| 1172 | config C_AMBEN_B0_B1_B2 |
| 1173 | bool "Enable Bank 0 & 1 & 2" |
| 1174 | |
| 1175 | config C_AMBEN_ALL |
| 1176 | bool "Enable All Banks" |
| 1177 | endchoice |
| 1178 | endmenu |
| 1179 | |
| 1180 | menu "EBIU_AMBCTL Control" |
Bob Liu | b5affb0 | 2012-05-16 17:37:24 +0800 | [diff] [blame] | 1181 | depends on !BF60x |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1182 | config BANK_0 |
Mike Frysinger | c8342f8 | 2009-03-31 00:18:35 +0000 | [diff] [blame] | 1183 | hex "Bank 0 (AMBCTL0.L)" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1184 | default 0x7BB0 |
Mike Frysinger | c8342f8 | 2009-03-31 00:18:35 +0000 | [diff] [blame] | 1185 | help |
| 1186 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are |
| 1187 | used to control the Asynchronous Memory Bank 0 settings. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1188 | |
| 1189 | config BANK_1 |
Mike Frysinger | c8342f8 | 2009-03-31 00:18:35 +0000 | [diff] [blame] | 1190 | hex "Bank 1 (AMBCTL0.H)" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1191 | default 0x7BB0 |
Michael Hennerich | 197fba5 | 2008-05-07 17:03:27 +0800 | [diff] [blame] | 1192 | default 0x5558 if BF54x |
Mike Frysinger | c8342f8 | 2009-03-31 00:18:35 +0000 | [diff] [blame] | 1193 | help |
| 1194 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are |
| 1195 | used to control the Asynchronous Memory Bank 1 settings. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1196 | |
| 1197 | config BANK_2 |
Mike Frysinger | c8342f8 | 2009-03-31 00:18:35 +0000 | [diff] [blame] | 1198 | hex "Bank 2 (AMBCTL1.L)" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1199 | default 0x7BB0 |
Mike Frysinger | c8342f8 | 2009-03-31 00:18:35 +0000 | [diff] [blame] | 1200 | help |
| 1201 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are |
| 1202 | used to control the Asynchronous Memory Bank 2 settings. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1203 | |
| 1204 | config BANK_3 |
Mike Frysinger | c8342f8 | 2009-03-31 00:18:35 +0000 | [diff] [blame] | 1205 | hex "Bank 3 (AMBCTL1.H)" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1206 | default 0x99B3 |
Mike Frysinger | c8342f8 | 2009-03-31 00:18:35 +0000 | [diff] [blame] | 1207 | help |
| 1208 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are |
| 1209 | used to control the Asynchronous Memory Bank 3 settings. |
| 1210 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1211 | endmenu |
| 1212 | |
Sonic Zhang | e40540b | 2007-11-21 23:49:52 +0800 | [diff] [blame] | 1213 | config EBIU_MBSCTLVAL |
| 1214 | hex "EBIU Bank Select Control Register" |
| 1215 | depends on BF54x |
| 1216 | default 0 |
| 1217 | |
| 1218 | config EBIU_MODEVAL |
| 1219 | hex "Flash Memory Mode Control Register" |
| 1220 | depends on BF54x |
| 1221 | default 1 |
| 1222 | |
| 1223 | config EBIU_FCTLVAL |
| 1224 | hex "Flash Memory Bank Control Register" |
| 1225 | depends on BF54x |
| 1226 | default 6 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1227 | endmenu |
| 1228 | |
| 1229 | ############################################################################# |
| 1230 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" |
| 1231 | |
| 1232 | config PCI |
| 1233 | bool "PCI support" |
Adrian Bunk | a95ca3b | 2008-08-27 10:55:05 +0800 | [diff] [blame] | 1234 | depends on BROKEN |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1235 | help |
| 1236 | Support for PCI bus. |
| 1237 | |
| 1238 | source "drivers/pci/Kconfig" |
| 1239 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1240 | source "drivers/pcmcia/Kconfig" |
| 1241 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1242 | endmenu |
| 1243 | |
| 1244 | menu "Executable file formats" |
| 1245 | |
| 1246 | source "fs/Kconfig.binfmt" |
| 1247 | |
| 1248 | endmenu |
| 1249 | |
| 1250 | menu "Power management options" |
Graf Yang | ad46163 | 2009-08-07 03:52:54 +0000 | [diff] [blame] | 1251 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1252 | source "kernel/power/Kconfig" |
| 1253 | |
Johannes Berg | f4cb570 | 2007-12-08 02:14:00 +0100 | [diff] [blame] | 1254 | config ARCH_SUSPEND_POSSIBLE |
| 1255 | def_bool y |
Johannes Berg | f4cb570 | 2007-12-08 02:14:00 +0100 | [diff] [blame] | 1256 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1257 | choice |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 1258 | prompt "Standby Power Saving Mode" |
Steven Miao | 0fbd88c | 2012-05-17 17:29:54 +0800 | [diff] [blame] | 1259 | depends on PM && !BF60x |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1260 | default PM_BFIN_SLEEP_DEEPER |
| 1261 | config PM_BFIN_SLEEP_DEEPER |
| 1262 | bool "Sleep Deeper" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1263 | help |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1264 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic |
| 1265 | power dissipation by disabling the clock to the processor core (CCLK). |
| 1266 | Furthermore, Standby sets the internal power supply voltage (VDDINT) |
| 1267 | to 0.85 V to provide the greatest power savings, while preserving the |
| 1268 | processor state. |
| 1269 | The PLL and system clock (SCLK) continue to operate at a very low |
| 1270 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, |
| 1271 | the SDRAM is put into Self Refresh Mode. Typically an external event |
| 1272 | such as GPIO interrupt or RTC activity wakes up the processor. |
| 1273 | Various Peripherals such as UART, SPORT, PPI may not function as |
| 1274 | normal during Sleep Deeper, due to the reduced SCLK frequency. |
| 1275 | When in the sleep mode, system DMA access to L1 memory is not supported. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1276 | |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 1277 | If unsure, select "Sleep Deeper". |
| 1278 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1279 | config PM_BFIN_SLEEP |
| 1280 | bool "Sleep" |
| 1281 | help |
| 1282 | Sleep Mode (High Power Savings) - The sleep mode reduces power |
| 1283 | dissipation by disabling the clock to the processor core (CCLK). |
| 1284 | The PLL and system clock (SCLK), however, continue to operate in |
| 1285 | this mode. Typically an external event or RTC activity will wake |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 1286 | up the processor. When in the sleep mode, system DMA access to L1 |
| 1287 | memory is not supported. |
| 1288 | |
| 1289 | If unsure, select "Sleep Deeper". |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1290 | endchoice |
| 1291 | |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 1292 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
| 1293 | depends on PM |
| 1294 | |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 1295 | config PM_BFIN_WAKE_PH6 |
| 1296 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 1297 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 1298 | default n |
| 1299 | help |
| 1300 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) |
| 1301 | |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 1302 | config PM_BFIN_WAKE_GP |
| 1303 | bool "Allow Wake-Up from GPIOs" |
| 1304 | depends on PM && BF54x |
| 1305 | default n |
| 1306 | help |
| 1307 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) |
Michael Hennerich | 1998628 | 2009-03-05 16:45:55 +0800 | [diff] [blame] | 1308 | (all processors, except ADSP-BF549). This option sets |
| 1309 | the general-purpose wake-up enable (GPWE) control bit to enable |
| 1310 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. |
Masanari Iida | 59bf896 | 2012-04-18 00:01:21 +0900 | [diff] [blame] | 1311 | On ADSP-BF549 this option enables the same functionality on the |
Michael Hennerich | 1998628 | 2009-03-05 16:45:55 +0800 | [diff] [blame] | 1312 | /MRXON pin also PH7. |
| 1313 | |
Steven Miao | 0fbd88c | 2012-05-17 17:29:54 +0800 | [diff] [blame] | 1314 | config PM_BFIN_WAKE_PA15 |
| 1315 | bool "Allow Wake-Up from PA15" |
| 1316 | depends on PM && BF60x |
| 1317 | default n |
| 1318 | help |
| 1319 | Enable PA15 Wake-Up |
| 1320 | |
| 1321 | config PM_BFIN_WAKE_PA15_POL |
| 1322 | int "Wake-up priority" |
| 1323 | depends on PM_BFIN_WAKE_PA15 |
| 1324 | default 0 |
| 1325 | help |
| 1326 | Wake-Up priority 0(low) 1(high) |
| 1327 | |
| 1328 | config PM_BFIN_WAKE_PB15 |
| 1329 | bool "Allow Wake-Up from PB15" |
| 1330 | depends on PM && BF60x |
| 1331 | default n |
| 1332 | help |
| 1333 | Enable PB15 Wake-Up |
| 1334 | |
| 1335 | config PM_BFIN_WAKE_PB15_POL |
| 1336 | int "Wake-up priority" |
| 1337 | depends on PM_BFIN_WAKE_PB15 |
| 1338 | default 0 |
| 1339 | help |
| 1340 | Wake-Up priority 0(low) 1(high) |
| 1341 | |
| 1342 | config PM_BFIN_WAKE_PC15 |
| 1343 | bool "Allow Wake-Up from PC15" |
| 1344 | depends on PM && BF60x |
| 1345 | default n |
| 1346 | help |
| 1347 | Enable PC15 Wake-Up |
| 1348 | |
| 1349 | config PM_BFIN_WAKE_PC15_POL |
| 1350 | int "Wake-up priority" |
| 1351 | depends on PM_BFIN_WAKE_PC15 |
| 1352 | default 0 |
| 1353 | help |
| 1354 | Wake-Up priority 0(low) 1(high) |
| 1355 | |
| 1356 | config PM_BFIN_WAKE_PD06 |
| 1357 | bool "Allow Wake-Up from PD06(ETH0_PHYINT)" |
| 1358 | depends on PM && BF60x |
| 1359 | default n |
| 1360 | help |
| 1361 | Enable PD06(ETH0_PHYINT) Wake-up |
| 1362 | |
| 1363 | config PM_BFIN_WAKE_PD06_POL |
| 1364 | int "Wake-up priority" |
| 1365 | depends on PM_BFIN_WAKE_PD06 |
| 1366 | default 0 |
| 1367 | help |
| 1368 | Wake-Up priority 0(low) 1(high) |
| 1369 | |
| 1370 | config PM_BFIN_WAKE_PE12 |
| 1371 | bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)" |
| 1372 | depends on PM && BF60x |
| 1373 | default n |
| 1374 | help |
| 1375 | Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up |
| 1376 | |
| 1377 | config PM_BFIN_WAKE_PE12_POL |
| 1378 | int "Wake-up priority" |
| 1379 | depends on PM_BFIN_WAKE_PE12 |
| 1380 | default 0 |
| 1381 | help |
| 1382 | Wake-Up priority 0(low) 1(high) |
| 1383 | |
| 1384 | config PM_BFIN_WAKE_PG04 |
| 1385 | bool "Allow Wake-Up from PG04(CAN0_RX)" |
| 1386 | depends on PM && BF60x |
| 1387 | default n |
| 1388 | help |
| 1389 | Enable PG04(CAN0_RX) Wake-up |
| 1390 | |
| 1391 | config PM_BFIN_WAKE_PG04_POL |
| 1392 | int "Wake-up priority" |
| 1393 | depends on PM_BFIN_WAKE_PG04 |
| 1394 | default 0 |
| 1395 | help |
| 1396 | Wake-Up priority 0(low) 1(high) |
| 1397 | |
| 1398 | config PM_BFIN_WAKE_PG13 |
| 1399 | bool "Allow Wake-Up from PG13" |
| 1400 | depends on PM && BF60x |
| 1401 | default n |
| 1402 | help |
| 1403 | Enable PG13 Wake-Up |
| 1404 | |
| 1405 | config PM_BFIN_WAKE_PG13_POL |
| 1406 | int "Wake-up priority" |
| 1407 | depends on PM_BFIN_WAKE_PG13 |
| 1408 | default 0 |
| 1409 | help |
| 1410 | Wake-Up priority 0(low) 1(high) |
| 1411 | |
| 1412 | config PM_BFIN_WAKE_USB |
| 1413 | bool "Allow Wake-Up from (USB)" |
| 1414 | depends on PM && BF60x |
| 1415 | default n |
| 1416 | help |
| 1417 | Enable (USB) Wake-up |
| 1418 | |
| 1419 | config PM_BFIN_WAKE_USB_POL |
| 1420 | int "Wake-up priority" |
| 1421 | depends on PM_BFIN_WAKE_USB |
| 1422 | default 0 |
| 1423 | help |
| 1424 | Wake-Up priority 0(low) 1(high) |
| 1425 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1426 | endmenu |
| 1427 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1428 | menu "CPU Frequency scaling" |
| 1429 | |
| 1430 | source "drivers/cpufreq/Kconfig" |
| 1431 | |
Michael Hennerich | 5ad2ca5 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1432 | config BFIN_CPU_FREQ |
| 1433 | bool |
| 1434 | depends on CPU_FREQ |
Michael Hennerich | 5ad2ca5 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1435 | default y |
| 1436 | |
Michael Hennerich | 14b0320 | 2008-05-07 11:41:26 +0800 | [diff] [blame] | 1437 | config CPU_VOLTAGE |
| 1438 | bool "CPU Voltage scaling" |
Michael Hennerich | 14b0320 | 2008-05-07 11:41:26 +0800 | [diff] [blame] | 1439 | depends on CPU_FREQ |
| 1440 | default n |
| 1441 | help |
| 1442 | Say Y here if you want CPU voltage scaling according to the CPU frequency. |
| 1443 | This option violates the PLL BYPASS recommendation in the Blackfin Processor |
Michael Hennerich | 73feb5c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1444 | manuals. There is a theoretical risk that during VDDINT transitions |
Michael Hennerich | 14b0320 | 2008-05-07 11:41:26 +0800 | [diff] [blame] | 1445 | the PLL may unlock. |
| 1446 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1447 | endmenu |
| 1448 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1449 | source "net/Kconfig" |
| 1450 | |
| 1451 | source "drivers/Kconfig" |
| 1452 | |
Mike Frysinger | 872d024 | 2009-10-06 04:49:07 +0000 | [diff] [blame] | 1453 | source "drivers/firmware/Kconfig" |
| 1454 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1455 | source "fs/Kconfig" |
| 1456 | |
Mike Frysinger | 74ce832 | 2007-11-21 23:50:49 +0800 | [diff] [blame] | 1457 | source "arch/blackfin/Kconfig.debug" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1458 | |
| 1459 | source "security/Kconfig" |
| 1460 | |
| 1461 | source "crypto/Kconfig" |
| 1462 | |
| 1463 | source "lib/Kconfig" |