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Zhang Le3a639132008-10-27 23:33:24 +00001/*
2 * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
Wu Zhangjinf7a904d2010-01-04 17:16:51 +08003 * Copyright (c) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
Zhang Le3a639132008-10-27 23:33:24 +00004 *
5 * This program is free software; you can redistribute it
6 * and/or modify it under the terms of the GNU General
7 * Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your
9 * option) any later version.
Zhang Le3a639132008-10-27 23:33:24 +000010 */
11
Wu Zhangjin8e497112009-07-02 23:26:08 +080012#ifndef __ASM_MACH_LOONGSON_PCI_H_
13#define __ASM_MACH_LOONGSON_PCI_H_
Wu Zhangjin5e983ff2009-07-02 23:23:03 +080014
Wu Zhangjine2fee572009-10-16 14:17:19 +080015extern struct pci_ops loongson_pci_ops;
Zhang Le3a639132008-10-27 23:33:24 +000016
Wu Zhangjin6f7a2512009-11-06 18:45:05 +080017/* this is an offset from mips_io_port_base */
18#define LOONGSON_PCI_IO_START 0x00004000UL
19
Wu Zhangjin55045ff2009-11-11 13:39:12 +080020#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
Wu Zhangjin6f7a2512009-11-06 18:45:05 +080021
22/*
23 * we use address window2 to map cpu address space to pci space
24 * window2: cpu [1G, 2G] -> pci [1G, 2G]
25 * why not use window 0 & 1? because they are used by cpu when booting.
26 * window0: cpu [0, 256M] -> ddr [0, 256M]
27 * window1: cpu [256M, 512M] -> pci [256M, 512M]
28 */
29
30/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
31#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */
32#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC
33
34#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST
35#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */
36
37#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \
38 LOONGSON_PCI_MEM_START + 1)
39
40#else /* loongson2f/32bit & loongson2e */
Wu Zhangjin85749d22009-07-02 23:26:45 +080041
42/* this pci memory space is mapped by pcimap in pci.c */
Wu Zhangjine2fee572009-10-16 14:17:19 +080043#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE
44#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
Wu Zhangjin85749d22009-07-02 23:26:45 +080045/* this is an offset from mips_io_port_base */
46#define LOONGSON_PCI_IO_START 0x00004000UL
47
Wu Zhangjin55045ff2009-11-11 13:39:12 +080048#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
Zhang Le3a639132008-10-27 23:33:24 +000049
Wu Zhangjin8e497112009-07-02 23:26:08 +080050#endif /* !__ASM_MACH_LOONGSON_PCI_H_ */