blob: af1ed7d24a1fbb20fd7e1fffba8ebb1f12bbcca5 [file] [log] [blame]
Sumit Semwalb7ee79a2011-01-24 06:21:54 +00001/*
2 * OMAP2plus display device setup / initialization.
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Senthilvadivu Guruswamy
6 * Sumit Semwal
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
Paul Gortmakerd44b28c2011-07-31 10:52:44 -040018#include <linux/string.h>
Sumit Semwalb7ee79a2011-01-24 06:21:54 +000019#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24#include <linux/err.h>
Tony Lindgrendeee6d52011-12-06 17:50:42 +010025#include <linux/delay.h>
Sumit Semwalb7ee79a2011-01-24 06:21:54 +000026
Tomi Valkeinena0b38cc2011-05-11 14:05:07 +030027#include <video/omapdss.h>
Senthilvadivu Guruswamycf07f532011-01-24 06:21:56 +000028#include <plat/omap_hwmod.h>
29#include <plat/omap_device.h>
Tomi Valkeinen700dee72011-05-23 15:50:47 +030030#include <plat/omap-pm.h>
Tony Lindgrendeee6d52011-12-06 17:50:42 +010031#include "common.h"
Sumit Semwalb7ee79a2011-01-24 06:21:54 +000032
Tony Lindgrenee0839c2012-02-24 10:34:35 -080033#include "iomap.h"
Mythri P Kee9dfd82012-01-02 14:02:37 +053034#include "mux.h"
Tomi Valkeinendc358352011-06-15 15:22:47 +030035#include "control.h"
Archit Tanejab923d402011-10-06 18:04:08 -060036#include "display.h"
37
38#define DISPC_CONTROL 0x0040
39#define DISPC_CONTROL2 0x0238
Chandrabhanu Mahapatra465698e2012-06-28 15:14:02 +053040#define DISPC_CONTROL3 0x0848
Archit Tanejab923d402011-10-06 18:04:08 -060041#define DISPC_IRQSTATUS 0x0018
42
43#define DSS_SYSCONFIG 0x10
44#define DSS_SYSSTATUS 0x14
45#define DSS_CONTROL 0x40
46#define DSS_SDI_CONTROL 0x44
47#define DSS_PLL_CONTROL 0x48
48
49#define LCD_EN_MASK (0x1 << 0)
50#define DIGIT_EN_MASK (0x1 << 1)
51
52#define FRAMEDONE_IRQ_SHIFT 0
53#define EVSYNC_EVEN_IRQ_SHIFT 2
54#define EVSYNC_ODD_IRQ_SHIFT 3
55#define FRAMEDONE2_IRQ_SHIFT 22
Chandrabhanu Mahapatra465698e2012-06-28 15:14:02 +053056#define FRAMEDONE3_IRQ_SHIFT 30
Archit Tanejab923d402011-10-06 18:04:08 -060057#define FRAMEDONETV_IRQ_SHIFT 24
58
59/*
60 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
61 * reset before deciding that something has gone wrong
62 */
63#define FRAMEDONE_IRQ_TIMEOUT 100
Tomi Valkeinendc358352011-06-15 15:22:47 +030064
Sumit Semwalb7ee79a2011-01-24 06:21:54 +000065static struct platform_device omap_display_device = {
66 .name = "omapdss",
67 .id = -1,
68 .dev = {
69 .platform_data = NULL,
70 },
71};
72
Archit Taneja179e0452011-04-18 09:32:13 +053073struct omap_dss_hwmod_data {
74 const char *oh_name;
75 const char *dev_name;
76 const int id;
77};
78
79static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
80 { "dss_core", "omapdss_dss", -1 },
81 { "dss_dispc", "omapdss_dispc", -1 },
82 { "dss_rfbi", "omapdss_rfbi", -1 },
83 { "dss_venc", "omapdss_venc", -1 },
84};
85
86static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
87 { "dss_core", "omapdss_dss", -1 },
88 { "dss_dispc", "omapdss_dispc", -1 },
89 { "dss_rfbi", "omapdss_rfbi", -1 },
90 { "dss_venc", "omapdss_venc", -1 },
Tomi Valkeinen7c68dd92011-08-03 14:00:57 +030091 { "dss_dsi1", "omapdss_dsi", 0 },
Archit Taneja179e0452011-04-18 09:32:13 +053092};
93
94static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
95 { "dss_core", "omapdss_dss", -1 },
96 { "dss_dispc", "omapdss_dispc", -1 },
97 { "dss_rfbi", "omapdss_rfbi", -1 },
98 { "dss_venc", "omapdss_venc", -1 },
Tomi Valkeinen7c68dd92011-08-03 14:00:57 +030099 { "dss_dsi1", "omapdss_dsi", 0 },
100 { "dss_dsi2", "omapdss_dsi", 1 },
Archit Taneja179e0452011-04-18 09:32:13 +0530101 { "dss_hdmi", "omapdss_hdmi", -1 },
102};
103
Tomi Valkeinene8a30b22012-03-19 20:03:15 -0700104static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
Mythri P Kee9dfd82012-01-02 14:02:37 +0530105{
Mythri P K9a901682012-01-02 14:02:38 +0530106 u32 reg;
107 u16 control_i2c_1;
108
Mythri P Kee9dfd82012-01-02 14:02:37 +0530109 omap_mux_init_signal("hdmi_cec",
110 OMAP_PIN_INPUT_PULLUP);
Mythri P Kee9dfd82012-01-02 14:02:37 +0530111 omap_mux_init_signal("hdmi_ddc_scl",
112 OMAP_PIN_INPUT_PULLUP);
113 omap_mux_init_signal("hdmi_ddc_sda",
114 OMAP_PIN_INPUT_PULLUP);
Mythri P K9a901682012-01-02 14:02:38 +0530115
116 /*
117 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
118 * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
119 * internal pull up resistor.
120 */
121 if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
122 control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
123 reg = omap4_ctrl_pad_readl(control_i2c_1);
124 reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
125 OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
126 omap4_ctrl_pad_writel(reg, control_i2c_1);
127 }
Mythri P Kee9dfd82012-01-02 14:02:37 +0530128}
129
Tomi Valkeinene8a30b22012-03-19 20:03:15 -0700130static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
Tomi Valkeinendc358352011-06-15 15:22:47 +0300131{
132 u32 enable_mask, enable_shift;
133 u32 pipd_mask, pipd_shift;
134 u32 reg;
135
136 if (dsi_id == 0) {
137 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
138 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
139 pipd_mask = OMAP4_DSI1_PIPD_MASK;
140 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
141 } else if (dsi_id == 1) {
142 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
143 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
144 pipd_mask = OMAP4_DSI2_PIPD_MASK;
145 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
146 } else {
147 return -ENODEV;
148 }
149
150 reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
151
152 reg &= ~enable_mask;
153 reg &= ~pipd_mask;
154
155 reg |= (lanes << enable_shift) & enable_mask;
156 reg |= (lanes << pipd_shift) & pipd_mask;
157
158 omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
159
160 return 0;
161}
162
Tony Lindgrend1589f02012-02-20 09:43:30 -0800163int __init omap_hdmi_init(enum omap_hdmi_flags flags)
Mythri P Kee9dfd82012-01-02 14:02:37 +0530164{
165 if (cpu_is_omap44xx())
Mythri P K9a901682012-01-02 14:02:38 +0530166 omap4_hdmi_mux_pads(flags);
Mythri P Kee9dfd82012-01-02 14:02:37 +0530167
168 return 0;
169}
170
Tomi Valkeinene8a30b22012-03-19 20:03:15 -0700171static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
Tomi Valkeinen5bc416c2011-06-15 15:21:12 +0300172{
Tomi Valkeinendc358352011-06-15 15:22:47 +0300173 if (cpu_is_omap44xx())
174 return omap4_dsi_mux_pads(dsi_id, lane_mask);
175
Tomi Valkeinen5bc416c2011-06-15 15:21:12 +0300176 return 0;
177}
178
Tomi Valkeinene8a30b22012-03-19 20:03:15 -0700179static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
Tomi Valkeinen5bc416c2011-06-15 15:21:12 +0300180{
Tomi Valkeinendc358352011-06-15 15:22:47 +0300181 if (cpu_is_omap44xx())
182 omap4_dsi_mux_pads(dsi_id, 0);
Tomi Valkeinen5bc416c2011-06-15 15:21:12 +0300183}
184
Tomi Valkeinen62c1dcf2012-03-08 12:37:58 +0200185static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
186{
187 return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
188}
189
Tomi Valkeinen966eaed2012-02-17 17:15:58 +0200190static struct platform_device *create_dss_pdev(const char *pdev_name,
191 int pdev_id, const char *oh_name, void *pdata, int pdata_len,
192 struct platform_device *parent)
193{
194 struct platform_device *pdev;
195 struct omap_device *od;
196 struct omap_hwmod *ohs[1];
197 struct omap_hwmod *oh;
198 int r;
199
200 oh = omap_hwmod_lookup(oh_name);
201 if (!oh) {
202 pr_err("Could not look up %s\n", oh_name);
203 r = -ENODEV;
204 goto err;
205 }
206
207 pdev = platform_device_alloc(pdev_name, pdev_id);
208 if (!pdev) {
209 pr_err("Could not create pdev for %s\n", pdev_name);
210 r = -ENOMEM;
211 goto err;
212 }
213
214 if (parent != NULL)
215 pdev->dev.parent = &parent->dev;
216
217 if (pdev->id != -1)
218 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
219 else
220 dev_set_name(&pdev->dev, "%s", pdev->name);
221
222 ohs[0] = oh;
223 od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
224 if (!od) {
225 pr_err("Could not alloc omap_device for %s\n", pdev_name);
226 r = -ENOMEM;
227 goto err;
228 }
229
230 r = platform_device_add_data(pdev, pdata, pdata_len);
231 if (r) {
232 pr_err("Could not set pdata for %s\n", pdev_name);
233 goto err;
234 }
235
236 r = omap_device_register(pdev);
237 if (r) {
238 pr_err("Could not register omap_device for %s\n", pdev_name);
239 goto err;
240 }
241
242 return pdev;
243
244err:
245 return ERR_PTR(r);
246}
247
Tomi Valkeinen53f576a2012-03-07 13:09:43 +0200248static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
249 int pdev_id, void *pdata, int pdata_len,
250 struct platform_device *parent)
251{
252 struct platform_device *pdev;
253 int r;
254
255 pdev = platform_device_alloc(pdev_name, pdev_id);
256 if (!pdev) {
257 pr_err("Could not create pdev for %s\n", pdev_name);
258 r = -ENOMEM;
259 goto err;
260 }
261
262 if (parent != NULL)
263 pdev->dev.parent = &parent->dev;
264
265 if (pdev->id != -1)
266 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
267 else
268 dev_set_name(&pdev->dev, "%s", pdev->name);
269
270 r = platform_device_add_data(pdev, pdata, pdata_len);
271 if (r) {
272 pr_err("Could not set pdata for %s\n", pdev_name);
273 goto err;
274 }
275
Tomi Valkeinenc3a21fc2012-06-05 13:17:32 +0300276 r = platform_device_add(pdev);
Tomi Valkeinen53f576a2012-03-07 13:09:43 +0200277 if (r) {
Tomi Valkeinenc3a21fc2012-06-05 13:17:32 +0300278 pr_err("Could not register platform_device for %s\n", pdev_name);
Tomi Valkeinen53f576a2012-03-07 13:09:43 +0200279 goto err;
280 }
281
282 return pdev;
283
284err:
285 return ERR_PTR(r);
286}
287
Sumit Semwalb7ee79a2011-01-24 06:21:54 +0000288int __init omap_display_init(struct omap_dss_board_info *board_data)
289{
290 int r = 0;
Kevin Hilman3528c582011-07-21 13:48:45 -0700291 struct platform_device *pdev;
Archit Taneja179e0452011-04-18 09:32:13 +0530292 int i, oh_count;
Archit Taneja179e0452011-04-18 09:32:13 +0530293 const struct omap_dss_hwmod_data *curr_dss_hwmod;
Tomi Valkeinen966eaed2012-02-17 17:15:58 +0200294 struct platform_device *dss_pdev;
Senthilvadivu Guruswamycf07f532011-01-24 06:21:56 +0000295
Tomi Valkeinen00928ea2012-02-20 11:50:06 +0200296 /* create omapdss device */
297
298 board_data->dsi_enable_pads = omap_dsi_enable_pads;
299 board_data->dsi_disable_pads = omap_dsi_disable_pads;
300 board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
301 board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
302
303 omap_display_device.dev.platform_data = board_data;
304
305 r = platform_device_register(&omap_display_device);
306 if (r < 0) {
307 pr_err("Unable to register omapdss device\n");
308 return r;
309 }
310
311 /* create devices for dss hwmods */
Senthilvadivu Guruswamycf07f532011-01-24 06:21:56 +0000312
Archit Taneja179e0452011-04-18 09:32:13 +0530313 if (cpu_is_omap24xx()) {
314 curr_dss_hwmod = omap2_dss_hwmod_data;
315 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
316 } else if (cpu_is_omap34xx()) {
317 curr_dss_hwmod = omap3_dss_hwmod_data;
318 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
319 } else {
320 curr_dss_hwmod = omap4_dss_hwmod_data;
321 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
322 }
Mayuresh Janorkar545376e2011-01-27 11:17:04 +0000323
Tomi Valkeinen966eaed2012-02-17 17:15:58 +0200324 /*
325 * First create the pdev for dss_core, which is used as a parent device
326 * by the other dss pdevs. Note: dss_core has to be the first item in
327 * the hwmod list.
328 */
329 dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
330 curr_dss_hwmod[0].id,
331 curr_dss_hwmod[0].oh_name,
Tomi Valkeinen35deca32012-03-01 15:45:53 +0200332 board_data, sizeof(*board_data),
Tomi Valkeinen966eaed2012-02-17 17:15:58 +0200333 NULL);
Semwal, Sumitfd4b34f2011-03-01 02:42:13 -0600334
Tomi Valkeinen966eaed2012-02-17 17:15:58 +0200335 if (IS_ERR(dss_pdev)) {
336 pr_err("Could not build omap_device for %s\n",
337 curr_dss_hwmod[0].oh_name);
338
339 return PTR_ERR(dss_pdev);
340 }
341
342 for (i = 1; i < oh_count; i++) {
343 pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
344 curr_dss_hwmod[i].id,
345 curr_dss_hwmod[i].oh_name,
Tomi Valkeinen35deca32012-03-01 15:45:53 +0200346 board_data, sizeof(*board_data),
Tomi Valkeinen966eaed2012-02-17 17:15:58 +0200347 dss_pdev);
Senthilvadivu Guruswamycf07f532011-01-24 06:21:56 +0000348
Tomi Valkeinen966eaed2012-02-17 17:15:58 +0200349 if (IS_ERR(pdev)) {
350 pr_err("Could not build omap_device for %s\n",
351 curr_dss_hwmod[i].oh_name);
352
353 return PTR_ERR(pdev);
354 }
Senthilvadivu Guruswamycf07f532011-01-24 06:21:56 +0000355 }
Sumit Semwalb7ee79a2011-01-24 06:21:54 +0000356
Tomi Valkeinen53f576a2012-03-07 13:09:43 +0200357 /* Create devices for DPI and SDI */
358
Tomi Valkeinen35deca32012-03-01 15:45:53 +0200359 pdev = create_simple_dss_pdev("omapdss_dpi", -1,
360 board_data, sizeof(*board_data), dss_pdev);
Tomi Valkeinen53f576a2012-03-07 13:09:43 +0200361 if (IS_ERR(pdev)) {
362 pr_err("Could not build platform_device for omapdss_dpi\n");
363 return PTR_ERR(pdev);
364 }
365
366 if (cpu_is_omap34xx()) {
Tomi Valkeinen35deca32012-03-01 15:45:53 +0200367 pdev = create_simple_dss_pdev("omapdss_sdi", -1,
368 board_data, sizeof(*board_data), dss_pdev);
Tomi Valkeinen53f576a2012-03-07 13:09:43 +0200369 if (IS_ERR(pdev)) {
370 pr_err("Could not build platform_device for omapdss_sdi\n");
371 return PTR_ERR(pdev);
372 }
373 }
374
Tomi Valkeinen00928ea2012-02-20 11:50:06 +0200375 return 0;
Sumit Semwalb7ee79a2011-01-24 06:21:54 +0000376}
Tomi Valkeinen13662dc2011-11-08 03:16:13 -0700377
Archit Tanejab923d402011-10-06 18:04:08 -0600378static void dispc_disable_outputs(void)
379{
380 u32 v, irq_mask = 0;
Chandrabhanu Mahapatra465698e2012-06-28 15:14:02 +0530381 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
Archit Tanejab923d402011-10-06 18:04:08 -0600382 int i;
383 struct omap_dss_dispc_dev_attr *da;
384 struct omap_hwmod *oh;
385
386 oh = omap_hwmod_lookup("dss_dispc");
387 if (!oh) {
388 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
389 return;
390 }
391
392 if (!oh->dev_attr) {
393 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
394 return;
395 }
396
397 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
398
399 /* store value of LCDENABLE and DIGITENABLE bits */
400 v = omap_hwmod_read(oh, DISPC_CONTROL);
401 lcd_en = v & LCD_EN_MASK;
402 digit_en = v & DIGIT_EN_MASK;
403
404 /* store value of LCDENABLE for LCD2 */
405 if (da->manager_count > 2) {
406 v = omap_hwmod_read(oh, DISPC_CONTROL2);
407 lcd2_en = v & LCD_EN_MASK;
408 }
409
Chandrabhanu Mahapatra465698e2012-06-28 15:14:02 +0530410 /* store value of LCDENABLE for LCD3 */
411 if (da->manager_count > 3) {
412 v = omap_hwmod_read(oh, DISPC_CONTROL3);
413 lcd3_en = v & LCD_EN_MASK;
414 }
415
416 if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
Archit Tanejab923d402011-10-06 18:04:08 -0600417 return; /* no managers currently enabled */
418
419 /*
420 * If any manager was enabled, we need to disable it before
421 * DSS clocks are disabled or DISPC module is reset
422 */
423 if (lcd_en)
424 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
425
426 if (digit_en) {
427 if (da->has_framedonetv_irq) {
428 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
429 } else {
430 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
431 1 << EVSYNC_ODD_IRQ_SHIFT;
432 }
433 }
434
435 if (lcd2_en)
436 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
Chandrabhanu Mahapatra465698e2012-06-28 15:14:02 +0530437 if (lcd3_en)
438 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
Archit Tanejab923d402011-10-06 18:04:08 -0600439
440 /*
441 * clear any previous FRAMEDONE, FRAMEDONETV,
Chandrabhanu Mahapatra465698e2012-06-28 15:14:02 +0530442 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
Archit Tanejab923d402011-10-06 18:04:08 -0600443 */
444 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
445
446 /* disable LCD and TV managers */
447 v = omap_hwmod_read(oh, DISPC_CONTROL);
448 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
449 omap_hwmod_write(v, oh, DISPC_CONTROL);
450
451 /* disable LCD2 manager */
452 if (da->manager_count > 2) {
453 v = omap_hwmod_read(oh, DISPC_CONTROL2);
454 v &= ~LCD_EN_MASK;
455 omap_hwmod_write(v, oh, DISPC_CONTROL2);
456 }
457
Chandrabhanu Mahapatra465698e2012-06-28 15:14:02 +0530458 /* disable LCD3 manager */
459 if (da->manager_count > 3) {
460 v = omap_hwmod_read(oh, DISPC_CONTROL3);
461 v &= ~LCD_EN_MASK;
462 omap_hwmod_write(v, oh, DISPC_CONTROL3);
463 }
464
Archit Tanejab923d402011-10-06 18:04:08 -0600465 i = 0;
466 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
467 irq_mask) {
468 i++;
469 if (i > FRAMEDONE_IRQ_TIMEOUT) {
Chandrabhanu Mahapatra465698e2012-06-28 15:14:02 +0530470 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
Archit Tanejab923d402011-10-06 18:04:08 -0600471 break;
472 }
473 mdelay(1);
474 }
475}
476
Tomi Valkeinen13662dc2011-11-08 03:16:13 -0700477#define MAX_MODULE_SOFTRESET_WAIT 10000
478int omap_dss_reset(struct omap_hwmod *oh)
479{
480 struct omap_hwmod_opt_clk *oc;
481 int c = 0;
482 int i, r;
483
484 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
485 pr_err("dss_core: hwmod data doesn't contain reset data\n");
486 return -EINVAL;
487 }
488
489 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
490 if (oc->_clk)
491 clk_enable(oc->_clk);
492
Archit Tanejab923d402011-10-06 18:04:08 -0600493 dispc_disable_outputs();
494
495 /* clear SDI registers */
496 if (cpu_is_omap3430()) {
497 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
498 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
499 }
500
501 /*
502 * clear DSS_CONTROL register to switch DSS clock sources to
503 * PRCM clock, if any
504 */
505 omap_hwmod_write(0x0, oh, DSS_CONTROL);
506
Tomi Valkeinen13662dc2011-11-08 03:16:13 -0700507 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
508 & SYSS_RESETDONE_MASK),
509 MAX_MODULE_SOFTRESET_WAIT, c);
510
511 if (c == MAX_MODULE_SOFTRESET_WAIT)
512 pr_warning("dss_core: waiting for reset to finish failed\n");
513 else
514 pr_debug("dss_core: softreset done\n");
515
516 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
517 if (oc->_clk)
518 clk_disable(oc->_clk);
519
520 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
521
522 return r;
523}