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Kukjin Kimcc511b82011-12-27 08:18:36 +01001/*
Sachin Kamatcbf08b92014-03-21 02:14:30 +09002 * SAMSUNG EXYNOS Flattened Device Tree enabled machine
Kukjin Kimcc511b82011-12-27 08:18:36 +01003 *
Sachin Kamatcbf08b92014-03-21 02:14:30 +09004 * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
Kukjin Kimcc511b82011-12-27 08:18:36 +01006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
Sachin Kamatcbf08b92014-03-21 02:14:30 +090012#include <linux/init.h>
Kukjin Kimcc511b82011-12-27 08:18:36 +010013#include <linux/io.h>
Sachin Kamatcbf08b92014-03-21 02:14:30 +090014#include <linux/kernel.h>
Tushar Behera334a1c72014-02-14 10:32:45 +090015#include <linux/serial_s3c.h>
Arnd Bergmann237c78b2012-01-07 12:30:20 +000016#include <linux/of.h>
Thomas Abrahame873a472012-05-15 16:25:23 +090017#include <linux/of_address.h>
Sachin Kamatcbf08b92014-03-21 02:14:30 +090018#include <linux/of_fdt.h>
19#include <linux/of_platform.h>
Bartlomiej Zolnierkiewicz35baa332013-08-30 12:15:04 +020020#include <linux/platform_device.h>
Sachin Kamatcbf08b92014-03-21 02:14:30 +090021#include <linux/pm_domain.h>
Kukjin Kimcc511b82011-12-27 08:18:36 +010022
Amit Daniel Kachhapb756a502012-03-08 02:07:41 -080023#include <asm/cacheflush.h>
Sachin Kamatcbf08b92014-03-21 02:14:30 +090024#include <asm/hardware/cache-l2x0.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/memory.h>
Kukjin Kimcc511b82011-12-27 08:18:36 +010028
Kukjin Kimcc511b82011-12-27 08:18:36 +010029#include <plat/cpu.h>
Kukjin Kimcc511b82011-12-27 08:18:36 +010030
31#include "common.h"
Sachin Kamatcbf08b92014-03-21 02:14:30 +090032#include "mfc.h"
Kukjin Kim65c9a852013-12-19 04:06:56 +090033#include "regs-pmu.h"
34
Amit Daniel Kachhap6cdeddc2012-03-08 02:09:12 -080035#define L2_AUX_VAL 0x7C470001
36#define L2_AUX_MASK 0xC200ffff
Kukjin Kimcc511b82011-12-27 08:18:36 +010037
Kukjin Kim94c7ca72012-02-11 22:15:45 +090038static struct map_desc exynos4_iodesc[] __initdata = {
39 {
Kukjin Kimcc511b82011-12-27 08:18:36 +010040 .virtual = (unsigned long)S3C_VA_SYS,
41 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
42 .length = SZ_64K,
43 .type = MT_DEVICE,
44 }, {
45 .virtual = (unsigned long)S3C_VA_TIMER,
46 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
47 .length = SZ_16K,
48 .type = MT_DEVICE,
49 }, {
50 .virtual = (unsigned long)S3C_VA_WATCHDOG,
51 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
52 .length = SZ_4K,
53 .type = MT_DEVICE,
54 }, {
55 .virtual = (unsigned long)S5P_VA_SROMC,
56 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
57 .length = SZ_4K,
58 .type = MT_DEVICE,
59 }, {
60 .virtual = (unsigned long)S5P_VA_SYSTIMER,
61 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
62 .length = SZ_4K,
63 .type = MT_DEVICE,
64 }, {
65 .virtual = (unsigned long)S5P_VA_PMU,
66 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
67 .length = SZ_64K,
68 .type = MT_DEVICE,
69 }, {
70 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
71 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
72 .length = SZ_4K,
73 .type = MT_DEVICE,
74 }, {
75 .virtual = (unsigned long)S5P_VA_GIC_CPU,
76 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
77 .length = SZ_64K,
78 .type = MT_DEVICE,
79 }, {
80 .virtual = (unsigned long)S5P_VA_GIC_DIST,
81 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
82 .length = SZ_64K,
83 .type = MT_DEVICE,
84 }, {
Kukjin Kimcc511b82011-12-27 08:18:36 +010085 .virtual = (unsigned long)S5P_VA_CMU,
86 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
87 .length = SZ_128K,
88 .type = MT_DEVICE,
89 }, {
90 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
91 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
92 .length = SZ_8K,
93 .type = MT_DEVICE,
94 }, {
95 .virtual = (unsigned long)S5P_VA_L2CC,
96 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
97 .length = SZ_4K,
98 .type = MT_DEVICE,
99 }, {
Kukjin Kimcc511b82011-12-27 08:18:36 +0100100 .virtual = (unsigned long)S5P_VA_DMC0,
101 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
MyungJoo Ham2bde0b02011-12-01 15:12:30 +0900102 .length = SZ_64K,
103 .type = MT_DEVICE,
104 }, {
105 .virtual = (unsigned long)S5P_VA_DMC1,
106 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
107 .length = SZ_64K,
Kukjin Kimcc511b82011-12-27 08:18:36 +0100108 .type = MT_DEVICE,
109 }, {
Kukjin Kimcc511b82011-12-27 08:18:36 +0100110 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
111 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
112 .length = SZ_4K,
113 .type = MT_DEVICE,
114 },
115};
116
117static struct map_desc exynos4_iodesc0[] __initdata = {
118 {
119 .virtual = (unsigned long)S5P_VA_SYSRAM,
120 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
121 .length = SZ_4K,
122 .type = MT_DEVICE,
123 },
124};
125
126static struct map_desc exynos4_iodesc1[] __initdata = {
127 {
128 .virtual = (unsigned long)S5P_VA_SYSRAM,
129 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
130 .length = SZ_4K,
131 .type = MT_DEVICE,
132 },
133};
134
Tomasz Figa41de8982012-12-11 13:58:43 +0900135static struct map_desc exynos4210_iodesc[] __initdata = {
136 {
137 .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
138 .pfn = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
139 .length = SZ_4K,
140 .type = MT_DEVICE,
141 },
142};
143
144static struct map_desc exynos4x12_iodesc[] __initdata = {
145 {
146 .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
147 .pfn = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
148 .length = SZ_4K,
149 .type = MT_DEVICE,
150 },
151};
152
153static struct map_desc exynos5250_iodesc[] __initdata = {
154 {
155 .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
156 .pfn = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
157 .length = SZ_4K,
158 .type = MT_DEVICE,
159 },
160};
161
Kukjin Kim94c7ca72012-02-11 22:15:45 +0900162static struct map_desc exynos5_iodesc[] __initdata = {
163 {
164 .virtual = (unsigned long)S3C_VA_SYS,
165 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
166 .length = SZ_64K,
167 .type = MT_DEVICE,
168 }, {
169 .virtual = (unsigned long)S3C_VA_TIMER,
170 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
171 .length = SZ_16K,
172 .type = MT_DEVICE,
173 }, {
174 .virtual = (unsigned long)S3C_VA_WATCHDOG,
175 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
176 .length = SZ_4K,
177 .type = MT_DEVICE,
178 }, {
179 .virtual = (unsigned long)S5P_VA_SROMC,
180 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
181 .length = SZ_4K,
182 .type = MT_DEVICE,
183 }, {
Kukjin Kim94c7ca72012-02-11 22:15:45 +0900184 .virtual = (unsigned long)S5P_VA_SYSRAM,
185 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
186 .length = SZ_4K,
187 .type = MT_DEVICE,
188 }, {
189 .virtual = (unsigned long)S5P_VA_CMU,
190 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
191 .length = 144 * SZ_1K,
192 .type = MT_DEVICE,
193 }, {
194 .virtual = (unsigned long)S5P_VA_PMU,
195 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
196 .length = SZ_64K,
197 .type = MT_DEVICE,
Kukjin Kim2edb36c2012-11-15 15:48:56 +0900198 },
199};
200
Sachin Kamatcbf08b92014-03-21 02:14:30 +0900201void exynos_restart(enum reboot_mode mode, const char *cmd)
Kukjin Kim94c7ca72012-02-11 22:15:45 +0900202{
Thomas Abraham60db7e52013-01-24 10:09:13 -0800203 struct device_node *np;
Sachin Kamatcbf08b92014-03-21 02:14:30 +0900204 u32 val = 0x1;
205 void __iomem *addr = EXYNOS_SWRESET;
Chander Kashyapeff4e7c2013-06-19 00:29:35 +0900206
207 if (of_machine_is_compatible("samsung,exynos5440")) {
Jungseok Lee1ba830c2013-05-25 06:33:03 +0900208 u32 status;
Thomas Abraham60db7e52013-01-24 10:09:13 -0800209 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
Jungseok Lee1ba830c2013-05-25 06:33:03 +0900210
211 addr = of_iomap(np, 0) + 0xbc;
212 status = __raw_readl(addr);
213
Thomas Abraham60db7e52013-01-24 10:09:13 -0800214 addr = of_iomap(np, 0) + 0xcc;
Jungseok Lee1ba830c2013-05-25 06:33:03 +0900215 val = __raw_readl(addr);
216
217 val = (val & 0xffff0000) | (status & 0xffff);
Kukjin Kim2edb36c2012-11-15 15:48:56 +0900218 }
219
220 __raw_writel(val, addr);
Kukjin Kim94c7ca72012-02-11 22:15:45 +0900221}
222
Bartlomiej Zolnierkiewicz35baa332013-08-30 12:15:04 +0200223static struct platform_device exynos_cpuidle = {
224 .name = "exynos_cpuidle",
225 .id = -1,
226};
227
228void __init exynos_cpuidle_init(void)
229{
230 platform_device_register(&exynos_cpuidle);
231}
232
Lukasz Majewskid568b6f2013-11-28 13:42:42 +0100233void __init exynos_cpufreq_init(void)
234{
235 platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
236}
237
Shawn Guobb13fab2012-04-26 10:35:40 +0800238void __init exynos_init_late(void)
239{
Kukjin Kim2edb36c2012-11-15 15:48:56 +0900240 if (of_machine_is_compatible("samsung,exynos5440"))
241 /* to be supported later */
242 return;
243
Sylwester Nawrocki1fd3cbc2013-12-21 06:33:30 +0900244 pm_genpd_poweroff_unused();
Tomasz Figa559ba232014-03-18 07:28:22 +0900245 exynos_pm_init();
Shawn Guobb13fab2012-04-26 10:35:40 +0800246}
247
Arnd Bergmann564d06b2013-06-19 01:36:56 +0900248static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
Thomas Abrahamf5f83c72013-04-23 22:46:53 +0900249 int depth, void *data)
250{
251 struct map_desc iodesc;
252 __be32 *reg;
253 unsigned long len;
254
255 if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
256 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
257 return 0;
258
259 reg = of_get_flat_dt_prop(node, "reg", &len);
260 if (reg == NULL || len != (sizeof(unsigned long) * 2))
261 return 0;
262
263 iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
264 iodesc.length = be32_to_cpu(reg[1]) - 1;
265 iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
266 iodesc.type = MT_DEVICE;
267 iotable_init(&iodesc, 1);
268 return 1;
269}
Thomas Abrahamf5f83c72013-04-23 22:46:53 +0900270
Kukjin Kimcc511b82011-12-27 08:18:36 +0100271/*
272 * exynos_map_io
273 *
274 * register the standard cpu IO areas
275 */
Sachin Kamat6eb84662014-03-21 02:09:39 +0900276static void __init exynos_map_io(void)
277{
Sachin Kamatcbf08b92014-03-21 02:14:30 +0900278 if (soc_is_exynos4())
Sachin Kamat6eb84662014-03-21 02:09:39 +0900279 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
280
Sachin Kamatcbf08b92014-03-21 02:14:30 +0900281 if (soc_is_exynos5())
Sachin Kamat6eb84662014-03-21 02:09:39 +0900282 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
283
284 if (soc_is_exynos4210()) {
285 if (samsung_rev() == EXYNOS4210_REV_0)
286 iotable_init(exynos4_iodesc0,
287 ARRAY_SIZE(exynos4_iodesc0));
288 else
289 iotable_init(exynos4_iodesc1,
290 ARRAY_SIZE(exynos4_iodesc1));
291 iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
292 }
293 if (soc_is_exynos4212() || soc_is_exynos4412())
294 iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
295 if (soc_is_exynos5250())
296 iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
297}
Kukjin Kimcc511b82011-12-27 08:18:36 +0100298
Arnd Bergmann0e2238e2013-06-19 01:36:47 +0900299void __init exynos_init_io(void)
Kukjin Kimcc511b82011-12-27 08:18:36 +0100300{
Doug Anderson9c1fcdc2013-06-05 13:56:33 -0700301 debug_ll_io_init();
302
Tomasz Figa04fae592013-06-15 09:13:25 +0900303 of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
Kukjin Kim2edb36c2012-11-15 15:48:56 +0900304
Kukjin Kimcc511b82011-12-27 08:18:36 +0100305 /* detect cpu id and rev. */
306 s5p_init_cpu(S5P_VA_CHIPID);
307
Sachin Kamat6eb84662014-03-21 02:09:39 +0900308 exynos_map_io();
Kukjin Kim94c7ca72012-02-11 22:15:45 +0900309}
310
Thomas Abraham9ee6af92012-05-15 15:47:40 +0900311struct bus_type exynos_subsys = {
312 .name = "exynos-core",
313 .dev_name = "exynos-core",
Kukjin Kim94c7ca72012-02-11 22:15:45 +0900314};
315
Kukjin Kim94c7ca72012-02-11 22:15:45 +0900316static int __init exynos_core_init(void)
Kukjin Kimcc511b82011-12-27 08:18:36 +0100317{
Thomas Abraham9ee6af92012-05-15 15:47:40 +0900318 return subsys_system_register(&exynos_subsys, NULL);
Kukjin Kimcc511b82011-12-27 08:18:36 +0100319}
Kukjin Kim94c7ca72012-02-11 22:15:45 +0900320core_initcall(exynos_core_init);
Kukjin Kimcc511b82011-12-27 08:18:36 +0100321
Kukjin Kimcc511b82011-12-27 08:18:36 +0100322static int __init exynos4_l2x0_cache_init(void)
323{
Il Hane1b19942012-04-05 07:59:36 -0700324 int ret;
325
Amit Daniel Kachhap6cdeddc2012-03-08 02:09:12 -0800326 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
Arnd Bergmann87107d82013-06-19 01:36:52 +0900327 if (ret)
328 return ret;
Kukjin Kimcc511b82011-12-27 08:18:36 +0100329
Arnd Bergmann39378e42014-03-13 17:25:52 +0100330 if (IS_ENABLED(CONFIG_S5P_SLEEP)) {
331 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
332 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
333 }
Kukjin Kimcc511b82011-12-27 08:18:36 +0100334 return 0;
335}
Kukjin Kimcc511b82011-12-27 08:18:36 +0100336early_initcall(exynos4_l2x0_cache_init);
Kukjin Kimcc511b82011-12-27 08:18:36 +0100337
Sachin Kamatcbf08b92014-03-21 02:14:30 +0900338static void __init exynos_dt_machine_init(void)
Kukjin Kimcc511b82011-12-27 08:18:36 +0100339{
Sachin Kamatcbf08b92014-03-21 02:14:30 +0900340 struct device_node *i2c_np;
341 const char *i2c_compat = "samsung,s3c2440-i2c";
342 unsigned int tmp;
343 int id;
Kukjin Kim94c7ca72012-02-11 22:15:45 +0900344
Sachin Kamatcbf08b92014-03-21 02:14:30 +0900345 /*
346 * Exynos5's legacy i2c controller and new high speed i2c
347 * controller have muxed interrupt sources. By default the
348 * interrupts for 4-channel HS-I2C controller are enabled.
349 * If node for first four channels of legacy i2c controller
350 * are available then re-configure the interrupts via the
351 * system register.
352 */
353 if (soc_is_exynos5()) {
354 for_each_compatible_node(i2c_np, NULL, i2c_compat) {
355 if (of_device_is_available(i2c_np)) {
356 id = of_alias_get_id(i2c_np, "i2c");
357 if (id < 4) {
358 tmp = readl(EXYNOS5_SYS_I2C_CFG);
359 writel(tmp & ~(0x1 << id),
360 EXYNOS5_SYS_I2C_CFG);
361 }
362 }
363 }
364 }
365
366 exynos_cpuidle_init();
367 exynos_cpufreq_init();
368
369 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
Kukjin Kimcc511b82011-12-27 08:18:36 +0100370}
Sachin Kamatcbf08b92014-03-21 02:14:30 +0900371
372static char const *exynos_dt_compat[] __initconst = {
Sachin Kamat48681232014-03-21 02:14:59 +0900373 "samsung,exynos4",
Sachin Kamatcbf08b92014-03-21 02:14:30 +0900374 "samsung,exynos4210",
375 "samsung,exynos4212",
376 "samsung,exynos4412",
Sachin Kamat48681232014-03-21 02:14:59 +0900377 "samsung,exynos5",
Sachin Kamatcbf08b92014-03-21 02:14:30 +0900378 "samsung,exynos5250",
379 "samsung,exynos5420",
380 "samsung,exynos5440",
381 NULL
382};
383
384static void __init exynos_reserve(void)
385{
386#ifdef CONFIG_S5P_DEV_MFC
387 int i;
388 char *mfc_mem[] = {
389 "samsung,mfc-v5",
390 "samsung,mfc-v6",
391 "samsung,mfc-v7",
392 };
393
394 for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
395 if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i]))
396 break;
397#endif
398}
399
400DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
401 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
402 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
403 .smp = smp_ops(exynos_smp_ops),
404 .map_io = exynos_init_io,
405 .init_early = exynos_firmware_init,
406 .init_machine = exynos_dt_machine_init,
407 .init_late = exynos_init_late,
408 .dt_compat = exynos_dt_compat,
409 .restart = exynos_restart,
410 .reserve = exynos_reserve,
411MACHINE_END