| Ben Dooks | 26da1bf | 2008-10-31 16:14:50 +0000 | [diff] [blame] | 1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h |
| 2 | * |
| 3 | * Copyright 2008 Openmoko, Inc. |
| 4 | * Copyright 2008 Simtec Electronics |
| 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * http://armlinux.simtec.co.uk/ |
| 7 | * |
| 8 | * GPIO Bank Q register and configuration definitions |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
| 15 | #define S3C64XX_GPQCON (S3C64XX_GPQ_BASE + 0x00) |
| 16 | #define S3C64XX_GPQDAT (S3C64XX_GPQ_BASE + 0x04) |
| 17 | #define S3C64XX_GPQPUD (S3C64XX_GPQ_BASE + 0x08) |
| 18 | #define S3C64XX_GPQCONSLP (S3C64XX_GPQ_BASE + 0x0c) |
| 19 | #define S3C64XX_GPQPUDSLP (S3C64XX_GPQ_BASE + 0x10) |
| 20 | |
| 21 | #define S3C64XX_GPQ_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) |
| 22 | #define S3C64XX_GPQ_INPUT(__gpio) (0x0 << ((__gpio) * 2)) |
| 23 | #define S3C64XX_GPQ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) |
| 24 | |
| 25 | #define S3C64XX_GPQ0_MEM0_ADDR18_RAS (0x02 << 0) |
| 26 | #define S3C64XX_GPQ0_EINT_G9_0 (0x03 << 0) |
| 27 | |
| 28 | #define S3C64XX_GPQ1_MEM0_ADDR19_CAS (0x02 << 2) |
| 29 | #define S3C64XX_GPQ1_EINT_G9_1 (0x03 << 2) |
| 30 | |
| 31 | #define S3C64XX_GPQ2_EINT_G9_2 (0x03 << 4) |
| 32 | |
| 33 | #define S3C64XX_GPQ3_EINT_G9_3 (0x03 << 6) |
| 34 | |
| 35 | #define S3C64XX_GPQ4_EINT_G9_4 (0x03 << 8) |
| 36 | |
| 37 | #define S3C64XX_GPQ5_EINT_G9_5 (0x03 << 10) |
| 38 | |
| 39 | #define S3C64XX_GPQ6_EINT_G9_6 (0x03 << 12) |
| 40 | |
| 41 | #define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC (0x02 << 14) |
| 42 | #define S3C64XX_GPQ7_EINT_G9_7 (0x03 << 14) |
| 43 | |
| 44 | #define S3C64XX_GPQ8_MEM0_ADDR16_APDMC (0x02 << 16) |
| 45 | #define S3C64XX_GPQ8_EINT_G9_8 (0x03 << 16) |
| 46 | |