Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /************************************************************************ |
ravinandan.arakali@neterion.com | 776bd20 | 2005-09-06 21:36:56 -0700 | [diff] [blame] | 2 | * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC |
Ramkrishna Vepa | 0c61ed5 | 2007-03-09 18:28:32 -0800 | [diff] [blame] | 3 | * Copyright(c) 2002-2007 Neterion Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | |
| 5 | * This software may be used and distributed according to the terms of |
| 6 | * the GNU General Public License (GPL), incorporated herein by reference. |
| 7 | * Drivers based on or derived from this code fall under the GPL and must |
| 8 | * retain the authorship, copyright and license notice. This file is not |
| 9 | * a complete program and may only be used when the entire operating |
| 10 | * system is licensed under the GPL. |
| 11 | * See the file COPYING in this distribution for more information. |
| 12 | ************************************************************************/ |
| 13 | #ifndef _S2IO_H |
| 14 | #define _S2IO_H |
| 15 | |
| 16 | #define TBD 0 |
Jiri Slaby | b7b5a12 | 2007-10-18 23:40:29 -0700 | [diff] [blame] | 17 | #define s2BIT(loc) (0x8000000000000000ULL >> (loc)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz)) |
| 19 | #define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff) |
| 20 | |
| 21 | #ifndef BOOL |
| 22 | #define BOOL int |
| 23 | #endif |
| 24 | |
| 25 | #ifndef TRUE |
| 26 | #define TRUE 1 |
| 27 | #define FALSE 0 |
| 28 | #endif |
| 29 | |
| 30 | #undef SUCCESS |
| 31 | #define SUCCESS 0 |
| 32 | #define FAILURE -1 |
Sivakumar Subramani | 19a6052 | 2007-01-31 13:30:49 -0500 | [diff] [blame] | 33 | #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL |
Sreenivasa Honnur | faa4f79 | 2008-01-24 01:45:43 -0800 | [diff] [blame] | 34 | #define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL |
Sivakumar Subramani | 19a6052 | 2007-01-31 13:30:49 -0500 | [diff] [blame] | 35 | #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100 |
Sivakumar Subramani | 9fc93a4 | 2007-02-24 01:57:32 -0500 | [diff] [blame] | 36 | #define S2IO_BIT_RESET 1 |
| 37 | #define S2IO_BIT_SET 2 |
Ananda Raju | bd1034f | 2006-04-21 19:20:22 -0400 | [diff] [blame] | 38 | #define CHECKBIT(value, nbit) (value & (1 << nbit)) |
| 39 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 40 | /* Maximum time to flicker LED when asked to identify NIC using ethtool */ |
| 41 | #define MAX_FLICKER_TIME 60000 /* 60 Secs */ |
| 42 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | /* Maximum outstanding splits to be configured into xena. */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 44 | enum { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | XENA_ONE_SPLIT_TRANSACTION = 0, |
| 46 | XENA_TWO_SPLIT_TRANSACTION = 1, |
| 47 | XENA_THREE_SPLIT_TRANSACTION = 2, |
| 48 | XENA_FOUR_SPLIT_TRANSACTION = 3, |
| 49 | XENA_EIGHT_SPLIT_TRANSACTION = 4, |
| 50 | XENA_TWELVE_SPLIT_TRANSACTION = 5, |
| 51 | XENA_SIXTEEN_SPLIT_TRANSACTION = 6, |
| 52 | XENA_THIRTYTWO_SPLIT_TRANSACTION = 7 |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 53 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4) |
| 55 | |
| 56 | /* OS concerned variables and constants */ |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 57 | #define WATCH_DOG_TIMEOUT 15*HZ |
| 58 | #define EFILL 0x1234 |
| 59 | #define ALIGN_SIZE 127 |
| 60 | #define PCIX_COMMAND_REGISTER 0x62 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | |
| 62 | /* |
| 63 | * Debug related variables. |
| 64 | */ |
| 65 | /* different debug levels. */ |
| 66 | #define ERR_DBG 0 |
| 67 | #define INIT_DBG 1 |
| 68 | #define INFO_DBG 2 |
| 69 | #define TX_DBG 3 |
| 70 | #define INTR_DBG 4 |
| 71 | |
| 72 | /* Global variable that defines the present debug level of the driver. */ |
Adrian Bunk | 26df54b | 2006-01-14 03:09:40 +0100 | [diff] [blame] | 73 | static int debug_level = ERR_DBG; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | |
| 75 | /* DEBUG message print. */ |
| 76 | #define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args) |
| 77 | |
Veena Parat | 491abf2 | 2007-07-23 02:37:14 -0400 | [diff] [blame] | 78 | #ifndef DMA_ERROR_CODE |
| 79 | #define DMA_ERROR_CODE (~(dma_addr_t)0x0) |
| 80 | #endif |
| 81 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 82 | /* Protocol assist features of the NIC */ |
| 83 | #define L3_CKSUM_OK 0xFFFF |
| 84 | #define L4_CKSUM_OK 0xFFFF |
| 85 | #define S2IO_JUMBO_SIZE 9600 |
| 86 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 87 | /* Driver statistics maintained by driver */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 88 | struct swStat { |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 89 | unsigned long long single_ecc_errs; |
| 90 | unsigned long long double_ecc_errs; |
Ananda Raju | bd1034f | 2006-04-21 19:20:22 -0400 | [diff] [blame] | 91 | unsigned long long parity_err_cnt; |
| 92 | unsigned long long serious_err_cnt; |
| 93 | unsigned long long soft_reset_cnt; |
| 94 | unsigned long long fifo_full_cnt; |
Sivakumar Subramani | 8116f3c | 2007-09-17 13:05:35 -0700 | [diff] [blame] | 95 | unsigned long long ring_full_cnt[8]; |
Ravinandan Arakali | 7d3d0439 | 2006-01-25 14:53:07 -0500 | [diff] [blame] | 96 | /* LRO statistics */ |
| 97 | unsigned long long clubbed_frms_cnt; |
| 98 | unsigned long long sending_both; |
| 99 | unsigned long long outof_sequence_pkts; |
| 100 | unsigned long long flush_max_pkts; |
| 101 | unsigned long long sum_avg_pkts_aggregated; |
| 102 | unsigned long long num_aggregations; |
Sreenivasa Honnur | c53d494 | 2007-05-10 04:18:54 -0400 | [diff] [blame] | 103 | /* Other statistics */ |
| 104 | unsigned long long mem_alloc_fail_cnt; |
Veena Parat | 491abf2 | 2007-07-23 02:37:14 -0400 | [diff] [blame] | 105 | unsigned long long pci_map_fail_cnt; |
Sreenivasa Honnur | c53d494 | 2007-05-10 04:18:54 -0400 | [diff] [blame] | 106 | unsigned long long watchdog_timer_cnt; |
Sreenivasa Honnur | 491976b | 2007-05-10 04:22:25 -0400 | [diff] [blame] | 107 | unsigned long long mem_allocated; |
| 108 | unsigned long long mem_freed; |
| 109 | unsigned long long link_up_cnt; |
| 110 | unsigned long long link_down_cnt; |
| 111 | unsigned long long link_up_time; |
| 112 | unsigned long long link_down_time; |
| 113 | |
| 114 | /* Transfer Code statistics */ |
| 115 | unsigned long long tx_buf_abort_cnt; |
| 116 | unsigned long long tx_desc_abort_cnt; |
| 117 | unsigned long long tx_parity_err_cnt; |
| 118 | unsigned long long tx_link_loss_cnt; |
| 119 | unsigned long long tx_list_proc_err_cnt; |
| 120 | |
| 121 | unsigned long long rx_parity_err_cnt; |
| 122 | unsigned long long rx_abort_cnt; |
| 123 | unsigned long long rx_parity_abort_cnt; |
| 124 | unsigned long long rx_rda_fail_cnt; |
| 125 | unsigned long long rx_unkn_prot_cnt; |
| 126 | unsigned long long rx_fcs_err_cnt; |
| 127 | unsigned long long rx_buf_size_err_cnt; |
| 128 | unsigned long long rx_rxd_corrupt_cnt; |
| 129 | unsigned long long rx_unkn_err_cnt; |
Sivakumar Subramani | 8116f3c | 2007-09-17 13:05:35 -0700 | [diff] [blame] | 130 | |
| 131 | /* Error/alarm statistics*/ |
| 132 | unsigned long long tda_err_cnt; |
| 133 | unsigned long long pfc_err_cnt; |
| 134 | unsigned long long pcc_err_cnt; |
| 135 | unsigned long long tti_err_cnt; |
| 136 | unsigned long long lso_err_cnt; |
| 137 | unsigned long long tpa_err_cnt; |
| 138 | unsigned long long sm_err_cnt; |
| 139 | unsigned long long mac_tmac_err_cnt; |
| 140 | unsigned long long mac_rmac_err_cnt; |
| 141 | unsigned long long xgxs_txgxs_err_cnt; |
| 142 | unsigned long long xgxs_rxgxs_err_cnt; |
| 143 | unsigned long long rc_err_cnt; |
| 144 | unsigned long long prc_pcix_err_cnt; |
| 145 | unsigned long long rpa_err_cnt; |
| 146 | unsigned long long rda_err_cnt; |
| 147 | unsigned long long rti_err_cnt; |
| 148 | unsigned long long mc_err_cnt; |
| 149 | |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 150 | }; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 151 | |
Ananda Raju | bd1034f | 2006-04-21 19:20:22 -0400 | [diff] [blame] | 152 | /* Xpak releated alarm and warnings */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 153 | struct xpakStat { |
Ananda Raju | bd1034f | 2006-04-21 19:20:22 -0400 | [diff] [blame] | 154 | u64 alarm_transceiver_temp_high; |
| 155 | u64 alarm_transceiver_temp_low; |
| 156 | u64 alarm_laser_bias_current_high; |
| 157 | u64 alarm_laser_bias_current_low; |
| 158 | u64 alarm_laser_output_power_high; |
| 159 | u64 alarm_laser_output_power_low; |
| 160 | u64 warn_transceiver_temp_high; |
| 161 | u64 warn_transceiver_temp_low; |
| 162 | u64 warn_laser_bias_current_high; |
| 163 | u64 warn_laser_bias_current_low; |
| 164 | u64 warn_laser_output_power_high; |
| 165 | u64 warn_laser_output_power_low; |
| 166 | u64 xpak_regs_stat; |
| 167 | u32 xpak_timer_count; |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 168 | }; |
Ananda Raju | bd1034f | 2006-04-21 19:20:22 -0400 | [diff] [blame] | 169 | |
| 170 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 171 | /* The statistics block of Xena */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 172 | struct stat_block { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 173 | /* Tx MAC statistics counters. */ |
Al Viro | 107c3a7 | 2006-08-13 15:38:04 -0400 | [diff] [blame] | 174 | __le32 tmac_data_octets; |
| 175 | __le32 tmac_frms; |
| 176 | __le64 tmac_drop_frms; |
| 177 | __le32 tmac_bcst_frms; |
| 178 | __le32 tmac_mcst_frms; |
| 179 | __le64 tmac_pause_ctrl_frms; |
| 180 | __le32 tmac_ucst_frms; |
| 181 | __le32 tmac_ttl_octets; |
| 182 | __le32 tmac_any_err_frms; |
| 183 | __le32 tmac_nucst_frms; |
| 184 | __le64 tmac_ttl_less_fb_octets; |
| 185 | __le64 tmac_vld_ip_octets; |
| 186 | __le32 tmac_drop_ip; |
| 187 | __le32 tmac_vld_ip; |
| 188 | __le32 tmac_rst_tcp; |
| 189 | __le32 tmac_icmp; |
| 190 | __le64 tmac_tcp; |
| 191 | __le32 reserved_0; |
| 192 | __le32 tmac_udp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 193 | |
| 194 | /* Rx MAC Statistics counters. */ |
Al Viro | 107c3a7 | 2006-08-13 15:38:04 -0400 | [diff] [blame] | 195 | __le32 rmac_data_octets; |
| 196 | __le32 rmac_vld_frms; |
| 197 | __le64 rmac_fcs_err_frms; |
| 198 | __le64 rmac_drop_frms; |
| 199 | __le32 rmac_vld_bcst_frms; |
| 200 | __le32 rmac_vld_mcst_frms; |
| 201 | __le32 rmac_out_rng_len_err_frms; |
| 202 | __le32 rmac_in_rng_len_err_frms; |
| 203 | __le64 rmac_long_frms; |
| 204 | __le64 rmac_pause_ctrl_frms; |
| 205 | __le64 rmac_unsup_ctrl_frms; |
| 206 | __le32 rmac_accepted_ucst_frms; |
| 207 | __le32 rmac_ttl_octets; |
| 208 | __le32 rmac_discarded_frms; |
| 209 | __le32 rmac_accepted_nucst_frms; |
| 210 | __le32 reserved_1; |
| 211 | __le32 rmac_drop_events; |
| 212 | __le64 rmac_ttl_less_fb_octets; |
| 213 | __le64 rmac_ttl_frms; |
| 214 | __le64 reserved_2; |
| 215 | __le32 rmac_usized_frms; |
| 216 | __le32 reserved_3; |
| 217 | __le32 rmac_frag_frms; |
| 218 | __le32 rmac_osized_frms; |
| 219 | __le32 reserved_4; |
| 220 | __le32 rmac_jabber_frms; |
| 221 | __le64 rmac_ttl_64_frms; |
| 222 | __le64 rmac_ttl_65_127_frms; |
| 223 | __le64 reserved_5; |
| 224 | __le64 rmac_ttl_128_255_frms; |
| 225 | __le64 rmac_ttl_256_511_frms; |
| 226 | __le64 reserved_6; |
| 227 | __le64 rmac_ttl_512_1023_frms; |
| 228 | __le64 rmac_ttl_1024_1518_frms; |
| 229 | __le32 rmac_ip; |
| 230 | __le32 reserved_7; |
| 231 | __le64 rmac_ip_octets; |
| 232 | __le32 rmac_drop_ip; |
| 233 | __le32 rmac_hdr_err_ip; |
| 234 | __le32 reserved_8; |
| 235 | __le32 rmac_icmp; |
| 236 | __le64 rmac_tcp; |
| 237 | __le32 rmac_err_drp_udp; |
| 238 | __le32 rmac_udp; |
| 239 | __le64 rmac_xgmii_err_sym; |
| 240 | __le64 rmac_frms_q0; |
| 241 | __le64 rmac_frms_q1; |
| 242 | __le64 rmac_frms_q2; |
| 243 | __le64 rmac_frms_q3; |
| 244 | __le64 rmac_frms_q4; |
| 245 | __le64 rmac_frms_q5; |
| 246 | __le64 rmac_frms_q6; |
| 247 | __le64 rmac_frms_q7; |
| 248 | __le16 rmac_full_q3; |
| 249 | __le16 rmac_full_q2; |
| 250 | __le16 rmac_full_q1; |
| 251 | __le16 rmac_full_q0; |
| 252 | __le16 rmac_full_q7; |
| 253 | __le16 rmac_full_q6; |
| 254 | __le16 rmac_full_q5; |
| 255 | __le16 rmac_full_q4; |
| 256 | __le32 reserved_9; |
| 257 | __le32 rmac_pause_cnt; |
| 258 | __le64 rmac_xgmii_data_err_cnt; |
| 259 | __le64 rmac_xgmii_ctrl_err_cnt; |
| 260 | __le32 rmac_err_tcp; |
| 261 | __le32 rmac_accepted_ip; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 262 | |
| 263 | /* PCI/PCI-X Read transaction statistics. */ |
Al Viro | 107c3a7 | 2006-08-13 15:38:04 -0400 | [diff] [blame] | 264 | __le32 new_rd_req_cnt; |
| 265 | __le32 rd_req_cnt; |
| 266 | __le32 rd_rtry_cnt; |
| 267 | __le32 new_rd_req_rtry_cnt; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 268 | |
| 269 | /* PCI/PCI-X Write/Read transaction statistics. */ |
Al Viro | 107c3a7 | 2006-08-13 15:38:04 -0400 | [diff] [blame] | 270 | __le32 wr_req_cnt; |
| 271 | __le32 wr_rtry_rd_ack_cnt; |
| 272 | __le32 new_wr_req_rtry_cnt; |
| 273 | __le32 new_wr_req_cnt; |
| 274 | __le32 wr_disc_cnt; |
| 275 | __le32 wr_rtry_cnt; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 276 | |
| 277 | /* PCI/PCI-X Write / DMA Transaction statistics. */ |
Al Viro | 107c3a7 | 2006-08-13 15:38:04 -0400 | [diff] [blame] | 278 | __le32 txp_wr_cnt; |
| 279 | __le32 rd_rtry_wr_ack_cnt; |
| 280 | __le32 txd_wr_cnt; |
| 281 | __le32 txd_rd_cnt; |
| 282 | __le32 rxd_wr_cnt; |
| 283 | __le32 rxd_rd_cnt; |
| 284 | __le32 rxf_wr_cnt; |
| 285 | __le32 txf_rd_cnt; |
raghavendra.koushik@neterion.com | 7ba013a | 2005-08-03 12:29:20 -0700 | [diff] [blame] | 286 | |
raghavendra.koushik@neterion.com | 541ae68 | 2005-08-03 12:36:55 -0700 | [diff] [blame] | 287 | /* Tx MAC statistics overflow counters. */ |
Al Viro | 107c3a7 | 2006-08-13 15:38:04 -0400 | [diff] [blame] | 288 | __le32 tmac_data_octets_oflow; |
| 289 | __le32 tmac_frms_oflow; |
| 290 | __le32 tmac_bcst_frms_oflow; |
| 291 | __le32 tmac_mcst_frms_oflow; |
| 292 | __le32 tmac_ucst_frms_oflow; |
| 293 | __le32 tmac_ttl_octets_oflow; |
| 294 | __le32 tmac_any_err_frms_oflow; |
| 295 | __le32 tmac_nucst_frms_oflow; |
| 296 | __le64 tmac_vlan_frms; |
| 297 | __le32 tmac_drop_ip_oflow; |
| 298 | __le32 tmac_vld_ip_oflow; |
| 299 | __le32 tmac_rst_tcp_oflow; |
| 300 | __le32 tmac_icmp_oflow; |
| 301 | __le32 tpa_unknown_protocol; |
| 302 | __le32 tmac_udp_oflow; |
| 303 | __le32 reserved_10; |
| 304 | __le32 tpa_parse_failure; |
raghavendra.koushik@neterion.com | 541ae68 | 2005-08-03 12:36:55 -0700 | [diff] [blame] | 305 | |
| 306 | /* Rx MAC Statistics overflow counters. */ |
Al Viro | 107c3a7 | 2006-08-13 15:38:04 -0400 | [diff] [blame] | 307 | __le32 rmac_data_octets_oflow; |
| 308 | __le32 rmac_vld_frms_oflow; |
| 309 | __le32 rmac_vld_bcst_frms_oflow; |
| 310 | __le32 rmac_vld_mcst_frms_oflow; |
| 311 | __le32 rmac_accepted_ucst_frms_oflow; |
| 312 | __le32 rmac_ttl_octets_oflow; |
| 313 | __le32 rmac_discarded_frms_oflow; |
| 314 | __le32 rmac_accepted_nucst_frms_oflow; |
| 315 | __le32 rmac_usized_frms_oflow; |
| 316 | __le32 rmac_drop_events_oflow; |
| 317 | __le32 rmac_frag_frms_oflow; |
| 318 | __le32 rmac_osized_frms_oflow; |
| 319 | __le32 rmac_ip_oflow; |
| 320 | __le32 rmac_jabber_frms_oflow; |
| 321 | __le32 rmac_icmp_oflow; |
| 322 | __le32 rmac_drop_ip_oflow; |
| 323 | __le32 rmac_err_drp_udp_oflow; |
| 324 | __le32 rmac_udp_oflow; |
| 325 | __le32 reserved_11; |
| 326 | __le32 rmac_pause_cnt_oflow; |
| 327 | __le64 rmac_ttl_1519_4095_frms; |
| 328 | __le64 rmac_ttl_4096_8191_frms; |
| 329 | __le64 rmac_ttl_8192_max_frms; |
| 330 | __le64 rmac_ttl_gt_max_frms; |
| 331 | __le64 rmac_osized_alt_frms; |
| 332 | __le64 rmac_jabber_alt_frms; |
| 333 | __le64 rmac_gt_max_alt_frms; |
| 334 | __le64 rmac_vlan_frms; |
| 335 | __le32 rmac_len_discard; |
| 336 | __le32 rmac_fcs_discard; |
| 337 | __le32 rmac_pf_discard; |
| 338 | __le32 rmac_da_discard; |
| 339 | __le32 rmac_red_discard; |
| 340 | __le32 rmac_rts_discard; |
| 341 | __le32 reserved_12; |
| 342 | __le32 rmac_ingm_full_discard; |
| 343 | __le32 reserved_13; |
| 344 | __le32 rmac_accepted_ip_oflow; |
| 345 | __le32 reserved_14; |
| 346 | __le32 link_fault_cnt; |
Ananda Raju | bd1034f | 2006-04-21 19:20:22 -0400 | [diff] [blame] | 347 | u8 buffer[20]; |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 348 | struct swStat sw_stat; |
| 349 | struct xpakStat xpak_stat; |
| 350 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 351 | |
Sivakumar Subramani | 926930b | 2007-02-24 01:59:39 -0500 | [diff] [blame] | 352 | /* Default value for 'vlan_strip_tag' configuration parameter */ |
| 353 | #define NO_STRIP_IN_PROMISC 2 |
| 354 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 355 | /* |
| 356 | * Structures representing different init time configuration |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 357 | * parameters of the NIC. |
| 358 | */ |
| 359 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 360 | #define MAX_TX_FIFOS 8 |
| 361 | #define MAX_RX_RINGS 8 |
| 362 | |
Sreenivasa Honnur | 6cfc482 | 2008-02-20 17:07:51 -0500 | [diff] [blame] | 363 | #define FIFO_DEFAULT_NUM 5 |
| 364 | #define FIFO_UDP_MAX_NUM 2 /* 0 - even, 1 -odd ports */ |
| 365 | #define FIFO_OTHER_MAX_NUM 1 |
| 366 | |
Surjit Reang | 2fda096 | 2008-01-24 02:08:59 -0800 | [diff] [blame] | 367 | |
Sreenivasa Honnur | 0cec35e | 2007-05-10 04:06:28 -0400 | [diff] [blame] | 368 | #define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 ) |
| 369 | #define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 ) |
| 370 | #define MAX_RX_DESC_3 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 ) |
| 371 | #define MAX_TX_DESC (MAX_AVAILABLE_TXDS) |
| 372 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 373 | /* FIFO mappings for all possible number of fifos configured */ |
Adrian Bunk | 26df54b | 2006-01-14 03:09:40 +0100 | [diff] [blame] | 374 | static int fifo_map[][MAX_TX_FIFOS] = { |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 375 | {0, 0, 0, 0, 0, 0, 0, 0}, |
| 376 | {0, 0, 0, 0, 1, 1, 1, 1}, |
| 377 | {0, 0, 0, 1, 1, 1, 2, 2}, |
| 378 | {0, 0, 1, 1, 2, 2, 3, 3}, |
| 379 | {0, 0, 1, 1, 2, 2, 3, 4}, |
| 380 | {0, 0, 1, 1, 2, 3, 4, 5}, |
| 381 | {0, 0, 1, 2, 3, 4, 5, 6}, |
| 382 | {0, 1, 2, 3, 4, 5, 6, 7}, |
| 383 | }; |
| 384 | |
Sreenivasa Honnur | 6cfc482 | 2008-02-20 17:07:51 -0500 | [diff] [blame] | 385 | static u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7}; |
| 386 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 387 | /* Maintains Per FIFO related information. */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 388 | struct tx_fifo_config { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 389 | #define MAX_AVAILABLE_TXDS 8192 |
| 390 | u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */ |
| 391 | /* Priority definition */ |
| 392 | #define TX_FIFO_PRI_0 0 /*Highest */ |
| 393 | #define TX_FIFO_PRI_1 1 |
| 394 | #define TX_FIFO_PRI_2 2 |
| 395 | #define TX_FIFO_PRI_3 3 |
| 396 | #define TX_FIFO_PRI_4 4 |
| 397 | #define TX_FIFO_PRI_5 5 |
| 398 | #define TX_FIFO_PRI_6 6 |
| 399 | #define TX_FIFO_PRI_7 7 /*lowest */ |
| 400 | u8 fifo_priority; /* specifies pointer level for FIFO */ |
| 401 | /* user should not set twos fifos with same pri */ |
| 402 | u8 f_no_snoop; |
| 403 | #define NO_SNOOP_TXD 0x01 |
| 404 | #define NO_SNOOP_TXD_BUFFER 0x02 |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 405 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 406 | |
| 407 | |
| 408 | /* Maintains per Ring related information */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 409 | struct rx_ring_config { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 410 | u32 num_rxd; /*No of RxDs per Rx Ring */ |
| 411 | #define RX_RING_PRI_0 0 /* highest */ |
| 412 | #define RX_RING_PRI_1 1 |
| 413 | #define RX_RING_PRI_2 2 |
| 414 | #define RX_RING_PRI_3 3 |
| 415 | #define RX_RING_PRI_4 4 |
| 416 | #define RX_RING_PRI_5 5 |
| 417 | #define RX_RING_PRI_6 6 |
| 418 | #define RX_RING_PRI_7 7 /* lowest */ |
| 419 | |
| 420 | u8 ring_priority; /*Specifies service priority of ring */ |
| 421 | /* OSM should not set any two rings with same priority */ |
| 422 | u8 ring_org; /*Organization of ring */ |
| 423 | #define RING_ORG_BUFF1 0x01 |
| 424 | #define RX_RING_ORG_BUFF3 0x03 |
| 425 | #define RX_RING_ORG_BUFF5 0x05 |
| 426 | |
| 427 | u8 f_no_snoop; |
| 428 | #define NO_SNOOP_RXD 0x01 |
| 429 | #define NO_SNOOP_RXD_BUFFER 0x02 |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 430 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 431 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 432 | /* This structure provides contains values of the tunable parameters |
| 433 | * of the H/W |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 434 | */ |
| 435 | struct config_param { |
| 436 | /* Tx Side */ |
| 437 | u32 tx_fifo_num; /*Number of Tx FIFOs */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 438 | |
Sreenivasa Honnur | 6cfc482 | 2008-02-20 17:07:51 -0500 | [diff] [blame] | 439 | /* 0-No steering, 1-Priority steering, 2-Default fifo map */ |
| 440 | #define NO_STEERING 0 |
| 441 | #define TX_PRIORITY_STEERING 0x1 |
| 442 | #define TX_DEFAULT_STEERING 0x2 |
| 443 | u8 tx_steering_type; |
| 444 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 445 | u8 fifo_mapping[MAX_TX_FIFOS]; |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 446 | struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 447 | u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */ |
| 448 | u64 tx_intr_type; |
Sivakumar Subramani | 8abc4d5 | 2007-09-15 13:11:34 -0700 | [diff] [blame] | 449 | #define INTA 0 |
| 450 | #define MSI_X 2 |
| 451 | u8 intr_type; |
Sivakumar Subramani | c77dd43 | 2007-08-06 05:36:28 -0400 | [diff] [blame] | 452 | u8 napi; |
Sivakumar Subramani | 8abc4d5 | 2007-09-15 13:11:34 -0700 | [diff] [blame] | 453 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 454 | /* Specifies if Tx Intr is UTILZ or PER_LIST type. */ |
| 455 | |
| 456 | /* Rx Side */ |
| 457 | u32 rx_ring_num; /*Number of receive rings */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 458 | #define MAX_RX_BLOCKS_PER_RING 150 |
| 459 | |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 460 | struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 461 | |
| 462 | #define HEADER_ETHERNET_II_802_3_SIZE 14 |
| 463 | #define HEADER_802_2_SIZE 3 |
| 464 | #define HEADER_SNAP_SIZE 5 |
| 465 | #define HEADER_VLAN_SIZE 4 |
| 466 | |
| 467 | #define MIN_MTU 46 |
| 468 | #define MAX_PYLD 1500 |
| 469 | #define MAX_MTU (MAX_PYLD+18) |
| 470 | #define MAX_MTU_VLAN (MAX_PYLD+22) |
| 471 | #define MAX_PYLD_JUMBO 9600 |
| 472 | #define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18) |
| 473 | #define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22) |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 474 | u16 bus_speed; |
Sreenivasa Honnur | faa4f79 | 2008-01-24 01:45:43 -0800 | [diff] [blame] | 475 | int max_mc_addr; /* xena=64 herc=256 */ |
| 476 | int max_mac_addr; /* xena=16 herc=64 */ |
| 477 | int mc_start_offset; /* xena=16 herc=64 */ |
Sreenivasa Honnur | 3a3d575 | 2008-02-20 16:44:07 -0500 | [diff] [blame] | 478 | u8 multiq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 479 | }; |
| 480 | |
| 481 | /* Structure representing MAC Addrs */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 482 | struct mac_addr { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 483 | u8 mac_addr[ETH_ALEN]; |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 484 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 485 | |
| 486 | /* Structure that represent every FIFO element in the BAR1 |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 487 | * Address location. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 488 | */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 489 | struct TxFIFO_element { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 490 | u64 TxDL_Pointer; |
| 491 | |
| 492 | u64 List_Control; |
| 493 | #define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8) |
Jiri Slaby | b7b5a12 | 2007-10-18 23:40:29 -0700 | [diff] [blame] | 494 | #define TX_FIFO_FIRST_LIST s2BIT(14) |
| 495 | #define TX_FIFO_LAST_LIST s2BIT(15) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 496 | #define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2) |
Jiri Slaby | b7b5a12 | 2007-10-18 23:40:29 -0700 | [diff] [blame] | 497 | #define TX_FIFO_SPECIAL_FUNC s2BIT(23) |
| 498 | #define TX_FIFO_DS_NO_SNOOP s2BIT(31) |
| 499 | #define TX_FIFO_BUFF_NO_SNOOP s2BIT(30) |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 500 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 501 | |
| 502 | /* Tx descriptor structure */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 503 | struct TxD { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 504 | u64 Control_1; |
| 505 | /* bit mask */ |
Jiri Slaby | b7b5a12 | 2007-10-18 23:40:29 -0700 | [diff] [blame] | 506 | #define TXD_LIST_OWN_XENA s2BIT(7) |
| 507 | #define TXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 508 | #define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE)) |
| 509 | #define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12) |
Jiri Slaby | b7b5a12 | 2007-10-18 23:40:29 -0700 | [diff] [blame] | 510 | #define TXD_GATHER_CODE (s2BIT(22) | s2BIT(23)) |
| 511 | #define TXD_GATHER_CODE_FIRST s2BIT(22) |
| 512 | #define TXD_GATHER_CODE_LAST s2BIT(23) |
| 513 | #define TXD_TCP_LSO_EN s2BIT(30) |
| 514 | #define TXD_UDP_COF_EN s2BIT(31) |
| 515 | #define TXD_UFO_EN s2BIT(31) | s2BIT(30) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 516 | #define TXD_TCP_LSO_MSS(val) vBIT(val,34,14) |
Ananda Raju | fed5ecc | 2005-11-14 15:25:08 -0500 | [diff] [blame] | 517 | #define TXD_UFO_MSS(val) vBIT(val,34,14) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 518 | #define TXD_BUFFER0_SIZE(val) vBIT(val,48,16) |
| 519 | |
| 520 | u64 Control_2; |
Jiri Slaby | b7b5a12 | 2007-10-18 23:40:29 -0700 | [diff] [blame] | 521 | #define TXD_TX_CKO_CONTROL (s2BIT(5)|s2BIT(6)|s2BIT(7)) |
| 522 | #define TXD_TX_CKO_IPV4_EN s2BIT(5) |
| 523 | #define TXD_TX_CKO_TCP_EN s2BIT(6) |
| 524 | #define TXD_TX_CKO_UDP_EN s2BIT(7) |
| 525 | #define TXD_VLAN_ENABLE s2BIT(15) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 526 | #define TXD_VLAN_TAG(val) vBIT(val,16,16) |
| 527 | #define TXD_INT_NUMBER(val) vBIT(val,34,6) |
Jiri Slaby | b7b5a12 | 2007-10-18 23:40:29 -0700 | [diff] [blame] | 528 | #define TXD_INT_TYPE_PER_LIST s2BIT(47) |
| 529 | #define TXD_INT_TYPE_UTILZ s2BIT(46) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 530 | #define TXD_SET_MARKER vBIT(0x6,0,4) |
| 531 | |
| 532 | u64 Buffer_Pointer; |
| 533 | u64 Host_Control; /* reserved for host */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 534 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 535 | |
| 536 | /* Structure to hold the phy and virt addr of every TxDL. */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 537 | struct list_info_hold { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 538 | dma_addr_t list_phy_addr; |
| 539 | void *list_virt_addr; |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 540 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 541 | |
Ananda Raju | da6971d | 2005-10-31 16:55:31 -0500 | [diff] [blame] | 542 | /* Rx descriptor structure for 1 buffer mode */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 543 | struct RxD_t { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 544 | u64 Host_Control; /* reserved for host */ |
| 545 | u64 Control_1; |
Jiri Slaby | b7b5a12 | 2007-10-18 23:40:29 -0700 | [diff] [blame] | 546 | #define RXD_OWN_XENA s2BIT(7) |
| 547 | #define RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 548 | #define RXD_FRAME_PROTO vBIT(0xFFFF,24,8) |
Sreenivasa Honnur | cdb5bf0 | 2008-02-20 17:09:15 -0500 | [diff] [blame] | 549 | #define RXD_FRAME_VLAN_TAG s2BIT(24) |
Jiri Slaby | b7b5a12 | 2007-10-18 23:40:29 -0700 | [diff] [blame] | 550 | #define RXD_FRAME_PROTO_IPV4 s2BIT(27) |
| 551 | #define RXD_FRAME_PROTO_IPV6 s2BIT(28) |
| 552 | #define RXD_FRAME_IP_FRAG s2BIT(29) |
| 553 | #define RXD_FRAME_PROTO_TCP s2BIT(30) |
| 554 | #define RXD_FRAME_PROTO_UDP s2BIT(31) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 555 | #define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP) |
| 556 | #define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF) |
| 557 | #define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF) |
| 558 | |
| 559 | u64 Control_2; |
raghavendra.koushik@neterion.com | 5e25b9d | 2005-08-03 12:27:09 -0700 | [diff] [blame] | 560 | #define THE_RXD_MARK 0x3 |
| 561 | #define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2) |
| 562 | #define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62) |
| 563 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 564 | #define MASK_VLAN_TAG vBIT(0xFFFF,48,16) |
| 565 | #define SET_VLAN_TAG(val) vBIT(val,48,16) |
| 566 | #define SET_NUM_TAG(val) vBIT(val,16,32) |
| 567 | |
Ananda Raju | da6971d | 2005-10-31 16:55:31 -0500 | [diff] [blame] | 568 | |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 569 | }; |
Ananda Raju | da6971d | 2005-10-31 16:55:31 -0500 | [diff] [blame] | 570 | /* Rx descriptor structure for 1 buffer mode */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 571 | struct RxD1 { |
| 572 | struct RxD_t h; |
Ananda Raju | da6971d | 2005-10-31 16:55:31 -0500 | [diff] [blame] | 573 | |
| 574 | #define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14) |
| 575 | #define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14) |
| 576 | #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \ |
| 577 | (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48) |
| 578 | u64 Buffer0_ptr; |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 579 | }; |
Ananda Raju | da6971d | 2005-10-31 16:55:31 -0500 | [diff] [blame] | 580 | /* Rx descriptor structure for 3 or 2 buffer mode */ |
| 581 | |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 582 | struct RxD3 { |
| 583 | struct RxD_t h; |
Ananda Raju | da6971d | 2005-10-31 16:55:31 -0500 | [diff] [blame] | 584 | |
| 585 | #define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14) |
| 586 | #define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16) |
| 587 | #define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16) |
| 588 | #define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8) |
| 589 | #define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16) |
| 590 | #define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16) |
| 591 | #define RXD_GET_BUFFER0_SIZE_3(Control_2) \ |
| 592 | (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48) |
| 593 | #define RXD_GET_BUFFER1_SIZE_3(Control_2) \ |
| 594 | (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32) |
| 595 | #define RXD_GET_BUFFER2_SIZE_3(Control_2) \ |
| 596 | (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 597 | #define BUF0_LEN 40 |
| 598 | #define BUF1_LEN 1 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 599 | |
| 600 | u64 Buffer0_ptr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 601 | u64 Buffer1_ptr; |
| 602 | u64 Buffer2_ptr; |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 603 | }; |
Ananda Raju | da6971d | 2005-10-31 16:55:31 -0500 | [diff] [blame] | 604 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 605 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 606 | /* Structure that represents the Rx descriptor block which contains |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 607 | * 128 Rx descriptors. |
| 608 | */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 609 | struct RxD_block { |
Ananda Raju | da6971d | 2005-10-31 16:55:31 -0500 | [diff] [blame] | 610 | #define MAX_RXDS_PER_BLOCK_1 127 |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 611 | struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 612 | |
| 613 | u64 reserved_0; |
| 614 | #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 615 | u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 616 | * Rxd in this blk */ |
| 617 | u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */ |
| 618 | u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 619 | * the upper 32 bits should |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 620 | * be 0 */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 621 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 623 | #define SIZE_OF_BLOCK 4096 |
| 624 | |
Sivakumar Subramani | 19a6052 | 2007-01-31 13:30:49 -0500 | [diff] [blame] | 625 | #define RXD_MODE_1 0 /* One Buffer mode */ |
Veena Parat | 6d517a2 | 2007-07-23 02:20:51 -0400 | [diff] [blame] | 626 | #define RXD_MODE_3B 1 /* Two Buffer mode */ |
Ananda Raju | da6971d | 2005-10-31 16:55:31 -0500 | [diff] [blame] | 627 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 628 | /* Structure to hold virtual addresses of Buf0 and Buf1 in |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 629 | * 2buf mode. */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 630 | struct buffAdd { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 631 | void *ba_0_org; |
| 632 | void *ba_1_org; |
| 633 | void *ba_0; |
| 634 | void *ba_1; |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 635 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 636 | |
| 637 | /* Structure which stores all the MAC control parameters */ |
| 638 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 639 | /* This structure stores the offset of the RxD in the ring |
| 640 | * from which the Rx Interrupt processor can start picking |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 641 | * up the RxDs for processing. |
| 642 | */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 643 | struct rx_curr_get_info { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 644 | u32 block_index; |
| 645 | u32 offset; |
| 646 | u32 ring_len; |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 647 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 648 | |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 649 | struct rx_curr_put_info { |
| 650 | u32 block_index; |
| 651 | u32 offset; |
| 652 | u32 ring_len; |
| 653 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 654 | |
| 655 | /* This structure stores the offset of the TxDl in the FIFO |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 656 | * from which the Tx Interrupt processor can start picking |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 657 | * up the TxDLs for send complete interrupt processing. |
| 658 | */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 659 | struct tx_curr_get_info { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 660 | u32 offset; |
| 661 | u32 fifo_len; |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 662 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 663 | |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 664 | struct tx_curr_put_info { |
| 665 | u32 offset; |
| 666 | u32 fifo_len; |
| 667 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 668 | |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 669 | struct rxd_info { |
Ananda Raju | da6971d | 2005-10-31 16:55:31 -0500 | [diff] [blame] | 670 | void *virt_addr; |
| 671 | dma_addr_t dma_addr; |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 672 | }; |
Ananda Raju | da6971d | 2005-10-31 16:55:31 -0500 | [diff] [blame] | 673 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 674 | /* Structure that holds the Phy and virt addresses of the Blocks */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 675 | struct rx_block_info { |
Ananda Raju | da6971d | 2005-10-31 16:55:31 -0500 | [diff] [blame] | 676 | void *block_virt_addr; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 677 | dma_addr_t block_dma_addr; |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 678 | struct rxd_info *rxds; |
| 679 | }; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 680 | |
| 681 | /* Ring specific structure */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 682 | struct ring_info { |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 683 | /* The ring number */ |
| 684 | int ring_no; |
| 685 | |
| 686 | /* |
| 687 | * Place holders for the virtual and physical addresses of |
| 688 | * all the Rx Blocks |
| 689 | */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 690 | struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING]; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 691 | int block_count; |
| 692 | int pkt_cnt; |
| 693 | |
| 694 | /* |
| 695 | * Put pointer info which indictes which RxD has to be replenished |
| 696 | * with a new buffer. |
| 697 | */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 698 | struct rx_curr_put_info rx_curr_put_info; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 699 | |
| 700 | /* |
| 701 | * Get pointer info which indictes which is the last RxD that was |
| 702 | * processed by the driver. |
| 703 | */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 704 | struct rx_curr_get_info rx_curr_get_info; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 705 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 706 | /* Buffer Address store. */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 707 | struct buffAdd **ba; |
| 708 | struct s2io_nic *nic; |
| 709 | }; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 710 | |
| 711 | /* Fifo specific structure */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 712 | struct fifo_info { |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 713 | /* FIFO number */ |
| 714 | int fifo_no; |
| 715 | |
| 716 | /* Maximum TxDs per TxDL */ |
| 717 | int max_txds; |
| 718 | |
| 719 | /* Place holder of all the TX List's Phy and Virt addresses. */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 720 | struct list_info_hold *list_info; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 721 | |
| 722 | /* |
| 723 | * Current offset within the tx FIFO where driver would write |
| 724 | * new Tx frame |
| 725 | */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 726 | struct tx_curr_put_info tx_curr_put_info; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 727 | |
| 728 | /* |
| 729 | * Current offset within tx FIFO from where the driver would start freeing |
| 730 | * the buffers |
| 731 | */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 732 | struct tx_curr_get_info tx_curr_get_info; |
Sreenivasa Honnur | 3a3d575 | 2008-02-20 16:44:07 -0500 | [diff] [blame] | 733 | #define FIFO_QUEUE_START 0 |
| 734 | #define FIFO_QUEUE_STOP 1 |
| 735 | int queue_state; |
| 736 | |
| 737 | /* copy of sp->dev pointer */ |
| 738 | struct net_device *dev; |
| 739 | |
| 740 | /* copy of multiq status */ |
| 741 | u8 multiq; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 742 | |
Surjit Reang | 2fda096 | 2008-01-24 02:08:59 -0800 | [diff] [blame] | 743 | /* Per fifo lock */ |
| 744 | spinlock_t tx_lock; |
| 745 | |
| 746 | /* Per fifo UFO in band structure */ |
| 747 | u64 *ufo_in_band_v; |
| 748 | |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 749 | struct s2io_nic *nic; |
Surjit Reang | 2fda096 | 2008-01-24 02:08:59 -0800 | [diff] [blame] | 750 | } ____cacheline_aligned; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 751 | |
Adrian Bunk | 47bdd71 | 2006-06-30 18:25:18 +0200 | [diff] [blame] | 752 | /* Information related to the Tx and Rx FIFOs and Rings of Xena |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 753 | * is maintained in this structure. |
| 754 | */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 755 | struct mac_info { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 756 | /* tx side stuff */ |
| 757 | /* logical pointer of start of each Tx FIFO */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 758 | struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 759 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 760 | /* Fifo specific structure */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 761 | struct fifo_info fifos[MAX_TX_FIFOS]; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 762 | |
ravinandan.arakali@neterion.com | 776bd20 | 2005-09-06 21:36:56 -0700 | [diff] [blame] | 763 | /* Save virtual address of TxD page with zero DMA addr(if any) */ |
| 764 | void *zerodma_virt_addr; |
| 765 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 766 | /* rx side stuff */ |
| 767 | /* Ring specific structure */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 768 | struct ring_info rings[MAX_RX_RINGS]; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 769 | |
| 770 | u16 rmac_pause_time; |
| 771 | u16 mc_pause_threshold_q0q3; |
| 772 | u16 mc_pause_threshold_q4q7; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 773 | |
| 774 | void *stats_mem; /* orignal pointer to allocated mem */ |
| 775 | dma_addr_t stats_mem_phy; /* Physical address of the stat block */ |
| 776 | u32 stats_mem_sz; |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 777 | struct stat_block *stats_info; /* Logical address of the stat block */ |
| 778 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 779 | |
| 780 | /* structure representing the user defined MAC addresses */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 781 | struct usr_addr { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 782 | char addr[ETH_ALEN]; |
| 783 | int usage_cnt; |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 784 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 785 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 786 | /* Default Tunable parameters of the NIC. */ |
Ananda Raju | 9dc737a | 2006-04-21 19:05:41 -0400 | [diff] [blame] | 787 | #define DEFAULT_FIFO_0_LEN 4096 |
| 788 | #define DEFAULT_FIFO_1_7_LEN 512 |
Ananda Raju | c92ca04 | 2006-04-21 19:18:03 -0400 | [diff] [blame] | 789 | #define SMALL_BLK_CNT 30 |
| 790 | #define LARGE_BLK_CNT 100 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 791 | |
Ravinandan Arakali | cc6e7c4 | 2005-10-04 06:41:24 -0400 | [diff] [blame] | 792 | /* |
| 793 | * Structure to keep track of the MSI-X vectors and the corresponding |
| 794 | * argument registered against each vector |
| 795 | */ |
| 796 | #define MAX_REQUESTED_MSI_X 17 |
| 797 | struct s2io_msix_entry |
| 798 | { |
| 799 | u16 vector; |
| 800 | u16 entry; |
| 801 | void *arg; |
| 802 | |
| 803 | u8 type; |
| 804 | #define MSIX_FIFO_TYPE 1 |
| 805 | #define MSIX_RING_TYPE 2 |
| 806 | |
| 807 | u8 in_use; |
| 808 | #define MSIX_REGISTERED_SUCCESS 0xAA |
| 809 | }; |
| 810 | |
| 811 | struct msix_info_st { |
| 812 | u64 addr; |
| 813 | u64 data; |
| 814 | }; |
| 815 | |
Ravinandan Arakali | 7d3d0439 | 2006-01-25 14:53:07 -0500 | [diff] [blame] | 816 | /* Data structure to represent a LRO session */ |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 817 | struct lro { |
Ravinandan Arakali | 7d3d0439 | 2006-01-25 14:53:07 -0500 | [diff] [blame] | 818 | struct sk_buff *parent; |
Ananda Raju | 75c30b1 | 2006-07-24 19:55:09 -0400 | [diff] [blame] | 819 | struct sk_buff *last_frag; |
Ravinandan Arakali | 7d3d0439 | 2006-01-25 14:53:07 -0500 | [diff] [blame] | 820 | u8 *l2h; |
| 821 | struct iphdr *iph; |
| 822 | struct tcphdr *tcph; |
| 823 | u32 tcp_next_seq; |
Al Viro | bd4f3ae | 2007-02-09 16:40:15 +0000 | [diff] [blame] | 824 | __be32 tcp_ack; |
Ravinandan Arakali | 7d3d0439 | 2006-01-25 14:53:07 -0500 | [diff] [blame] | 825 | int total_len; |
| 826 | int frags_len; |
| 827 | int sg_num; |
| 828 | int in_use; |
Al Viro | bd4f3ae | 2007-02-09 16:40:15 +0000 | [diff] [blame] | 829 | __be16 window; |
Sreenivasa Honnur | cdb5bf0 | 2008-02-20 17:09:15 -0500 | [diff] [blame] | 830 | u16 vlan_tag; |
Ravinandan Arakali | 7d3d0439 | 2006-01-25 14:53:07 -0500 | [diff] [blame] | 831 | u32 cur_tsval; |
Surjit Reang | c885595 | 2008-02-03 04:27:38 -0800 | [diff] [blame] | 832 | __be32 cur_tsecr; |
Ravinandan Arakali | 7d3d0439 | 2006-01-25 14:53:07 -0500 | [diff] [blame] | 833 | u8 saw_ts; |
Sreenivasa Honnur | cdb5bf0 | 2008-02-20 17:09:15 -0500 | [diff] [blame] | 834 | } ____cacheline_aligned; |
Ravinandan Arakali | 7d3d0439 | 2006-01-25 14:53:07 -0500 | [diff] [blame] | 835 | |
Sivakumar Subramani | 92b8443 | 2007-09-06 06:51:14 -0400 | [diff] [blame] | 836 | /* These flags represent the devices temporary state */ |
| 837 | enum s2io_device_state_t |
| 838 | { |
| 839 | __S2IO_STATE_LINK_TASK=0, |
| 840 | __S2IO_STATE_CARD_UP |
| 841 | }; |
| 842 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 843 | /* Structure representing one instance of the NIC */ |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 844 | struct s2io_nic { |
Ananda Raju | da6971d | 2005-10-31 16:55:31 -0500 | [diff] [blame] | 845 | int rxd_mode; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 846 | /* |
| 847 | * Count of packets to be processed in a given iteration, it will be indicated |
| 848 | * by the quota field of the device structure when NAPI is enabled. |
| 849 | */ |
| 850 | int pkts_to_process; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 851 | struct net_device *dev; |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 852 | struct napi_struct napi; |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 853 | struct mac_info mac_control; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 854 | struct config_param config; |
| 855 | struct pci_dev *pdev; |
| 856 | void __iomem *bar0; |
| 857 | void __iomem *bar1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 858 | #define MAX_MAC_SUPPORTED 16 |
| 859 | #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED |
| 860 | |
Sreenivasa Honnur | faa4f79 | 2008-01-24 01:45:43 -0800 | [diff] [blame] | 861 | struct mac_addr def_mac_addr[256]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 862 | |
| 863 | struct net_device_stats stats; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 864 | int high_dma_flag; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 865 | int device_enabled_once; |
| 866 | |
Ananda Raju | c92ca04 | 2006-04-21 19:18:03 -0400 | [diff] [blame] | 867 | char name[60]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 868 | |
raghavendra.koushik@neterion.com | 25fff88 | 2005-08-03 12:34:11 -0700 | [diff] [blame] | 869 | /* Timer that handles I/O errors/exceptions */ |
| 870 | struct timer_list alarm_timer; |
| 871 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 872 | /* Space to back up the PCI config space */ |
| 873 | u32 config_space[256 / sizeof(u32)]; |
| 874 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 875 | atomic_t rx_bufs_left[MAX_RX_RINGS]; |
| 876 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 877 | #define PROMISC 1 |
| 878 | #define ALL_MULTI 2 |
| 879 | |
| 880 | #define MAX_ADDRS_SUPPORTED 64 |
| 881 | u16 usr_addr_count; |
| 882 | u16 mc_addr_count; |
Sreenivasa Honnur | faa4f79 | 2008-01-24 01:45:43 -0800 | [diff] [blame] | 883 | struct usr_addr usr_addrs[256]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 884 | |
| 885 | u16 m_cast_flg; |
| 886 | u16 all_multi_pos; |
| 887 | u16 promisc_flg; |
| 888 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 889 | /* Id timer, used to blink NIC to physically identify NIC. */ |
| 890 | struct timer_list id_timer; |
| 891 | |
| 892 | /* Restart timer, used to restart NIC if the device is stuck and |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 893 | * a schedule task that will set the correct Link state once the |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 894 | * NIC's PHY has stabilized after a state change. |
| 895 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 896 | struct work_struct rst_timer_task; |
| 897 | struct work_struct set_link_task; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 898 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 899 | /* Flag that can be used to turn on or turn off the Rx checksum |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 900 | * offload feature. |
| 901 | */ |
| 902 | int rx_csum; |
| 903 | |
Sreenivasa Honnur | 6cfc482 | 2008-02-20 17:07:51 -0500 | [diff] [blame] | 904 | /* Below variables are used for fifo selection to transmit a packet */ |
| 905 | u16 fifo_selector[MAX_TX_FIFOS]; |
| 906 | |
| 907 | /* Total fifos for tcp packets */ |
| 908 | u8 total_tcp_fifos; |
| 909 | |
| 910 | /* |
| 911 | * Beginning index of udp for udp packets |
| 912 | * Value will be equal to |
| 913 | * (tx_fifo_num - FIFO_UDP_MAX_NUM - FIFO_OTHER_MAX_NUM) |
| 914 | */ |
| 915 | u8 udp_fifo_idx; |
| 916 | |
| 917 | u8 total_udp_fifos; |
| 918 | |
| 919 | /* |
| 920 | * Beginning index of fifo for all other packets |
| 921 | * Value will be equal to (tx_fifo_num - FIFO_OTHER_MAX_NUM) |
| 922 | */ |
| 923 | u8 other_fifo_idx; |
| 924 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 925 | /* after blink, the adapter must be restored with original |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 926 | * values. |
| 927 | */ |
| 928 | u64 adapt_ctrl_org; |
| 929 | |
| 930 | /* Last known link state. */ |
| 931 | u16 last_link_state; |
| 932 | #define LINK_DOWN 1 |
| 933 | #define LINK_UP 2 |
| 934 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 935 | int task_flag; |
Sreenivasa Honnur | 491976b | 2007-05-10 04:22:25 -0400 | [diff] [blame] | 936 | unsigned long long start_time; |
raghavendra.koushik@neterion.com | be3a6b0 | 2005-08-03 12:35:55 -0700 | [diff] [blame] | 937 | struct vlan_group *vlgrp; |
Ravinandan Arakali | cc6e7c4 | 2005-10-04 06:41:24 -0400 | [diff] [blame] | 938 | #define MSIX_FLG 0xA5 |
| 939 | struct msix_entry *entries; |
Sivakumar Subramani | 8abc4d5 | 2007-09-15 13:11:34 -0700 | [diff] [blame] | 940 | int msi_detected; |
| 941 | wait_queue_head_t msi_wait; |
Ravinandan Arakali | cc6e7c4 | 2005-10-04 06:41:24 -0400 | [diff] [blame] | 942 | struct s2io_msix_entry *s2io_entries; |
Ananda Raju | e6a8fee | 2006-07-06 23:58:23 -0700 | [diff] [blame] | 943 | char desc[MAX_REQUESTED_MSI_X][25]; |
Ravinandan Arakali | cc6e7c4 | 2005-10-04 06:41:24 -0400 | [diff] [blame] | 944 | |
Ananda Raju | c92ca04 | 2006-04-21 19:18:03 -0400 | [diff] [blame] | 945 | int avail_msix_vectors; /* No. of MSI-X vectors granted by system */ |
| 946 | |
Ravinandan Arakali | cc6e7c4 | 2005-10-04 06:41:24 -0400 | [diff] [blame] | 947 | struct msix_info_st msix_info[0x3f]; |
| 948 | |
raghavendra.koushik@neterion.com | 541ae68 | 2005-08-03 12:36:55 -0700 | [diff] [blame] | 949 | #define XFRAME_I_DEVICE 1 |
| 950 | #define XFRAME_II_DEVICE 2 |
| 951 | u8 device_type; |
raghavendra.koushik@neterion.com | be3a6b0 | 2005-08-03 12:35:55 -0700 | [diff] [blame] | 952 | |
Ravinandan Arakali | 7d3d0439 | 2006-01-25 14:53:07 -0500 | [diff] [blame] | 953 | #define MAX_LRO_SESSIONS 32 |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 954 | struct lro lro0_n[MAX_LRO_SESSIONS]; |
Ravinandan Arakali | 7d3d0439 | 2006-01-25 14:53:07 -0500 | [diff] [blame] | 955 | unsigned long clubbed_frms_cnt; |
| 956 | unsigned long sending_both; |
| 957 | u8 lro; |
| 958 | u16 lro_max_aggr_per_sess; |
Sivakumar Subramani | 92b8443 | 2007-09-06 06:51:14 -0400 | [diff] [blame] | 959 | volatile unsigned long state; |
Sivakumar Subramani | 9caab45 | 2007-09-06 06:21:54 -0400 | [diff] [blame] | 960 | u64 general_int_mask; |
Sivakumar Subramani | 19a6052 | 2007-01-31 13:30:49 -0500 | [diff] [blame] | 961 | #define VPD_STRING_LEN 80 |
| 962 | u8 product_name[VPD_STRING_LEN]; |
| 963 | u8 serial_num[VPD_STRING_LEN]; |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 964 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 965 | |
| 966 | #define RESET_ERROR 1; |
| 967 | #define CMD_ERROR 2; |
| 968 | |
| 969 | /* OS related system calls */ |
| 970 | #ifndef readq |
| 971 | static inline u64 readq(void __iomem *addr) |
| 972 | { |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 973 | u64 ret = 0; |
| 974 | ret = readl(addr + 4); |
Andrew Morton | 7ef24b6 | 2005-08-25 17:14:46 -0700 | [diff] [blame] | 975 | ret <<= 32; |
| 976 | ret |= readl(addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 977 | |
| 978 | return ret; |
| 979 | } |
| 980 | #endif |
| 981 | |
| 982 | #ifndef writeq |
| 983 | static inline void writeq(u64 val, void __iomem *addr) |
| 984 | { |
| 985 | writel((u32) (val), addr); |
| 986 | writel((u32) (val >> 32), (addr + 4)); |
| 987 | } |
Ananda Raju | c92ca04 | 2006-04-21 19:18:03 -0400 | [diff] [blame] | 988 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 989 | |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 990 | /* |
| 991 | * Some registers have to be written in a particular order to |
| 992 | * expect correct hardware operation. The macro SPECIAL_REG_WRITE |
| 993 | * is used to perform such ordered writes. Defines UF (Upper First) |
Ananda Raju | c92ca04 | 2006-04-21 19:18:03 -0400 | [diff] [blame] | 994 | * and LF (Lower First) will be used to specify the required write order. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 995 | */ |
| 996 | #define UF 1 |
| 997 | #define LF 2 |
| 998 | static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order) |
| 999 | { |
Ananda Raju | c92ca04 | 2006-04-21 19:18:03 -0400 | [diff] [blame] | 1000 | u32 ret; |
| 1001 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1002 | if (order == LF) { |
| 1003 | writel((u32) (val), addr); |
Ananda Raju | c92ca04 | 2006-04-21 19:18:03 -0400 | [diff] [blame] | 1004 | ret = readl(addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1005 | writel((u32) (val >> 32), (addr + 4)); |
Ananda Raju | c92ca04 | 2006-04-21 19:18:03 -0400 | [diff] [blame] | 1006 | ret = readl(addr + 4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1007 | } else { |
| 1008 | writel((u32) (val >> 32), (addr + 4)); |
Ananda Raju | c92ca04 | 2006-04-21 19:18:03 -0400 | [diff] [blame] | 1009 | ret = readl(addr + 4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1010 | writel((u32) (val), addr); |
Ananda Raju | c92ca04 | 2006-04-21 19:18:03 -0400 | [diff] [blame] | 1011 | ret = readl(addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1012 | } |
| 1013 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1014 | |
| 1015 | /* Interrupt related values of Xena */ |
| 1016 | |
| 1017 | #define ENABLE_INTRS 1 |
| 1018 | #define DISABLE_INTRS 2 |
| 1019 | |
| 1020 | /* Highest level interrupt blocks */ |
| 1021 | #define TX_PIC_INTR (0x0001<<0) |
| 1022 | #define TX_DMA_INTR (0x0001<<1) |
| 1023 | #define TX_MAC_INTR (0x0001<<2) |
| 1024 | #define TX_XGXS_INTR (0x0001<<3) |
| 1025 | #define TX_TRAFFIC_INTR (0x0001<<4) |
| 1026 | #define RX_PIC_INTR (0x0001<<5) |
| 1027 | #define RX_DMA_INTR (0x0001<<6) |
| 1028 | #define RX_MAC_INTR (0x0001<<7) |
| 1029 | #define RX_XGXS_INTR (0x0001<<8) |
| 1030 | #define RX_TRAFFIC_INTR (0x0001<<9) |
| 1031 | #define MC_INTR (0x0001<<10) |
| 1032 | #define ENA_ALL_INTRS ( TX_PIC_INTR | \ |
| 1033 | TX_DMA_INTR | \ |
| 1034 | TX_MAC_INTR | \ |
| 1035 | TX_XGXS_INTR | \ |
| 1036 | TX_TRAFFIC_INTR | \ |
| 1037 | RX_PIC_INTR | \ |
| 1038 | RX_DMA_INTR | \ |
| 1039 | RX_MAC_INTR | \ |
| 1040 | RX_XGXS_INTR | \ |
| 1041 | RX_TRAFFIC_INTR | \ |
| 1042 | MC_INTR ) |
| 1043 | |
| 1044 | /* Interrupt masks for the general interrupt mask register */ |
| 1045 | #define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL |
| 1046 | |
Jiri Slaby | b7b5a12 | 2007-10-18 23:40:29 -0700 | [diff] [blame] | 1047 | #define TXPIC_INT_M s2BIT(0) |
| 1048 | #define TXDMA_INT_M s2BIT(1) |
| 1049 | #define TXMAC_INT_M s2BIT(2) |
| 1050 | #define TXXGXS_INT_M s2BIT(3) |
| 1051 | #define TXTRAFFIC_INT_M s2BIT(8) |
| 1052 | #define PIC_RX_INT_M s2BIT(32) |
| 1053 | #define RXDMA_INT_M s2BIT(33) |
| 1054 | #define RXMAC_INT_M s2BIT(34) |
| 1055 | #define MC_INT_M s2BIT(35) |
| 1056 | #define RXXGXS_INT_M s2BIT(36) |
| 1057 | #define RXTRAFFIC_INT_M s2BIT(40) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1058 | |
| 1059 | /* PIC level Interrupts TODO*/ |
| 1060 | |
| 1061 | /* DMA level Inressupts */ |
Jiri Slaby | b7b5a12 | 2007-10-18 23:40:29 -0700 | [diff] [blame] | 1062 | #define TXDMA_PFC_INT_M s2BIT(0) |
| 1063 | #define TXDMA_PCC_INT_M s2BIT(2) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1064 | |
| 1065 | /* PFC block interrupts */ |
Jiri Slaby | b7b5a12 | 2007-10-18 23:40:29 -0700 | [diff] [blame] | 1066 | #define PFC_MISC_ERR_1 s2BIT(0) /* Interrupt to indicate FIFO full */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1067 | |
| 1068 | /* PCC block interrupts. */ |
| 1069 | #define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate |
| 1070 | PCC_FB_ECC Error. */ |
| 1071 | |
raghavendra.koushik@neterion.com | 2034672 | 2005-08-03 12:24:33 -0700 | [diff] [blame] | 1072 | #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1073 | /* |
| 1074 | * Prototype declaration. |
| 1075 | */ |
| 1076 | static int __devinit s2io_init_nic(struct pci_dev *pdev, |
| 1077 | const struct pci_device_id *pre); |
| 1078 | static void __devexit s2io_rem_nic(struct pci_dev *pdev); |
| 1079 | static int init_shared_mem(struct s2io_nic *sp); |
| 1080 | static void free_shared_mem(struct s2io_nic *sp); |
| 1081 | static int init_nic(struct s2io_nic *nic); |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 1082 | static void rx_intr_handler(struct ring_info *ring_data); |
| 1083 | static void tx_intr_handler(struct fifo_info *fifo_data); |
Sivakumar Subramani | 8116f3c | 2007-09-17 13:05:35 -0700 | [diff] [blame] | 1084 | static void s2io_handle_errors(void * dev_id); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1085 | |
| 1086 | static int s2io_starter(void); |
Sivakumar Subramani | 19a6052 | 2007-01-31 13:30:49 -0500 | [diff] [blame] | 1087 | static void s2io_closer(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1088 | static void s2io_tx_watchdog(struct net_device *dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1089 | static void s2io_set_multicast(struct net_device *dev); |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 1090 | static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp); |
| 1091 | static void s2io_link(struct s2io_nic * sp, int link); |
| 1092 | static void s2io_reset(struct s2io_nic * sp); |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 1093 | static int s2io_poll(struct napi_struct *napi, int budget); |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 1094 | static void s2io_init_pci(struct s2io_nic * sp); |
Sivakumar Subramani | 2fd3768 | 2007-09-14 07:39:19 -0400 | [diff] [blame] | 1095 | static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr); |
raghavendra.koushik@neterion.com | 25fff88 | 2005-08-03 12:34:11 -0700 | [diff] [blame] | 1096 | static void s2io_alarm_handle(unsigned long data); |
Ravinandan Arakali | cc6e7c4 | 2005-10-04 06:41:24 -0400 | [diff] [blame] | 1097 | static irqreturn_t |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1098 | s2io_msix_ring_handle(int irq, void *dev_id); |
Ravinandan Arakali | cc6e7c4 | 2005-10-04 06:41:24 -0400 | [diff] [blame] | 1099 | static irqreturn_t |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1100 | s2io_msix_fifo_handle(int irq, void *dev_id); |
| 1101 | static irqreturn_t s2io_isr(int irq, void *dev_id); |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 1102 | static int verify_xena_quiescence(struct s2io_nic *sp); |
Jeff Garzik | 7282d49 | 2006-09-13 14:30:00 -0400 | [diff] [blame] | 1103 | static const struct ethtool_ops netdev_ethtool_ops; |
David Howells | c402895 | 2006-11-22 14:57:56 +0000 | [diff] [blame] | 1104 | static void s2io_set_link(struct work_struct *work); |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 1105 | static int s2io_set_swapper(struct s2io_nic * sp); |
| 1106 | static void s2io_card_down(struct s2io_nic *nic); |
| 1107 | static int s2io_card_up(struct s2io_nic *nic); |
Sivakumar Subramani | 9fc93a4 | 2007-02-24 01:57:32 -0500 | [diff] [blame] | 1108 | static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit, |
| 1109 | int bit_state); |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 1110 | static int s2io_add_isr(struct s2io_nic * sp); |
| 1111 | static void s2io_rem_isr(struct s2io_nic * sp); |
Sivakumar Subramani | 19a6052 | 2007-01-31 13:30:49 -0500 | [diff] [blame] | 1112 | |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 1113 | static void restore_xmsi_data(struct s2io_nic *nic); |
Sreenivasa Honnur | faa4f79 | 2008-01-24 01:45:43 -0800 | [diff] [blame] | 1114 | static void do_s2io_store_unicast_mc(struct s2io_nic *sp); |
| 1115 | static void do_s2io_restore_unicast_mc(struct s2io_nic *sp); |
| 1116 | static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset); |
| 1117 | static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr); |
| 1118 | static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset); |
| 1119 | static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr); |
Ravinandan Arakali | 7d3d0439 | 2006-01-25 14:53:07 -0500 | [diff] [blame] | 1120 | |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 1121 | static int |
| 1122 | s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro, |
| 1123 | struct RxD_t *rxdp, struct s2io_nic *sp); |
| 1124 | static void clear_lro_session(struct lro *lro); |
Sreenivasa Honnur | cdb5bf0 | 2008-02-20 17:09:15 -0500 | [diff] [blame] | 1125 | static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag); |
Ralf Baechle | 1ee6dd7 | 2007-01-31 14:09:29 -0500 | [diff] [blame] | 1126 | static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro); |
| 1127 | static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro, |
| 1128 | struct sk_buff *skb, u32 tcp_len); |
Sivakumar Subramani | 9fc93a4 | 2007-02-24 01:57:32 -0500 | [diff] [blame] | 1129 | static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring); |
Ananda Raju | b41477f | 2006-07-24 19:52:49 -0400 | [diff] [blame] | 1130 | |
Linas Vepstas | d796fdb | 2007-05-14 18:37:30 -0500 | [diff] [blame] | 1131 | static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev, |
| 1132 | pci_channel_state_t state); |
| 1133 | static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev); |
| 1134 | static void s2io_io_resume(struct pci_dev *pdev); |
| 1135 | |
Ananda Raju | 75c30b1 | 2006-07-24 19:55:09 -0400 | [diff] [blame] | 1136 | #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size |
| 1137 | #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size |
| 1138 | #define s2io_offload_type(skb) skb_shinfo(skb)->gso_type |
| 1139 | |
Ananda Raju | b41477f | 2006-07-24 19:52:49 -0400 | [diff] [blame] | 1140 | #define S2IO_PARM_INT(X, def_val) \ |
| 1141 | static unsigned int X = def_val;\ |
| 1142 | module_param(X , uint, 0); |
| 1143 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1144 | #endif /* _S2IO_H */ |