Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Local APIC handling, local APIC timers |
| 3 | * |
Ingo Molnar | 8f47e16 | 2009-01-31 02:03:42 +0100 | [diff] [blame] | 4 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * |
| 6 | * Fixes |
| 7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; |
| 8 | * thanks to Eric Gilmore |
| 9 | * and Rolf G. Tews |
| 10 | * for testing these extensively. |
| 11 | * Maciej W. Rozycki : Various updates and fixes. |
| 12 | * Mikael Pettersson : Power Management for UP-APIC. |
| 13 | * Pavel Machek and |
| 14 | * Mikael Pettersson : PM converted to driver model. |
| 15 | */ |
| 16 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 17 | #include <linux/perf_event.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <linux/kernel_stat.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 19 | #include <linux/mc146818rtc.h> |
Thomas Gleixner | 70a2002 | 2008-01-30 13:30:18 +0100 | [diff] [blame] | 20 | #include <linux/acpi_pmtmr.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 21 | #include <linux/clockchips.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/bootmem.h> |
Frederic Weisbecker | bcbc4f2 | 2008-12-09 23:54:20 +0100 | [diff] [blame] | 24 | #include <linux/ftrace.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 25 | #include <linux/ioport.h> |
| 26 | #include <linux/module.h> |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 27 | #include <linux/syscore_ops.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 28 | #include <linux/delay.h> |
Jaswinder Singh Rajput | e423e33 | 2009-01-04 16:16:25 +0530 | [diff] [blame] | 29 | #include <linux/timex.h> |
Ralf Baechle | 334955e | 2011-06-01 19:04:57 +0100 | [diff] [blame] | 30 | #include <linux/i8253.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 31 | #include <linux/dmar.h> |
| 32 | #include <linux/init.h> |
| 33 | #include <linux/cpu.h> |
| 34 | #include <linux/dmi.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 35 | #include <linux/smp.h> |
| 36 | #include <linux/mm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | |
Steven Rostedt (Red Hat) | 83ab851 | 2013-06-21 10:29:05 -0400 | [diff] [blame] | 38 | #include <asm/trace/irq_vectors.h> |
Suresh Siddha | 8a8f422 | 2012-03-30 11:47:08 -0700 | [diff] [blame] | 39 | #include <asm/irq_remapping.h> |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 40 | #include <asm/perf_event.h> |
Thomas Gleixner | 736deca | 2009-08-19 12:35:53 +0200 | [diff] [blame] | 41 | #include <asm/x86_init.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | #include <asm/pgalloc.h> |
Arun Sharma | 60063497 | 2011-07-26 16:09:06 -0700 | [diff] [blame] | 43 | #include <linux/atomic.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 44 | #include <asm/mpspec.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 45 | #include <asm/i8259.h> |
Andi Kleen | 73dea47 | 2006-02-03 21:50:50 +0100 | [diff] [blame] | 46 | #include <asm/proto.h> |
Andi Kleen | 2c8c0e6 | 2006-09-26 10:52:32 +0200 | [diff] [blame] | 47 | #include <asm/apic.h> |
Henrik Kretzschmar | 7167d08 | 2011-02-22 15:38:05 +0100 | [diff] [blame] | 48 | #include <asm/io_apic.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 49 | #include <asm/desc.h> |
| 50 | #include <asm/hpet.h> |
| 51 | #include <asm/idle.h> |
| 52 | #include <asm/mtrr.h> |
Ralf Baechle | 16f871b | 2011-06-01 19:05:06 +0100 | [diff] [blame] | 53 | #include <asm/time.h> |
Jaswinder Singh Rajput | 2bc1379 | 2009-01-11 20:34:47 +0530 | [diff] [blame] | 54 | #include <asm/smp.h> |
Andi Kleen | be71b85 | 2009-02-12 13:49:38 +0100 | [diff] [blame] | 55 | #include <asm/mce.h> |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 56 | #include <asm/tsc.h> |
Sheng Yang | 2904ed8 | 2010-12-21 14:18:48 +0800 | [diff] [blame] | 57 | #include <asm/hypervisor.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 59 | unsigned int num_processors; |
Ingo Molnar | fdbecd9 | 2009-01-31 03:57:12 +0100 | [diff] [blame] | 60 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 61 | unsigned disabled_cpus; |
Ingo Molnar | fdbecd9 | 2009-01-31 03:57:12 +0100 | [diff] [blame] | 62 | |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 63 | /* Processor that is doing the boot up */ |
| 64 | unsigned int boot_cpu_physical_apicid = -1U; |
David Rientjes | cc08e04 | 2013-11-14 15:05:32 -0800 | [diff] [blame] | 65 | EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); |
Glauber Costa | 5af5573 | 2008-03-25 13:28:56 -0300 | [diff] [blame] | 66 | |
Cyrill Gorcunov | 80e5609 | 2008-08-24 02:01:42 -0700 | [diff] [blame] | 67 | /* |
Ingo Molnar | fdbecd9 | 2009-01-31 03:57:12 +0100 | [diff] [blame] | 68 | * The highest APIC ID seen during enumeration. |
Cyrill Gorcunov | 80e5609 | 2008-08-24 02:01:42 -0700 | [diff] [blame] | 69 | */ |
Jiang Liu | a491cc902 | 2014-06-09 16:19:32 +0800 | [diff] [blame] | 70 | static unsigned int max_physical_apicid; |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 71 | |
Ingo Molnar | fdbecd9 | 2009-01-31 03:57:12 +0100 | [diff] [blame] | 72 | /* |
| 73 | * Bitmask of physically existing CPUs: |
| 74 | */ |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 75 | physid_mask_t phys_cpu_present_map; |
| 76 | |
| 77 | /* |
HATAYAMA Daisuke | 151e0c7 | 2014-01-15 15:44:58 +0900 | [diff] [blame] | 78 | * Processor to be disabled specified by kernel parameter |
| 79 | * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to |
| 80 | * avoid undefined behaviour caused by sending INIT from AP to BSP. |
| 81 | */ |
H. Peter Anvin | 5b4d1db | 2014-01-15 13:02:08 -0800 | [diff] [blame] | 82 | static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; |
HATAYAMA Daisuke | 151e0c7 | 2014-01-15 15:44:58 +0900 | [diff] [blame] | 83 | |
| 84 | /* |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 85 | * Map cpu index to physical APIC ID |
| 86 | */ |
Vlad Zolotarov | 0816b0f | 2012-06-11 12:56:52 +0300 | [diff] [blame] | 87 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); |
| 88 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 89 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); |
| 90 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); |
Cyrill Gorcunov | 80e5609 | 2008-08-24 02:01:42 -0700 | [diff] [blame] | 91 | |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 92 | #ifdef CONFIG_X86_32 |
Tejun Heo | 4c321ff | 2011-01-23 14:37:30 +0100 | [diff] [blame] | 93 | |
Tejun Heo | 4c321ff | 2011-01-23 14:37:30 +0100 | [diff] [blame] | 94 | /* |
| 95 | * On x86_32, the mapping between cpu and logical apicid may vary |
| 96 | * depending on apic in use. The following early percpu variable is |
| 97 | * used for the mapping. This is where the behaviors of x86_64 and 32 |
| 98 | * actually diverge. Let's keep it ugly for now. |
| 99 | */ |
Vlad Zolotarov | 0816b0f | 2012-06-11 12:56:52 +0300 | [diff] [blame] | 100 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); |
Tejun Heo | 4c321ff | 2011-01-23 14:37:30 +0100 | [diff] [blame] | 101 | |
Yinghai Lu | f28c0ae | 2008-08-24 02:01:49 -0700 | [diff] [blame] | 102 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
| 103 | static int enabled_via_apicbase; |
| 104 | |
Cyrill Gorcunov | c0eaa45 | 2009-04-12 20:47:40 +0400 | [diff] [blame] | 105 | /* |
| 106 | * Handle interrupt mode configuration register (IMCR). |
| 107 | * This register controls whether the interrupt signals |
| 108 | * that reach the BSP come from the master PIC or from the |
| 109 | * local APIC. Before entering Symmetric I/O Mode, either |
| 110 | * the BIOS or the operating system must switch out of |
| 111 | * PIC Mode by changing the IMCR. |
| 112 | */ |
Alexander van Heukelum | 5cda395 | 2009-04-13 17:39:24 +0200 | [diff] [blame] | 113 | static inline void imcr_pic_to_apic(void) |
Cyrill Gorcunov | c0eaa45 | 2009-04-12 20:47:40 +0400 | [diff] [blame] | 114 | { |
| 115 | /* select IMCR register */ |
| 116 | outb(0x70, 0x22); |
| 117 | /* NMI and 8259 INTR go through APIC */ |
| 118 | outb(0x01, 0x23); |
| 119 | } |
| 120 | |
Alexander van Heukelum | 5cda395 | 2009-04-13 17:39:24 +0200 | [diff] [blame] | 121 | static inline void imcr_apic_to_pic(void) |
Cyrill Gorcunov | c0eaa45 | 2009-04-12 20:47:40 +0400 | [diff] [blame] | 122 | { |
| 123 | /* select IMCR register */ |
| 124 | outb(0x70, 0x22); |
| 125 | /* NMI and 8259 INTR go directly to BSP */ |
| 126 | outb(0x00, 0x23); |
| 127 | } |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 128 | #endif |
| 129 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 130 | /* |
| 131 | * Knob to control our willingness to enable the local APIC. |
| 132 | * |
| 133 | * +1=force-enable |
| 134 | */ |
| 135 | static int force_enable_local_apic __initdata; |
David Rientjes | dc9788f | 2014-02-04 23:55:06 -0800 | [diff] [blame] | 136 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 137 | /* |
| 138 | * APIC command line parameters |
| 139 | */ |
| 140 | static int __init parse_lapic(char *arg) |
| 141 | { |
| 142 | if (config_enabled(CONFIG_X86_32) && !arg) |
| 143 | force_enable_local_apic = 1; |
Mathias Krause | 27cf929 | 2013-02-19 20:47:07 +0100 | [diff] [blame] | 144 | else if (arg && !strncmp(arg, "notscdeadline", 13)) |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 145 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
| 146 | return 0; |
| 147 | } |
| 148 | early_param("lapic", parse_lapic); |
| 149 | |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 150 | #ifdef CONFIG_X86_64 |
Chris Wright | bc1d99c | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 151 | static int apic_calibrate_pmtmr __initdata; |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 152 | static __init int setup_apicpmtimer(char *s) |
| 153 | { |
| 154 | apic_calibrate_pmtmr = 1; |
| 155 | notsc_setup(NULL); |
| 156 | return 0; |
| 157 | } |
| 158 | __setup("apicpmtimer", setup_apicpmtimer); |
| 159 | #endif |
| 160 | |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 161 | unsigned long mp_lapic_addr; |
| 162 | int disable_apic; |
| 163 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 164 | static int disable_apic_timer __initdata; |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 165 | /* Local APIC timer works in C2 */ |
Linus Torvalds | 2e7c283 | 2007-03-23 11:32:31 -0700 | [diff] [blame] | 166 | int local_apic_timer_c2_ok; |
| 167 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); |
| 168 | |
Jan Beulich | 2414e02 | 2014-11-03 08:39:43 +0000 | [diff] [blame] | 169 | int first_system_vector = FIRST_SYSTEM_VECTOR; |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 170 | |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 171 | /* |
| 172 | * Debug level, exported for io_apic.c |
| 173 | */ |
Maciej W. Rozycki | baa1318 | 2008-07-14 18:44:51 +0100 | [diff] [blame] | 174 | unsigned int apic_verbosity; |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 175 | |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 176 | int pic_mode; |
| 177 | |
Alexey Starikovskiy | bab4b27 | 2008-05-19 19:47:03 +0400 | [diff] [blame] | 178 | /* Have we found an MP table */ |
| 179 | int smp_found_config; |
| 180 | |
Aaron Durbin | 3992872 | 2006-12-07 02:14:01 +0100 | [diff] [blame] | 181 | static struct resource lapic_resource = { |
| 182 | .name = "Local APIC", |
| 183 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, |
| 184 | }; |
| 185 | |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 186 | unsigned int lapic_timer_frequency = 0; |
Thomas Gleixner | d03030e | 2007-10-12 23:04:06 +0200 | [diff] [blame] | 187 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 188 | static void apic_pm_activate(void); |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 189 | |
Andi Kleen | d343289 | 2008-01-30 13:33:17 +0100 | [diff] [blame] | 190 | static unsigned long apic_phys; |
| 191 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 192 | /* |
| 193 | * Get the LAPIC version |
| 194 | */ |
| 195 | static inline int lapic_get_version(void) |
| 196 | { |
| 197 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
| 198 | } |
| 199 | |
| 200 | /* |
Cyrill Gorcunov | 9c80386 | 2008-08-16 23:21:54 +0400 | [diff] [blame] | 201 | * Check, if the APIC is integrated or a separate chip |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 202 | */ |
| 203 | static inline int lapic_is_integrated(void) |
| 204 | { |
Cyrill Gorcunov | 9c80386 | 2008-08-16 23:21:54 +0400 | [diff] [blame] | 205 | #ifdef CONFIG_X86_64 |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 206 | return 1; |
Cyrill Gorcunov | 9c80386 | 2008-08-16 23:21:54 +0400 | [diff] [blame] | 207 | #else |
| 208 | return APIC_INTEGRATED(lapic_get_version()); |
| 209 | #endif |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 210 | } |
| 211 | |
| 212 | /* |
| 213 | * Check, whether this is a modern or a first generation APIC |
| 214 | */ |
| 215 | static int modern_apic(void) |
| 216 | { |
| 217 | /* AMD systems use old APIC versions, so check the CPU */ |
| 218 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && |
| 219 | boot_cpu_data.x86 >= 0xf) |
| 220 | return 1; |
| 221 | return lapic_get_version() >= 0x14; |
| 222 | } |
| 223 | |
Cyrill Gorcunov | 08306ce | 2009-04-12 20:47:41 +0400 | [diff] [blame] | 224 | /* |
Cyrill Gorcunov | a933c61 | 2009-10-14 00:07:04 +0400 | [diff] [blame] | 225 | * right after this call apic become NOOP driven |
| 226 | * so apic->write/read doesn't do anything |
Cyrill Gorcunov | 08306ce | 2009-04-12 20:47:41 +0400 | [diff] [blame] | 227 | */ |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 228 | static void __init apic_disable(void) |
Cyrill Gorcunov | 08306ce | 2009-04-12 20:47:41 +0400 | [diff] [blame] | 229 | { |
Cyrill Gorcunov | f88f2b4 | 2009-10-15 19:04:16 +0400 | [diff] [blame] | 230 | pr_info("APIC: switched to apic NOOP\n"); |
Cyrill Gorcunov | a933c61 | 2009-10-14 00:07:04 +0400 | [diff] [blame] | 231 | apic = &apic_noop; |
Cyrill Gorcunov | 08306ce | 2009-04-12 20:47:41 +0400 | [diff] [blame] | 232 | } |
| 233 | |
Yinghai Lu | c1eeb2d | 2009-02-16 23:02:14 -0800 | [diff] [blame] | 234 | void native_apic_wait_icr_idle(void) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 235 | { |
| 236 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) |
| 237 | cpu_relax(); |
| 238 | } |
| 239 | |
Yinghai Lu | c1eeb2d | 2009-02-16 23:02:14 -0800 | [diff] [blame] | 240 | u32 native_safe_apic_wait_icr_idle(void) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 241 | { |
| 242 | u32 send_status; |
| 243 | int timeout; |
| 244 | |
| 245 | timeout = 0; |
| 246 | do { |
| 247 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; |
| 248 | if (!send_status) |
| 249 | break; |
Fernando Luis Vazquez Cao | b49d7d8 | 2011-12-15 11:32:24 +0900 | [diff] [blame] | 250 | inc_irq_stat(icr_read_retry_count); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 251 | udelay(100); |
| 252 | } while (timeout++ < 1000); |
| 253 | |
| 254 | return send_status; |
| 255 | } |
| 256 | |
Yinghai Lu | c1eeb2d | 2009-02-16 23:02:14 -0800 | [diff] [blame] | 257 | void native_apic_icr_write(u32 low, u32 id) |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 258 | { |
Jan Kiszka | ea7bdc6 | 2014-01-27 20:14:06 +0100 | [diff] [blame] | 259 | unsigned long flags; |
| 260 | |
| 261 | local_irq_save(flags); |
Cyrill Gorcunov | ed4e5ec | 2008-08-15 13:51:20 +0200 | [diff] [blame] | 262 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 263 | apic_write(APIC_ICR, low); |
Jan Kiszka | ea7bdc6 | 2014-01-27 20:14:06 +0100 | [diff] [blame] | 264 | local_irq_restore(flags); |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 265 | } |
| 266 | |
Yinghai Lu | c1eeb2d | 2009-02-16 23:02:14 -0800 | [diff] [blame] | 267 | u64 native_apic_icr_read(void) |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 268 | { |
| 269 | u32 icr1, icr2; |
| 270 | |
| 271 | icr2 = apic_read(APIC_ICR2); |
| 272 | icr1 = apic_read(APIC_ICR); |
| 273 | |
Cyrill Gorcunov | cf9768d7 | 2008-08-16 23:21:55 +0400 | [diff] [blame] | 274 | return icr1 | ((u64)icr2 << 32); |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 275 | } |
| 276 | |
Cyrill Gorcunov | 7c37e48 | 2008-08-24 02:01:40 -0700 | [diff] [blame] | 277 | #ifdef CONFIG_X86_32 |
| 278 | /** |
| 279 | * get_physical_broadcast - Get number of physical broadcast IDs |
| 280 | */ |
| 281 | int get_physical_broadcast(void) |
| 282 | { |
| 283 | return modern_apic() ? 0xff : 0xf; |
| 284 | } |
| 285 | #endif |
| 286 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 287 | /** |
| 288 | * lapic_get_maxlvt - get the maximum number of local vector table entries |
| 289 | */ |
| 290 | int lapic_get_maxlvt(void) |
| 291 | { |
Cyrill Gorcunov | 36a028d | 2008-07-24 13:52:28 +0200 | [diff] [blame] | 292 | unsigned int v; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 293 | |
| 294 | v = apic_read(APIC_LVR); |
Cyrill Gorcunov | 36a028d | 2008-07-24 13:52:28 +0200 | [diff] [blame] | 295 | /* |
| 296 | * - we always have APIC integrated on 64bit mode |
| 297 | * - 82489DXs do not report # of LVT entries |
| 298 | */ |
| 299 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 300 | } |
| 301 | |
| 302 | /* |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 303 | * Local APIC timer |
| 304 | */ |
| 305 | |
Cyrill Gorcunov | c40aaec | 2008-08-18 20:45:55 +0400 | [diff] [blame] | 306 | /* Clock divisor */ |
Cyrill Gorcunov | c40aaec | 2008-08-18 20:45:55 +0400 | [diff] [blame] | 307 | #define APIC_DIVISOR 16 |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 308 | #define TSC_DIVISOR 32 |
Cyrill Gorcunov | f07f4f9 | 2008-08-15 13:51:21 +0200 | [diff] [blame] | 309 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 310 | /* |
| 311 | * This function sets up the local APIC timer, with a timeout of |
| 312 | * 'clocks' APIC bus clock. During calibration we actually call |
| 313 | * this function twice on the boot CPU, once with a bogus timeout |
| 314 | * value, second time for real. The other (noncalibrating) CPUs |
| 315 | * call this function only once, with the real, calibrated value. |
| 316 | * |
| 317 | * We do reads before writes even if unnecessary, to get around the |
| 318 | * P5 APIC double write bug. |
| 319 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 320 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
| 321 | { |
| 322 | unsigned int lvtt_value, tmp_value; |
| 323 | |
| 324 | lvtt_value = LOCAL_TIMER_VECTOR; |
| 325 | if (!oneshot) |
| 326 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 327 | else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
| 328 | lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; |
| 329 | |
Cyrill Gorcunov | f07f4f9 | 2008-08-15 13:51:21 +0200 | [diff] [blame] | 330 | if (!lapic_is_integrated()) |
| 331 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); |
| 332 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 333 | if (!irqen) |
| 334 | lvtt_value |= APIC_LVT_MASKED; |
| 335 | |
| 336 | apic_write(APIC_LVTT, lvtt_value); |
| 337 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 338 | if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { |
| 339 | printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); |
| 340 | return; |
| 341 | } |
| 342 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 343 | /* |
| 344 | * Divide PICLK by 16 |
| 345 | */ |
| 346 | tmp_value = apic_read(APIC_TDCR); |
Cyrill Gorcunov | c40aaec | 2008-08-18 20:45:55 +0400 | [diff] [blame] | 347 | apic_write(APIC_TDCR, |
| 348 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
| 349 | APIC_TDR_DIV_16); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 350 | |
| 351 | if (!oneshot) |
Cyrill Gorcunov | f07f4f9 | 2008-08-15 13:51:21 +0200 | [diff] [blame] | 352 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 353 | } |
| 354 | |
| 355 | /* |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 356 | * Setup extended LVT, AMD specific |
Robert Richter | 7b83dae | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 357 | * |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 358 | * Software should use the LVT offsets the BIOS provides. The offsets |
| 359 | * are determined by the subsystems using it like those for MCE |
| 360 | * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts |
| 361 | * are supported. Beginning with family 10h at least 4 offsets are |
| 362 | * available. |
Robert Richter | 286f571 | 2008-07-22 21:08:46 +0200 | [diff] [blame] | 363 | * |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 364 | * Since the offsets must be consistent for all cores, we keep track |
| 365 | * of the LVT offsets in software and reserve the offset for the same |
| 366 | * vector also to be used on other cores. An offset is freed by |
| 367 | * setting the entry to APIC_EILVT_MASKED. |
| 368 | * |
| 369 | * If the BIOS is right, there should be no conflicts. Otherwise a |
| 370 | * "[Firmware Bug]: ..." error message is generated. However, if |
| 371 | * software does not properly determines the offsets, it is not |
| 372 | * necessarily a BIOS bug. |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 373 | */ |
Robert Richter | 7b83dae | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 374 | |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 375 | static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 376 | |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 377 | static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) |
| 378 | { |
| 379 | return (old & APIC_EILVT_MASKED) |
| 380 | || (new == APIC_EILVT_MASKED) |
| 381 | || ((new & ~APIC_EILVT_MASKED) == old); |
| 382 | } |
| 383 | |
| 384 | static unsigned int reserve_eilvt_offset(int offset, unsigned int new) |
| 385 | { |
Robert Richter | 8abc312 | 2012-03-27 20:04:02 +0200 | [diff] [blame] | 386 | unsigned int rsvd, vector; |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 387 | |
| 388 | if (offset >= APIC_EILVT_NR_MAX) |
| 389 | return ~0; |
| 390 | |
Robert Richter | 8abc312 | 2012-03-27 20:04:02 +0200 | [diff] [blame] | 391 | rsvd = atomic_read(&eilvt_offsets[offset]); |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 392 | do { |
Robert Richter | 8abc312 | 2012-03-27 20:04:02 +0200 | [diff] [blame] | 393 | vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ |
| 394 | if (vector && !eilvt_entry_is_changeable(vector, new)) |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 395 | /* may not change if vectors are different */ |
| 396 | return rsvd; |
| 397 | rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); |
| 398 | } while (rsvd != new); |
| 399 | |
Robert Richter | 8abc312 | 2012-03-27 20:04:02 +0200 | [diff] [blame] | 400 | rsvd &= ~APIC_EILVT_MASKED; |
| 401 | if (rsvd && rsvd != vector) |
| 402 | pr_info("LVT offset %d assigned for vector 0x%02x\n", |
| 403 | offset, rsvd); |
| 404 | |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 405 | return new; |
| 406 | } |
| 407 | |
| 408 | /* |
| 409 | * If mask=1, the LVT entry does not generate interrupts while mask=0 |
Robert Richter | cbf74ce | 2011-05-30 16:31:11 +0200 | [diff] [blame] | 410 | * enables the vector. See also the BKDGs. Must be called with |
| 411 | * preemption disabled. |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 412 | */ |
| 413 | |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 414 | int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 415 | { |
| 416 | unsigned long reg = APIC_EILVTn(offset); |
| 417 | unsigned int new, old, reserved; |
| 418 | |
| 419 | new = (mask << 16) | (msg_type << 8) | vector; |
| 420 | old = apic_read(reg); |
| 421 | reserved = reserve_eilvt_offset(offset, new); |
| 422 | |
| 423 | if (reserved != new) { |
Robert Richter | eb48c9c | 2010-10-25 16:03:39 +0200 | [diff] [blame] | 424 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
| 425 | "vector 0x%x, but the register is already in use for " |
| 426 | "vector 0x%x on another cpu\n", |
| 427 | smp_processor_id(), reg, offset, new, reserved); |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 428 | return -EINVAL; |
| 429 | } |
| 430 | |
| 431 | if (!eilvt_entry_is_changeable(old, new)) { |
Robert Richter | eb48c9c | 2010-10-25 16:03:39 +0200 | [diff] [blame] | 432 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
| 433 | "vector 0x%x, but the register is already in use for " |
| 434 | "vector 0x%x on this cpu\n", |
| 435 | smp_processor_id(), reg, offset, new, old); |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 436 | return -EBUSY; |
| 437 | } |
| 438 | |
| 439 | apic_write(reg, new); |
| 440 | |
| 441 | return 0; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 442 | } |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 443 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt); |
Robert Richter | 7b83dae | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 444 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 445 | /* |
| 446 | * Program the next event, relative to now |
| 447 | */ |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 448 | static int lapic_next_event(unsigned long delta, |
| 449 | struct clock_event_device *evt) |
| 450 | { |
| 451 | apic_write(APIC_TMICT, delta); |
| 452 | return 0; |
| 453 | } |
| 454 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 455 | static int lapic_next_deadline(unsigned long delta, |
| 456 | struct clock_event_device *evt) |
| 457 | { |
| 458 | u64 tsc; |
| 459 | |
| 460 | rdtscll(tsc); |
| 461 | wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); |
| 462 | return 0; |
| 463 | } |
| 464 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 465 | /* |
| 466 | * Setup the lapic timer in periodic or oneshot mode |
| 467 | */ |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 468 | static void lapic_timer_setup(enum clock_event_mode mode, |
| 469 | struct clock_event_device *evt) |
| 470 | { |
| 471 | unsigned long flags; |
| 472 | unsigned int v; |
| 473 | |
| 474 | /* Lapic used as dummy for broadcast ? */ |
| 475 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) |
| 476 | return; |
| 477 | |
| 478 | local_irq_save(flags); |
| 479 | |
| 480 | switch (mode) { |
| 481 | case CLOCK_EVT_MODE_PERIODIC: |
| 482 | case CLOCK_EVT_MODE_ONESHOT: |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 483 | __setup_APIC_LVTT(lapic_timer_frequency, |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 484 | mode != CLOCK_EVT_MODE_PERIODIC, 1); |
| 485 | break; |
| 486 | case CLOCK_EVT_MODE_UNUSED: |
| 487 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 488 | v = apic_read(APIC_LVTT); |
| 489 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); |
| 490 | apic_write(APIC_LVTT, v); |
Andreas Herrmann | 6f9b410 | 2009-10-27 11:01:38 +0100 | [diff] [blame] | 491 | apic_write(APIC_TMICT, 0); |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 492 | break; |
| 493 | case CLOCK_EVT_MODE_RESUME: |
| 494 | /* Nothing to do here */ |
| 495 | break; |
| 496 | } |
| 497 | |
| 498 | local_irq_restore(flags); |
| 499 | } |
| 500 | |
| 501 | /* |
| 502 | * Local APIC timer broadcast function |
| 503 | */ |
Mike Travis | 9628937 | 2008-12-31 18:08:46 -0800 | [diff] [blame] | 504 | static void lapic_timer_broadcast(const struct cpumask *mask) |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 505 | { |
| 506 | #ifdef CONFIG_SMP |
Ingo Molnar | dac5f41 | 2009-01-28 15:42:24 +0100 | [diff] [blame] | 507 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 508 | #endif |
| 509 | } |
| 510 | |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 511 | |
| 512 | /* |
| 513 | * The local apic timer can be used for any function which is CPU local. |
| 514 | */ |
| 515 | static struct clock_event_device lapic_clockevent = { |
| 516 | .name = "lapic", |
| 517 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
| 518 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, |
| 519 | .shift = 32, |
| 520 | .set_mode = lapic_timer_setup, |
| 521 | .set_next_event = lapic_next_event, |
| 522 | .broadcast = lapic_timer_broadcast, |
| 523 | .rating = 100, |
| 524 | .irq = -1, |
| 525 | }; |
| 526 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); |
| 527 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 528 | /* |
Uwe Kleine-König | 421f91d | 2010-06-11 12:17:00 +0200 | [diff] [blame] | 529 | * Setup the local APIC timer for this CPU. Copy the initialized values |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 530 | * of the boot CPU and register the clock event in the framework. |
| 531 | */ |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 532 | static void setup_APIC_timer(void) |
Fernando Luis VazquezCao | 8339e9f | 2007-05-02 19:27:17 +0200 | [diff] [blame] | 533 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 534 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 535 | |
Christoph Lameter | 349c004 | 2011-03-12 12:50:10 +0100 | [diff] [blame] | 536 | if (this_cpu_has(X86_FEATURE_ARAT)) { |
Venkatesh Pallipadi | db954b5 | 2009-04-06 18:51:29 -0700 | [diff] [blame] | 537 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; |
| 538 | /* Make LAPIC timer preferrable over percpu HPET */ |
| 539 | lapic_clockevent.rating = 150; |
| 540 | } |
| 541 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 542 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
Rusty Russell | 320ab2b | 2008-12-13 21:20:26 +1030 | [diff] [blame] | 543 | levt->cpumask = cpumask_of(smp_processor_id()); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 544 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 545 | if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
| 546 | levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | |
| 547 | CLOCK_EVT_FEAT_DUMMY); |
| 548 | levt->set_next_event = lapic_next_deadline; |
| 549 | clockevents_config_and_register(levt, |
| 550 | (tsc_khz / TSC_DIVISOR) * 1000, |
| 551 | 0xF, ~0UL); |
| 552 | } else |
| 553 | clockevents_register_device(levt); |
Fernando Luis VazquezCao | 8339e9f | 2007-05-02 19:27:17 +0200 | [diff] [blame] | 554 | } |
| 555 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 556 | /* |
| 557 | * In this functions we calibrate APIC bus clocks to the external timer. |
| 558 | * |
| 559 | * We want to do the calibration only once since we want to have local timer |
| 560 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus |
| 561 | * frequency. |
| 562 | * |
| 563 | * This was previously done by reading the PIT/HPET and waiting for a wrap |
| 564 | * around to find out, that a tick has elapsed. I have a box, where the PIT |
| 565 | * readout is broken, so it never gets out of the wait loop again. This was |
| 566 | * also reported by others. |
| 567 | * |
| 568 | * Monitoring the jiffies value is inaccurate and the clockevents |
| 569 | * infrastructure allows us to do a simple substitution of the interrupt |
| 570 | * handler. |
| 571 | * |
| 572 | * The calibration routine also uses the pm_timer when possible, as the PIT |
| 573 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes |
| 574 | * back to normal later in the boot process). |
| 575 | */ |
| 576 | |
| 577 | #define LAPIC_CAL_LOOPS (HZ/10) |
| 578 | |
| 579 | static __initdata int lapic_cal_loops = -1; |
| 580 | static __initdata long lapic_cal_t1, lapic_cal_t2; |
| 581 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; |
| 582 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; |
| 583 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; |
| 584 | |
| 585 | /* |
| 586 | * Temporary interrupt handler. |
| 587 | */ |
| 588 | static void __init lapic_cal_handler(struct clock_event_device *dev) |
| 589 | { |
| 590 | unsigned long long tsc = 0; |
| 591 | long tapic = apic_read(APIC_TMCCT); |
| 592 | unsigned long pm = acpi_pm_read_early(); |
| 593 | |
| 594 | if (cpu_has_tsc) |
| 595 | rdtscll(tsc); |
| 596 | |
| 597 | switch (lapic_cal_loops++) { |
| 598 | case 0: |
| 599 | lapic_cal_t1 = tapic; |
| 600 | lapic_cal_tsc1 = tsc; |
| 601 | lapic_cal_pm1 = pm; |
| 602 | lapic_cal_j1 = jiffies; |
| 603 | break; |
| 604 | |
| 605 | case LAPIC_CAL_LOOPS: |
| 606 | lapic_cal_t2 = tapic; |
| 607 | lapic_cal_tsc2 = tsc; |
| 608 | if (pm < lapic_cal_pm1) |
| 609 | pm += ACPI_PM_OVRRUN; |
| 610 | lapic_cal_pm2 = pm; |
| 611 | lapic_cal_j2 = jiffies; |
| 612 | break; |
| 613 | } |
| 614 | } |
| 615 | |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 616 | static int __init |
| 617 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 618 | { |
| 619 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; |
| 620 | const long pm_thresh = pm_100ms / 100; |
| 621 | unsigned long mult; |
| 622 | u64 res; |
| 623 | |
| 624 | #ifndef CONFIG_X86_PM_TIMER |
| 625 | return -1; |
| 626 | #endif |
| 627 | |
Yasuaki Ishimatsu | 39ba5d4 | 2009-01-28 12:52:24 +0900 | [diff] [blame] | 628 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 629 | |
| 630 | /* Check, if the PM timer is available */ |
| 631 | if (!deltapm) |
| 632 | return -1; |
| 633 | |
| 634 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); |
| 635 | |
| 636 | if (deltapm > (pm_100ms - pm_thresh) && |
| 637 | deltapm < (pm_100ms + pm_thresh)) { |
Yasuaki Ishimatsu | 39ba5d4 | 2009-01-28 12:52:24 +0900 | [diff] [blame] | 638 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 639 | return 0; |
| 640 | } |
| 641 | |
| 642 | res = (((u64)deltapm) * mult) >> 22; |
| 643 | do_div(res, 1000000); |
| 644 | pr_warning("APIC calibration not consistent " |
Yasuaki Ishimatsu | 39ba5d4 | 2009-01-28 12:52:24 +0900 | [diff] [blame] | 645 | "with PM-Timer: %ldms instead of 100ms\n",(long)res); |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 646 | |
| 647 | /* Correct the lapic counter value */ |
| 648 | res = (((u64)(*delta)) * pm_100ms); |
| 649 | do_div(res, deltapm); |
| 650 | pr_info("APIC delta adjusted to PM-Timer: " |
| 651 | "%lu (%ld)\n", (unsigned long)res, *delta); |
| 652 | *delta = (long)res; |
| 653 | |
| 654 | /* Correct the tsc counter value */ |
| 655 | if (cpu_has_tsc) { |
| 656 | res = (((u64)(*deltatsc)) * pm_100ms); |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 657 | do_div(res, deltapm); |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 658 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
Frans Pop | 3235dc3 | 2010-02-06 18:47:17 +0100 | [diff] [blame] | 659 | "PM-Timer: %lu (%ld)\n", |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 660 | (unsigned long)res, *deltatsc); |
| 661 | *deltatsc = (long)res; |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 662 | } |
| 663 | |
| 664 | return 0; |
| 665 | } |
| 666 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 667 | static int __init calibrate_APIC_clock(void) |
| 668 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 669 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 670 | void (*real_handler)(struct clock_event_device *dev); |
| 671 | unsigned long deltaj; |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 672 | long delta, deltatsc; |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 673 | int pm_referenced = 0; |
| 674 | |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 675 | /** |
| 676 | * check if lapic timer has already been calibrated by platform |
| 677 | * specific routine, such as tsc calibration code. if so, we just fill |
| 678 | * in the clockevent structure and return. |
| 679 | */ |
| 680 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 681 | if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
| 682 | return 0; |
| 683 | } else if (lapic_timer_frequency) { |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 684 | apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", |
| 685 | lapic_timer_frequency); |
| 686 | lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, |
| 687 | TICK_NSEC, lapic_clockevent.shift); |
| 688 | lapic_clockevent.max_delta_ns = |
| 689 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); |
| 690 | lapic_clockevent.min_delta_ns = |
| 691 | clockevent_delta2ns(0xF, &lapic_clockevent); |
| 692 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
| 693 | return 0; |
| 694 | } |
| 695 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 696 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
| 697 | "calibrating APIC timer ...\n"); |
| 698 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 699 | local_irq_disable(); |
| 700 | |
| 701 | /* Replace the global interrupt handler */ |
| 702 | real_handler = global_clock_event->event_handler; |
| 703 | global_clock_event->event_handler = lapic_cal_handler; |
| 704 | |
| 705 | /* |
Cyrill Gorcunov | 81608f3 | 2008-10-10 19:00:17 +0400 | [diff] [blame] | 706 | * Setup the APIC counter to maximum. There is no way the lapic |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 707 | * can underflow in the 100ms detection time frame |
| 708 | */ |
Cyrill Gorcunov | 81608f3 | 2008-10-10 19:00:17 +0400 | [diff] [blame] | 709 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 710 | |
| 711 | /* Let the interrupts run */ |
| 712 | local_irq_enable(); |
| 713 | |
| 714 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
| 715 | cpu_relax(); |
| 716 | |
| 717 | local_irq_disable(); |
| 718 | |
| 719 | /* Restore the real event handler */ |
| 720 | global_clock_event->event_handler = real_handler; |
| 721 | |
| 722 | /* Build delta t1-t2 as apic timer counts down */ |
| 723 | delta = lapic_cal_t1 - lapic_cal_t2; |
| 724 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); |
| 725 | |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 726 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
| 727 | |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 728 | /* we trust the PM based calibration if possible */ |
| 729 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 730 | &delta, &deltatsc); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 731 | |
| 732 | /* Calculate the scaled math multiplication factor */ |
| 733 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, |
| 734 | lapic_clockevent.shift); |
| 735 | lapic_clockevent.max_delta_ns = |
Pierre Tardy | 4aed89d | 2011-01-06 16:23:29 +0100 | [diff] [blame] | 736 | clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 737 | lapic_clockevent.min_delta_ns = |
| 738 | clockevent_delta2ns(0xF, &lapic_clockevent); |
| 739 | |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 740 | lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 741 | |
| 742 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); |
Thomas Gleixner | 411462f | 2009-11-16 11:52:39 +0100 | [diff] [blame] | 743 | apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 744 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 745 | lapic_timer_frequency); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 746 | |
| 747 | if (cpu_has_tsc) { |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 748 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
| 749 | "%ld.%04ld MHz.\n", |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 750 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
| 751 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 752 | } |
| 753 | |
| 754 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " |
| 755 | "%u.%04u MHz.\n", |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 756 | lapic_timer_frequency / (1000000 / HZ), |
| 757 | lapic_timer_frequency % (1000000 / HZ)); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 758 | |
| 759 | /* |
| 760 | * Do a sanity check on the APIC calibration result |
| 761 | */ |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 762 | if (lapic_timer_frequency < (1000000 / HZ)) { |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 763 | local_irq_enable(); |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 764 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 765 | return -1; |
| 766 | } |
| 767 | |
| 768 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; |
| 769 | |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 770 | /* |
| 771 | * PM timer calibration failed or not turned on |
| 772 | * so lets try APIC timer based calibration |
| 773 | */ |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 774 | if (!pm_referenced) { |
| 775 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); |
| 776 | |
| 777 | /* |
| 778 | * Setup the apic timer manually |
| 779 | */ |
| 780 | levt->event_handler = lapic_cal_handler; |
| 781 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); |
| 782 | lapic_cal_loops = -1; |
| 783 | |
| 784 | /* Let the interrupts run */ |
| 785 | local_irq_enable(); |
| 786 | |
| 787 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
| 788 | cpu_relax(); |
| 789 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 790 | /* Stop the lapic timer */ |
| 791 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); |
| 792 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 793 | /* Jiffies delta */ |
| 794 | deltaj = lapic_cal_j2 - lapic_cal_j1; |
| 795 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); |
| 796 | |
| 797 | /* Check, if the jiffies result is consistent */ |
| 798 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) |
| 799 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); |
| 800 | else |
| 801 | levt->features |= CLOCK_EVT_FEAT_DUMMY; |
| 802 | } else |
| 803 | local_irq_enable(); |
| 804 | |
| 805 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { |
Jaswinder Singh Rajput | e423e33 | 2009-01-04 16:16:25 +0530 | [diff] [blame] | 806 | pr_warning("APIC timer disabled due to verification failure\n"); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 807 | return -1; |
| 808 | } |
| 809 | |
| 810 | return 0; |
| 811 | } |
| 812 | |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 813 | /* |
| 814 | * Setup the boot APIC |
| 815 | * |
| 816 | * Calibrate and verify the result. |
| 817 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 818 | void __init setup_boot_APIC_clock(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 819 | { |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 820 | /* |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 821 | * The local apic timer can be disabled via the kernel |
| 822 | * commandline or from the CPU detection code. Register the lapic |
| 823 | * timer as a dummy clock event source on SMP systems, so the |
| 824 | * broadcast mechanism is used. On UP systems simply ignore it. |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 825 | */ |
| 826 | if (disable_apic_timer) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 827 | pr_info("Disabling APIC timer\n"); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 828 | /* No broadcast on UP ! */ |
Thomas Gleixner | 9d09951 | 2008-01-30 13:33:04 +0100 | [diff] [blame] | 829 | if (num_possible_cpus() > 1) { |
| 830 | lapic_clockevent.mult = 1; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 831 | setup_APIC_timer(); |
Thomas Gleixner | 9d09951 | 2008-01-30 13:33:04 +0100 | [diff] [blame] | 832 | } |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 833 | return; |
| 834 | } |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 835 | |
Cyrill Gorcunov | 89b3b1f4 | 2008-07-15 21:02:54 +0400 | [diff] [blame] | 836 | if (calibrate_APIC_clock()) { |
Thomas Gleixner | c2b84b3 | 2008-01-30 13:33:04 +0100 | [diff] [blame] | 837 | /* No broadcast on UP ! */ |
| 838 | if (num_possible_cpus() > 1) |
| 839 | setup_APIC_timer(); |
| 840 | return; |
| 841 | } |
| 842 | |
| 843 | /* |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 844 | * If nmi_watchdog is set to IO_APIC, we need the |
| 845 | * PIT/HPET going. Otherwise register lapic as a dummy |
| 846 | * device. |
| 847 | */ |
Don Zickus | 072b198 | 2010-11-12 11:22:24 -0500 | [diff] [blame] | 848 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 849 | |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 850 | /* Setup the lapic or request the broadcast */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 851 | setup_APIC_timer(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 852 | } |
| 853 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 854 | void setup_secondary_APIC_clock(void) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 855 | { |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 856 | setup_APIC_timer(); |
| 857 | } |
| 858 | |
| 859 | /* |
| 860 | * The guts of the apic timer interrupt |
| 861 | */ |
| 862 | static void local_apic_timer_interrupt(void) |
| 863 | { |
| 864 | int cpu = smp_processor_id(); |
| 865 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); |
| 866 | |
| 867 | /* |
| 868 | * Normally we should not be here till LAPIC has been initialized but |
| 869 | * in some cases like kdump, its possible that there is a pending LAPIC |
| 870 | * timer interrupt from previous kernel's context and is delivered in |
| 871 | * new kernel the moment interrupts are enabled. |
| 872 | * |
| 873 | * Interrupts are enabled early and LAPIC is setup much later, hence |
| 874 | * its possible that when we get here evt->event_handler is NULL. |
| 875 | * Check for event_handler being NULL and discard the interrupt as |
| 876 | * spurious. |
| 877 | */ |
| 878 | if (!evt->event_handler) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 879 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 880 | /* Switch it off */ |
| 881 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); |
| 882 | return; |
| 883 | } |
| 884 | |
| 885 | /* |
| 886 | * the NMI deadlock-detector uses this. |
| 887 | */ |
Hiroshi Shimamoto | 915b0d0 | 2008-12-08 19:19:26 -0800 | [diff] [blame] | 888 | inc_irq_stat(apic_timer_irqs); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 889 | |
| 890 | evt->event_handler(evt); |
| 891 | } |
| 892 | |
| 893 | /* |
| 894 | * Local APIC timer interrupt. This is the most natural way for doing |
| 895 | * local interrupts, but local timer interrupts can be emulated by |
| 896 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] |
| 897 | * |
| 898 | * [ if a single-CPU system runs an SMP kernel then we call the local |
| 899 | * interrupt as well. Thus we cannot inline the local irq ... ] |
| 900 | */ |
Andi Kleen | 1d9090e | 2013-08-05 15:02:37 -0700 | [diff] [blame] | 901 | __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 902 | { |
| 903 | struct pt_regs *old_regs = set_irq_regs(regs); |
| 904 | |
| 905 | /* |
| 906 | * NOTE! We'd better ACK the irq immediately, |
| 907 | * because timer handling can be slow. |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 908 | * |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 909 | * update_process_times() expects us to have done irq_enter(). |
| 910 | * Besides, if we don't timer interrupts ignore the global |
| 911 | * interrupt lock, which is the WrongThing (tm) to do. |
| 912 | */ |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 913 | entering_ack_irq(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 914 | local_apic_timer_interrupt(); |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 915 | exiting_irq(); |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 916 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 917 | set_irq_regs(old_regs); |
| 918 | } |
| 919 | |
Andi Kleen | 1d9090e | 2013-08-05 15:02:37 -0700 | [diff] [blame] | 920 | __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs) |
Seiji Aguchi | cf910e8 | 2013-06-20 11:46:53 -0400 | [diff] [blame] | 921 | { |
| 922 | struct pt_regs *old_regs = set_irq_regs(regs); |
| 923 | |
| 924 | /* |
| 925 | * NOTE! We'd better ACK the irq immediately, |
| 926 | * because timer handling can be slow. |
| 927 | * |
| 928 | * update_process_times() expects us to have done irq_enter(). |
| 929 | * Besides, if we don't timer interrupts ignore the global |
| 930 | * interrupt lock, which is the WrongThing (tm) to do. |
| 931 | */ |
| 932 | entering_ack_irq(); |
| 933 | trace_local_timer_entry(LOCAL_TIMER_VECTOR); |
| 934 | local_apic_timer_interrupt(); |
| 935 | trace_local_timer_exit(LOCAL_TIMER_VECTOR); |
| 936 | exiting_irq(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 937 | |
| 938 | set_irq_regs(old_regs); |
| 939 | } |
| 940 | |
| 941 | int setup_profiling_timer(unsigned int multiplier) |
| 942 | { |
| 943 | return -EINVAL; |
| 944 | } |
| 945 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 946 | /* |
| 947 | * Local APIC start and shutdown |
| 948 | */ |
| 949 | |
| 950 | /** |
| 951 | * clear_local_APIC - shutdown the local APIC |
| 952 | * |
| 953 | * This is called, when a CPU is disabled and before rebooting, so the state of |
| 954 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS |
| 955 | * leftovers during boot. |
| 956 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 957 | void clear_local_APIC(void) |
| 958 | { |
Chuck Ebbert | 2584a82 | 2008-05-20 18:18:12 -0400 | [diff] [blame] | 959 | int maxlvt; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 960 | u32 v; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 961 | |
Andi Kleen | d343289 | 2008-01-30 13:33:17 +0100 | [diff] [blame] | 962 | /* APIC hasn't been mapped yet */ |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 963 | if (!x2apic_mode && !apic_phys) |
Andi Kleen | d343289 | 2008-01-30 13:33:17 +0100 | [diff] [blame] | 964 | return; |
| 965 | |
| 966 | maxlvt = lapic_get_maxlvt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 967 | /* |
Siddha, Suresh B | 704fc59 | 2006-06-26 13:59:53 +0200 | [diff] [blame] | 968 | * Masking an LVT entry can trigger a local APIC error |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 969 | * if the vector is zero. Mask LVTERR first to prevent this. |
| 970 | */ |
| 971 | if (maxlvt >= 3) { |
| 972 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 973 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 974 | } |
| 975 | /* |
| 976 | * Careful: we have to set masks only first to deassert |
| 977 | * any level-triggered sources. |
| 978 | */ |
| 979 | v = apic_read(APIC_LVTT); |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 980 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 981 | v = apic_read(APIC_LVT0); |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 982 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 983 | v = apic_read(APIC_LVT1); |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 984 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 985 | if (maxlvt >= 4) { |
| 986 | v = apic_read(APIC_LVTPC); |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 987 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 988 | } |
| 989 | |
Cyrill Gorcunov | 6764014 | 2008-08-16 23:21:50 +0400 | [diff] [blame] | 990 | /* lets not touch this if we didn't frob it */ |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 991 | #ifdef CONFIG_X86_THERMAL_VECTOR |
Cyrill Gorcunov | 6764014 | 2008-08-16 23:21:50 +0400 | [diff] [blame] | 992 | if (maxlvt >= 5) { |
| 993 | v = apic_read(APIC_LVTTHMR); |
| 994 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); |
| 995 | } |
| 996 | #endif |
Andi Kleen | 5ca8681 | 2009-02-12 13:49:37 +0100 | [diff] [blame] | 997 | #ifdef CONFIG_X86_MCE_INTEL |
| 998 | if (maxlvt >= 6) { |
| 999 | v = apic_read(APIC_LVTCMCI); |
| 1000 | if (!(v & APIC_LVT_MASKED)) |
| 1001 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); |
| 1002 | } |
| 1003 | #endif |
| 1004 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1005 | /* |
| 1006 | * Clean APIC state for other OSs: |
| 1007 | */ |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1008 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
| 1009 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
| 1010 | apic_write(APIC_LVT1, APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1011 | if (maxlvt >= 3) |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1012 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1013 | if (maxlvt >= 4) |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1014 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
Cyrill Gorcunov | 6764014 | 2008-08-16 23:21:50 +0400 | [diff] [blame] | 1015 | |
| 1016 | /* Integrated APIC (!82489DX) ? */ |
| 1017 | if (lapic_is_integrated()) { |
| 1018 | if (maxlvt > 3) |
| 1019 | /* Clear ESR due to Pentium errata 3AP and 11AP */ |
| 1020 | apic_write(APIC_ESR, 0); |
| 1021 | apic_read(APIC_ESR); |
| 1022 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1023 | } |
| 1024 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1025 | /** |
| 1026 | * disable_local_APIC - clear and disable the local APIC |
| 1027 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1028 | void disable_local_APIC(void) |
| 1029 | { |
| 1030 | unsigned int value; |
| 1031 | |
Jan Beulich | 4a13ad0 | 2009-01-14 12:28:51 +0000 | [diff] [blame] | 1032 | /* APIC hasn't been mapped yet */ |
Yinghai Lu | fd19dce | 2010-07-15 00:00:59 -0700 | [diff] [blame] | 1033 | if (!x2apic_mode && !apic_phys) |
Jan Beulich | 4a13ad0 | 2009-01-14 12:28:51 +0000 | [diff] [blame] | 1034 | return; |
| 1035 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1036 | clear_local_APIC(); |
| 1037 | |
| 1038 | /* |
| 1039 | * Disable APIC (implies clearing of registers |
| 1040 | * for 82489DX!). |
| 1041 | */ |
| 1042 | value = apic_read(APIC_SPIV); |
| 1043 | value &= ~APIC_SPIV_APIC_ENABLED; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1044 | apic_write(APIC_SPIV, value); |
Cyrill Gorcunov | 990b183 | 2008-08-18 20:45:51 +0400 | [diff] [blame] | 1045 | |
| 1046 | #ifdef CONFIG_X86_32 |
| 1047 | /* |
| 1048 | * When LAPIC was disabled by the BIOS and enabled by the kernel, |
| 1049 | * restore the disabled state. |
| 1050 | */ |
| 1051 | if (enabled_via_apicbase) { |
| 1052 | unsigned int l, h; |
| 1053 | |
| 1054 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 1055 | l &= ~MSR_IA32_APICBASE_ENABLE; |
| 1056 | wrmsr(MSR_IA32_APICBASE, l, h); |
| 1057 | } |
| 1058 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1059 | } |
| 1060 | |
Cyrill Gorcunov | fe4024d | 2008-08-18 20:45:52 +0400 | [diff] [blame] | 1061 | /* |
| 1062 | * If Linux enabled the LAPIC against the BIOS default disable it down before |
| 1063 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and |
| 1064 | * not power-off. Additionally clear all LVT entries before disable_local_APIC |
| 1065 | * for the case where Linux didn't enable the LAPIC. |
| 1066 | */ |
Hiroshi Shimamoto | 9b7711f | 2007-10-19 18:21:11 -0700 | [diff] [blame] | 1067 | void lapic_shutdown(void) |
| 1068 | { |
| 1069 | unsigned long flags; |
| 1070 | |
Cyrill Gorcunov | 8312136 | 2009-09-15 11:12:30 +0400 | [diff] [blame] | 1071 | if (!cpu_has_apic && !apic_from_smp_config()) |
Hiroshi Shimamoto | 9b7711f | 2007-10-19 18:21:11 -0700 | [diff] [blame] | 1072 | return; |
| 1073 | |
| 1074 | local_irq_save(flags); |
| 1075 | |
Cyrill Gorcunov | fe4024d | 2008-08-18 20:45:52 +0400 | [diff] [blame] | 1076 | #ifdef CONFIG_X86_32 |
| 1077 | if (!enabled_via_apicbase) |
| 1078 | clear_local_APIC(); |
| 1079 | else |
| 1080 | #endif |
| 1081 | disable_local_APIC(); |
| 1082 | |
Hiroshi Shimamoto | 9b7711f | 2007-10-19 18:21:11 -0700 | [diff] [blame] | 1083 | |
| 1084 | local_irq_restore(flags); |
| 1085 | } |
| 1086 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1087 | /** |
| 1088 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs |
| 1089 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1090 | void __init sync_Arb_IDs(void) |
| 1091 | { |
Cyrill Gorcunov | 296cb95 | 2008-08-15 13:51:23 +0200 | [diff] [blame] | 1092 | /* |
| 1093 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not |
| 1094 | * needed on AMD. |
| 1095 | */ |
| 1096 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1097 | return; |
| 1098 | |
| 1099 | /* |
| 1100 | * Wait for idle. |
| 1101 | */ |
| 1102 | apic_wait_icr_idle(); |
| 1103 | |
| 1104 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
Cyrill Gorcunov | 6f6da97 | 2008-08-15 23:05:19 +0400 | [diff] [blame] | 1105 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
| 1106 | APIC_INT_LEVELTRIG | APIC_DM_INIT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1107 | } |
| 1108 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1109 | /* |
| 1110 | * An initial setup of the virtual wire mode. |
| 1111 | */ |
| 1112 | void __init init_bsp_APIC(void) |
| 1113 | { |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1114 | unsigned int value; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1115 | |
| 1116 | /* |
| 1117 | * Don't do the setup now if we have a SMP BIOS as the |
| 1118 | * through-I/O-APIC virtual wire mode might be active. |
| 1119 | */ |
| 1120 | if (smp_found_config || !cpu_has_apic) |
| 1121 | return; |
| 1122 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1123 | /* |
| 1124 | * Do not trust the local APIC being empty at bootup. |
| 1125 | */ |
| 1126 | clear_local_APIC(); |
| 1127 | |
| 1128 | /* |
| 1129 | * Enable APIC. |
| 1130 | */ |
| 1131 | value = apic_read(APIC_SPIV); |
| 1132 | value &= ~APIC_VECTOR_MASK; |
| 1133 | value |= APIC_SPIV_APIC_ENABLED; |
Cyrill Gorcunov | 638c041 | 2008-08-15 23:05:18 +0400 | [diff] [blame] | 1134 | |
| 1135 | #ifdef CONFIG_X86_32 |
| 1136 | /* This bit is reserved on P4/Xeon and should be cleared */ |
| 1137 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && |
| 1138 | (boot_cpu_data.x86 == 15)) |
| 1139 | value &= ~APIC_SPIV_FOCUS_DISABLED; |
| 1140 | else |
| 1141 | #endif |
| 1142 | value |= APIC_SPIV_FOCUS_DISABLED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1143 | value |= SPURIOUS_APIC_VECTOR; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1144 | apic_write(APIC_SPIV, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1145 | |
| 1146 | /* |
| 1147 | * Set up the virtual wire mode. |
| 1148 | */ |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1149 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1150 | value = APIC_DM_NMI; |
Cyrill Gorcunov | 638c041 | 2008-08-15 23:05:18 +0400 | [diff] [blame] | 1151 | if (!lapic_is_integrated()) /* 82489DX */ |
| 1152 | value |= APIC_LVT_LEVEL_TRIGGER; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1153 | apic_write(APIC_LVT1, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1154 | } |
| 1155 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 1156 | static void lapic_setup_esr(void) |
Cyrill Gorcunov | c43da2f | 2008-08-18 20:45:54 +0400 | [diff] [blame] | 1157 | { |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1158 | unsigned int oldvalue, value, maxlvt; |
Cyrill Gorcunov | c43da2f | 2008-08-18 20:45:54 +0400 | [diff] [blame] | 1159 | |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1160 | if (!lapic_is_integrated()) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1161 | pr_info("No ESR for 82489DX.\n"); |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1162 | return; |
Cyrill Gorcunov | c43da2f | 2008-08-18 20:45:54 +0400 | [diff] [blame] | 1163 | } |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1164 | |
Ingo Molnar | 08125d3 | 2009-01-28 05:08:44 +0100 | [diff] [blame] | 1165 | if (apic->disable_esr) { |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1166 | /* |
| 1167 | * Something untraceable is creating bad interrupts on |
| 1168 | * secondary quads ... for the moment, just leave the |
| 1169 | * ESR disabled - we can't do anything useful with the |
| 1170 | * errors anyway - mbligh |
| 1171 | */ |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1172 | pr_info("Leaving ESR disabled.\n"); |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1173 | return; |
| 1174 | } |
| 1175 | |
| 1176 | maxlvt = lapic_get_maxlvt(); |
| 1177 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
| 1178 | apic_write(APIC_ESR, 0); |
| 1179 | oldvalue = apic_read(APIC_ESR); |
| 1180 | |
| 1181 | /* enables sending errors */ |
| 1182 | value = ERROR_APIC_VECTOR; |
| 1183 | apic_write(APIC_LVTERR, value); |
| 1184 | |
| 1185 | /* |
| 1186 | * spec says clear errors after enabling vector. |
| 1187 | */ |
| 1188 | if (maxlvt > 3) |
| 1189 | apic_write(APIC_ESR, 0); |
| 1190 | value = apic_read(APIC_ESR); |
| 1191 | if (value != oldvalue) |
| 1192 | apic_printk(APIC_VERBOSE, "ESR value before enabling " |
| 1193 | "vector: 0x%08x after: 0x%08x\n", |
| 1194 | oldvalue, value); |
Cyrill Gorcunov | c43da2f | 2008-08-18 20:45:54 +0400 | [diff] [blame] | 1195 | } |
| 1196 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1197 | /** |
| 1198 | * setup_local_APIC - setup the local APIC |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1199 | * |
| 1200 | * Used to setup local APIC while initializing BSP or bringin up APs. |
| 1201 | * Always called with preemption disabled. |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1202 | */ |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 1203 | void setup_local_APIC(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1204 | { |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1205 | int cpu = smp_processor_id(); |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 1206 | unsigned int value, queued; |
| 1207 | int i, j, acked = 0; |
| 1208 | unsigned long long tsc = 0, ntsc; |
Andy Lutomirski | b47dcbd | 2014-10-15 10:12:07 -0700 | [diff] [blame] | 1209 | long long max_loops = cpu_khz ? cpu_khz : 1000000; |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 1210 | |
| 1211 | if (cpu_has_tsc) |
| 1212 | rdtscll(tsc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1213 | |
Jan Beulich | f118263 | 2009-01-14 12:27:35 +0000 | [diff] [blame] | 1214 | if (disable_apic) { |
Henrik Kretzschmar | 7167d08 | 2011-02-22 15:38:05 +0100 | [diff] [blame] | 1215 | disable_ioapic_support(); |
Jan Beulich | f118263 | 2009-01-14 12:27:35 +0000 | [diff] [blame] | 1216 | return; |
| 1217 | } |
| 1218 | |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1219 | #ifdef CONFIG_X86_32 |
| 1220 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
Ingo Molnar | 08125d3 | 2009-01-28 05:08:44 +0100 | [diff] [blame] | 1221 | if (lapic_is_integrated() && apic->disable_esr) { |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1222 | apic_write(APIC_ESR, 0); |
| 1223 | apic_write(APIC_ESR, 0); |
| 1224 | apic_write(APIC_ESR, 0); |
| 1225 | apic_write(APIC_ESR, 0); |
| 1226 | } |
| 1227 | #endif |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1228 | perf_events_lapic_init(); |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1229 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1230 | /* |
| 1231 | * Double-check whether this APIC is really registered. |
| 1232 | * This is meaningless in clustered apic mode, so we skip it. |
| 1233 | */ |
Daniel Walker | c2777f9 | 2009-09-12 10:40:20 -0700 | [diff] [blame] | 1234 | BUG_ON(!apic->apic_id_registered()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1235 | |
| 1236 | /* |
| 1237 | * Intel recommends to set DFR, LDR and TPR before enabling |
| 1238 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel |
| 1239 | * document number 292116). So here it goes... |
| 1240 | */ |
Ingo Molnar | a5c4329 | 2009-01-28 06:50:47 +0100 | [diff] [blame] | 1241 | apic->init_apic_ldr(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1242 | |
Tejun Heo | 6f802c4 | 2011-01-23 14:37:31 +0100 | [diff] [blame] | 1243 | #ifdef CONFIG_X86_32 |
| 1244 | /* |
Tejun Heo | acb8bc0 | 2011-01-23 14:37:33 +0100 | [diff] [blame] | 1245 | * APIC LDR is initialized. If logical_apicid mapping was |
| 1246 | * initialized during get_smp_config(), make sure it matches the |
| 1247 | * actual value. |
Tejun Heo | 6f802c4 | 2011-01-23 14:37:31 +0100 | [diff] [blame] | 1248 | */ |
Tejun Heo | acb8bc0 | 2011-01-23 14:37:33 +0100 | [diff] [blame] | 1249 | i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); |
| 1250 | WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); |
| 1251 | /* always use the value from LDR */ |
Tejun Heo | 6f802c4 | 2011-01-23 14:37:31 +0100 | [diff] [blame] | 1252 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = |
| 1253 | logical_smp_processor_id(); |
| 1254 | #endif |
| 1255 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1256 | /* |
| 1257 | * Set Task Priority to 'accept all'. We never change this |
| 1258 | * later on. |
| 1259 | */ |
| 1260 | value = apic_read(APIC_TASKPRI); |
| 1261 | value &= ~APIC_TPRI_MASK; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1262 | apic_write(APIC_TASKPRI, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1263 | |
| 1264 | /* |
Vivek Goyal | da7ed9f | 2006-03-25 16:31:16 +0100 | [diff] [blame] | 1265 | * After a crash, we no longer service the interrupts and a pending |
| 1266 | * interrupt from previous kernel might still have ISR bit set. |
| 1267 | * |
| 1268 | * Most probably by now CPU has serviced that pending interrupt and |
| 1269 | * it might not have done the ack_APIC_irq() because it thought, |
| 1270 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it |
| 1271 | * does not clear the ISR bit and cpu thinks it has already serivced |
| 1272 | * the interrupt. Hence a vector might get locked. It was noticed |
| 1273 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. |
| 1274 | */ |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 1275 | do { |
| 1276 | queued = 0; |
| 1277 | for (i = APIC_ISR_NR - 1; i >= 0; i--) |
| 1278 | queued |= apic_read(APIC_IRR + i*0x10); |
| 1279 | |
| 1280 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { |
| 1281 | value = apic_read(APIC_ISR + i*0x10); |
| 1282 | for (j = 31; j >= 0; j--) { |
| 1283 | if (value & (1<<j)) { |
| 1284 | ack_APIC_irq(); |
| 1285 | acked++; |
| 1286 | } |
| 1287 | } |
Vivek Goyal | da7ed9f | 2006-03-25 16:31:16 +0100 | [diff] [blame] | 1288 | } |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 1289 | if (acked > 256) { |
| 1290 | printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", |
| 1291 | acked); |
| 1292 | break; |
| 1293 | } |
Shai Fultheim | 42fa425 | 2012-04-20 01:12:32 +0300 | [diff] [blame] | 1294 | if (queued) { |
Andy Lutomirski | b47dcbd | 2014-10-15 10:12:07 -0700 | [diff] [blame] | 1295 | if (cpu_has_tsc && cpu_khz) { |
Shai Fultheim | 42fa425 | 2012-04-20 01:12:32 +0300 | [diff] [blame] | 1296 | rdtscll(ntsc); |
| 1297 | max_loops = (cpu_khz << 10) - (ntsc - tsc); |
| 1298 | } else |
| 1299 | max_loops--; |
| 1300 | } |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 1301 | } while (queued && max_loops > 0); |
| 1302 | WARN_ON(max_loops <= 0); |
Vivek Goyal | da7ed9f | 2006-03-25 16:31:16 +0100 | [diff] [blame] | 1303 | |
| 1304 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1305 | * Now that we are all set up, enable the APIC |
| 1306 | */ |
| 1307 | value = apic_read(APIC_SPIV); |
| 1308 | value &= ~APIC_VECTOR_MASK; |
| 1309 | /* |
| 1310 | * Enable APIC |
| 1311 | */ |
| 1312 | value |= APIC_SPIV_APIC_ENABLED; |
| 1313 | |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1314 | #ifdef CONFIG_X86_32 |
| 1315 | /* |
| 1316 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with |
| 1317 | * certain networking cards. If high frequency interrupts are |
| 1318 | * happening on a particular IOAPIC pin, plus the IOAPIC routing |
| 1319 | * entry is masked/unmasked at a high rate as well then sooner or |
| 1320 | * later IOAPIC line gets 'stuck', no more interrupts are received |
| 1321 | * from the device. If focus CPU is disabled then the hang goes |
| 1322 | * away, oh well :-( |
| 1323 | * |
| 1324 | * [ This bug can be reproduced easily with a level-triggered |
| 1325 | * PCI Ne2000 networking cards and PII/PIII processors, dual |
| 1326 | * BX chipset. ] |
| 1327 | */ |
| 1328 | /* |
| 1329 | * Actually disabling the focus CPU check just makes the hang less |
| 1330 | * frequent as it makes the interrupt distributon model be more |
| 1331 | * like LRU than MRU (the short-term load is more even across CPUs). |
| 1332 | * See also the comment in end_level_ioapic_irq(). --macro |
| 1333 | */ |
| 1334 | |
| 1335 | /* |
| 1336 | * - enable focus processor (bit==0) |
| 1337 | * - 64bit mode always use processor focus |
| 1338 | * so no need to set it |
| 1339 | */ |
| 1340 | value &= ~APIC_SPIV_FOCUS_DISABLED; |
| 1341 | #endif |
Andi Kleen | 3f14c74 | 2006-09-26 10:52:29 +0200 | [diff] [blame] | 1342 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1343 | /* |
| 1344 | * Set spurious IRQ vector |
| 1345 | */ |
| 1346 | value |= SPURIOUS_APIC_VECTOR; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1347 | apic_write(APIC_SPIV, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1348 | |
| 1349 | /* |
| 1350 | * Set up LVT0, LVT1: |
| 1351 | * |
| 1352 | * set up through-local-APIC on the BP's LINT0. This is not |
| 1353 | * strictly necessary in pure symmetric-IO mode, but sometimes |
| 1354 | * we delegate interrupts to the 8259A. |
| 1355 | */ |
| 1356 | /* |
| 1357 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro |
| 1358 | */ |
| 1359 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1360 | if (!cpu && (pic_mode || !value)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1361 | value = APIC_DM_EXTINT; |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1362 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1363 | } else { |
| 1364 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1365 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1366 | } |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1367 | apic_write(APIC_LVT0, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1368 | |
| 1369 | /* |
| 1370 | * only the BP should see the LINT1 NMI signal, obviously. |
| 1371 | */ |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1372 | if (!cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1373 | value = APIC_DM_NMI; |
| 1374 | else |
| 1375 | value = APIC_DM_NMI | APIC_LVT_MASKED; |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1376 | if (!lapic_is_integrated()) /* 82489DX */ |
| 1377 | value |= APIC_LVT_LEVEL_TRIGGER; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1378 | apic_write(APIC_LVT1, value); |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1379 | |
Andi Kleen | be71b85 | 2009-02-12 13:49:38 +0100 | [diff] [blame] | 1380 | #ifdef CONFIG_X86_MCE_INTEL |
| 1381 | /* Recheck CMCI information after local APIC is up on CPU #0 */ |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1382 | if (!cpu) |
Andi Kleen | be71b85 | 2009-02-12 13:49:38 +0100 | [diff] [blame] | 1383 | cmci_recheck(); |
| 1384 | #endif |
Andi Kleen | 739f33b | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 1385 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1386 | |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 1387 | static void end_local_APIC_setup(void) |
Andi Kleen | 739f33b | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 1388 | { |
| 1389 | lapic_setup_esr(); |
Cyrill Gorcunov | fa6b95f | 2008-08-18 20:45:58 +0400 | [diff] [blame] | 1390 | |
| 1391 | #ifdef CONFIG_X86_32 |
Cyrill Gorcunov | 1b4ee4e | 2008-08-18 23:12:33 +0400 | [diff] [blame] | 1392 | { |
| 1393 | unsigned int value; |
| 1394 | /* Disable the local apic timer */ |
| 1395 | value = apic_read(APIC_LVTT); |
| 1396 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); |
| 1397 | apic_write(APIC_LVTT, value); |
| 1398 | } |
Cyrill Gorcunov | fa6b95f | 2008-08-18 20:45:58 +0400 | [diff] [blame] | 1399 | #endif |
| 1400 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1401 | apic_pm_activate(); |
Jan Beulich | 2fb270f | 2011-02-09 08:21:02 +0000 | [diff] [blame] | 1402 | } |
| 1403 | |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 1404 | /* |
| 1405 | * APIC setup function for application processors. Called from smpboot.c |
| 1406 | */ |
| 1407 | void apic_ap_setup(void) |
Jan Beulich | 2fb270f | 2011-02-09 08:21:02 +0000 | [diff] [blame] | 1408 | { |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 1409 | setup_local_APIC(); |
Jan Beulich | 2fb270f | 2011-02-09 08:21:02 +0000 | [diff] [blame] | 1410 | end_local_APIC_setup(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1411 | } |
| 1412 | |
Yinghai Lu | 06cd9a7 | 2009-02-16 17:29:58 -0800 | [diff] [blame] | 1413 | #ifdef CONFIG_X86_X2APIC |
Thomas Gleixner | bfb0507 | 2015-01-15 21:22:12 +0000 | [diff] [blame] | 1414 | int x2apic_mode; |
Thomas Gleixner | 12e189d | 2015-01-15 21:22:22 +0000 | [diff] [blame] | 1415 | |
| 1416 | enum { |
| 1417 | X2APIC_OFF, |
| 1418 | X2APIC_ON, |
| 1419 | X2APIC_DISABLED, |
| 1420 | }; |
| 1421 | static int x2apic_state; |
| 1422 | |
Thomas Gleixner | 44e25ff | 2015-01-15 21:22:24 +0000 | [diff] [blame] | 1423 | static inline void __x2apic_disable(void) |
| 1424 | { |
| 1425 | u64 msr; |
| 1426 | |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1427 | if (cpu_has_apic) |
| 1428 | return; |
| 1429 | |
Thomas Gleixner | 44e25ff | 2015-01-15 21:22:24 +0000 | [diff] [blame] | 1430 | rdmsrl(MSR_IA32_APICBASE, msr); |
| 1431 | if (!(msr & X2APIC_ENABLE)) |
| 1432 | return; |
| 1433 | /* Disable xapic and x2apic first and then reenable xapic mode */ |
| 1434 | wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); |
| 1435 | wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); |
| 1436 | printk_once(KERN_INFO "x2apic disabled\n"); |
| 1437 | } |
| 1438 | |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1439 | static inline void __x2apic_enable(void) |
| 1440 | { |
| 1441 | u64 msr; |
| 1442 | |
| 1443 | rdmsrl(MSR_IA32_APICBASE, msr); |
| 1444 | if (msr & X2APIC_ENABLE) |
| 1445 | return; |
| 1446 | wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); |
| 1447 | printk_once(KERN_INFO "x2apic enabled\n"); |
| 1448 | } |
| 1449 | |
Thomas Gleixner | bfb0507 | 2015-01-15 21:22:12 +0000 | [diff] [blame] | 1450 | static int __init setup_nox2apic(char *str) |
| 1451 | { |
| 1452 | if (x2apic_enabled()) { |
| 1453 | int apicid = native_apic_msr_read(APIC_ID); |
| 1454 | |
| 1455 | if (apicid >= 255) { |
| 1456 | pr_warning("Apicid: %08x, cannot enforce nox2apic\n", |
| 1457 | apicid); |
| 1458 | return 0; |
| 1459 | } |
Thomas Gleixner | 44e25ff | 2015-01-15 21:22:24 +0000 | [diff] [blame] | 1460 | pr_warning("x2apic already enabled.\n"); |
| 1461 | __x2apic_disable(); |
| 1462 | } |
| 1463 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); |
Thomas Gleixner | 12e189d | 2015-01-15 21:22:22 +0000 | [diff] [blame] | 1464 | x2apic_state = X2APIC_DISABLED; |
Thomas Gleixner | 44e25ff | 2015-01-15 21:22:24 +0000 | [diff] [blame] | 1465 | x2apic_mode = 0; |
Thomas Gleixner | bfb0507 | 2015-01-15 21:22:12 +0000 | [diff] [blame] | 1466 | return 0; |
| 1467 | } |
| 1468 | early_param("nox2apic", setup_nox2apic); |
| 1469 | |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1470 | /* Called from cpu_init() to enable x2apic on (secondary) cpus */ |
| 1471 | void x2apic_setup(void) |
| 1472 | { |
| 1473 | /* |
| 1474 | * If x2apic is not in ON state, disable it if already enabled |
| 1475 | * from BIOS. |
| 1476 | */ |
| 1477 | if (x2apic_state != X2APIC_ON) { |
| 1478 | __x2apic_disable(); |
| 1479 | return; |
| 1480 | } |
| 1481 | __x2apic_enable(); |
| 1482 | } |
| 1483 | |
Thomas Gleixner | 44e25ff | 2015-01-15 21:22:24 +0000 | [diff] [blame] | 1484 | static __init void x2apic_disable(void) |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1485 | { |
Thomas Gleixner | 6d2d49d | 2015-01-15 21:22:27 +0000 | [diff] [blame] | 1486 | u32 x2apic_id; |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1487 | |
Thomas Gleixner | 6d2d49d | 2015-01-15 21:22:27 +0000 | [diff] [blame] | 1488 | if (x2apic_state != X2APIC_ON) |
| 1489 | goto out; |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1490 | |
Thomas Gleixner | 6d2d49d | 2015-01-15 21:22:27 +0000 | [diff] [blame] | 1491 | x2apic_id = read_apic_id(); |
| 1492 | if (x2apic_id >= 255) |
| 1493 | panic("Cannot disable x2apic, id: %08x\n", x2apic_id); |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1494 | |
Thomas Gleixner | 6d2d49d | 2015-01-15 21:22:27 +0000 | [diff] [blame] | 1495 | __x2apic_disable(); |
| 1496 | register_lapic_address(mp_lapic_addr); |
| 1497 | out: |
Thomas Gleixner | 12e189d | 2015-01-15 21:22:22 +0000 | [diff] [blame] | 1498 | x2apic_state = X2APIC_DISABLED; |
Thomas Gleixner | 6d2d49d | 2015-01-15 21:22:27 +0000 | [diff] [blame] | 1499 | x2apic_mode = 0; |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1500 | } |
| 1501 | |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1502 | static __init void x2apic_enable(void) |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1503 | { |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1504 | if (x2apic_state != X2APIC_OFF) |
Yinghai Lu | 06cd9a7 | 2009-02-16 17:29:58 -0800 | [diff] [blame] | 1505 | return; |
| 1506 | |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1507 | x2apic_mode = 1; |
Thomas Gleixner | 12e189d | 2015-01-15 21:22:22 +0000 | [diff] [blame] | 1508 | x2apic_state = X2APIC_ON; |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1509 | __x2apic_enable(); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1510 | } |
Thomas Gleixner | d524165 | 2015-01-15 21:22:17 +0000 | [diff] [blame] | 1511 | |
Thomas Gleixner | 62e6163 | 2015-01-15 21:22:21 +0000 | [diff] [blame] | 1512 | static __init void try_to_enable_x2apic(int remap_mode) |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1513 | { |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1514 | if (x2apic_state == X2APIC_DISABLED) |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1515 | return; |
| 1516 | |
Thomas Gleixner | 62e6163 | 2015-01-15 21:22:21 +0000 | [diff] [blame] | 1517 | if (remap_mode != IRQ_REMAP_X2APIC_MODE) { |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1518 | /* IR is required if there is APIC ID > 255 even when running |
| 1519 | * under KVM |
| 1520 | */ |
| 1521 | if (max_physical_apicid > 255 || |
Linus Torvalds | 8329aa9 | 2015-02-13 10:26:18 -0800 | [diff] [blame] | 1522 | !hypervisor_x2apic_available()) { |
Thomas Gleixner | 62e6163 | 2015-01-15 21:22:21 +0000 | [diff] [blame] | 1523 | pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); |
Thomas Gleixner | 44e25ff | 2015-01-15 21:22:24 +0000 | [diff] [blame] | 1524 | x2apic_disable(); |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1525 | return; |
| 1526 | } |
| 1527 | |
| 1528 | /* |
| 1529 | * without IR all CPUs can be addressed by IOAPIC/MSI |
| 1530 | * only in physical mode |
| 1531 | */ |
Thomas Gleixner | 55eae7d | 2015-01-15 21:22:19 +0000 | [diff] [blame] | 1532 | x2apic_phys = 1; |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1533 | } |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1534 | x2apic_enable(); |
Thomas Gleixner | 55eae7d | 2015-01-15 21:22:19 +0000 | [diff] [blame] | 1535 | } |
| 1536 | |
| 1537 | void __init check_x2apic(void) |
| 1538 | { |
| 1539 | if (x2apic_enabled()) { |
| 1540 | pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); |
| 1541 | x2apic_mode = 1; |
Thomas Gleixner | 12e189d | 2015-01-15 21:22:22 +0000 | [diff] [blame] | 1542 | x2apic_state = X2APIC_ON; |
| 1543 | } else if (!cpu_has_x2apic) { |
| 1544 | x2apic_state = X2APIC_DISABLED; |
Thomas Gleixner | 55eae7d | 2015-01-15 21:22:19 +0000 | [diff] [blame] | 1545 | } |
| 1546 | } |
| 1547 | #else /* CONFIG_X86_X2APIC */ |
| 1548 | static int __init validate_x2apic(void) |
| 1549 | { |
| 1550 | if (!apic_is_x2apic_enabled()) |
| 1551 | return 0; |
| 1552 | /* |
| 1553 | * Checkme: Can we simply turn off x2apic here instead of panic? |
| 1554 | */ |
| 1555 | panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); |
| 1556 | } |
| 1557 | early_initcall(validate_x2apic); |
| 1558 | |
Thomas Gleixner | 62e6163 | 2015-01-15 21:22:21 +0000 | [diff] [blame] | 1559 | static inline void try_to_enable_x2apic(int remap_mode) { } |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1560 | static inline void __x2apic_enable(void) { } |
Thomas Gleixner | 55eae7d | 2015-01-15 21:22:19 +0000 | [diff] [blame] | 1561 | #endif /* !CONFIG_X86_X2APIC */ |
| 1562 | |
| 1563 | static int __init try_to_enable_IR(void) |
| 1564 | { |
| 1565 | #ifdef CONFIG_X86_IO_APIC |
| 1566 | if (!x2apic_enabled() && skip_ioapic_setup) { |
| 1567 | pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); |
| 1568 | return -1; |
| 1569 | } |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1570 | #endif |
Thomas Gleixner | 55eae7d | 2015-01-15 21:22:19 +0000 | [diff] [blame] | 1571 | return irq_remapping_enable(); |
Gleb Natapov | ce69a78 | 2009-07-20 15:24:17 +0300 | [diff] [blame] | 1572 | } |
| 1573 | |
| 1574 | void __init enable_IR_x2apic(void) |
| 1575 | { |
| 1576 | unsigned long flags; |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1577 | int ret, ir_stat; |
Yinghai Lu | b7f42ab | 2009-08-17 11:19:40 -0700 | [diff] [blame] | 1578 | |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1579 | ir_stat = irq_remapping_prepare(); |
| 1580 | if (ir_stat < 0 && !x2apic_supported()) |
Yinghai Lu | e670761 | 2009-11-21 00:23:37 -0800 | [diff] [blame] | 1581 | return; |
Gleb Natapov | ce69a78 | 2009-07-20 15:24:17 +0300 | [diff] [blame] | 1582 | |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 1583 | ret = save_ioapic_entries(); |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 1584 | if (ret) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1585 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1586 | return; |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 1587 | } |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1588 | |
Suresh Siddha | 05c3dc2 | 2009-03-16 17:05:03 -0700 | [diff] [blame] | 1589 | local_irq_save(flags); |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 1590 | legacy_pic->mask_all(); |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 1591 | mask_ioapic_entries(); |
Suresh Siddha | 05c3dc2 | 2009-03-16 17:05:03 -0700 | [diff] [blame] | 1592 | |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1593 | /* If irq_remapping_prepare() succeded, try to enable it */ |
| 1594 | if (ir_stat >= 0) |
| 1595 | ir_stat = try_to_enable_IR(); |
| 1596 | /* ir_stat contains the remap mode or an error code */ |
| 1597 | try_to_enable_x2apic(ir_stat); |
Yinghai Lu | a31bc32 | 2011-12-23 11:01:43 -0800 | [diff] [blame] | 1598 | |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1599 | if (ir_stat < 0) |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 1600 | restore_ioapic_entries(); |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 1601 | legacy_pic->restore_mask(); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1602 | local_irq_restore(flags); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1603 | } |
Weidong Han | 9375823 | 2009-04-17 16:42:14 +0800 | [diff] [blame] | 1604 | |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1605 | #ifdef CONFIG_X86_64 |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1606 | /* |
| 1607 | * Detect and enable local APICs on non-SMP boards. |
| 1608 | * Original code written by Keir Fraser. |
| 1609 | * On AMD64 we trust the BIOS - if it says no APIC it is likely |
| 1610 | * not correctly set up (usually the APIC timer won't work etc.) |
| 1611 | */ |
| 1612 | static int __init detect_init_APIC(void) |
| 1613 | { |
| 1614 | if (!cpu_has_apic) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1615 | pr_info("No local APIC present\n"); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1616 | return -1; |
| 1617 | } |
| 1618 | |
| 1619 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1620 | return 0; |
| 1621 | } |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1622 | #else |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1623 | |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 1624 | static int __init apic_verify(void) |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1625 | { |
| 1626 | u32 features, h, l; |
| 1627 | |
| 1628 | /* |
| 1629 | * The APIC feature bit should now be enabled |
| 1630 | * in `cpuid' |
| 1631 | */ |
| 1632 | features = cpuid_edx(1); |
| 1633 | if (!(features & (1 << X86_FEATURE_APIC))) { |
| 1634 | pr_warning("Could not enable APIC!\n"); |
| 1635 | return -1; |
| 1636 | } |
| 1637 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
| 1638 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
| 1639 | |
| 1640 | /* The BIOS may have set up the APIC at some other address */ |
Bryan O'Donoghue | cbf2829 | 2012-04-18 17:37:39 +0100 | [diff] [blame] | 1641 | if (boot_cpu_data.x86 >= 6) { |
| 1642 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 1643 | if (l & MSR_IA32_APICBASE_ENABLE) |
| 1644 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; |
| 1645 | } |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1646 | |
| 1647 | pr_info("Found and enabled local APIC!\n"); |
| 1648 | return 0; |
| 1649 | } |
| 1650 | |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 1651 | int __init apic_force_enable(unsigned long addr) |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1652 | { |
| 1653 | u32 h, l; |
| 1654 | |
| 1655 | if (disable_apic) |
| 1656 | return -1; |
| 1657 | |
| 1658 | /* |
| 1659 | * Some BIOSes disable the local APIC in the APIC_BASE |
| 1660 | * MSR. This can only be done in software for Intel P6 or later |
| 1661 | * and AMD K7 (Model > 1) or later. |
| 1662 | */ |
Bryan O'Donoghue | cbf2829 | 2012-04-18 17:37:39 +0100 | [diff] [blame] | 1663 | if (boot_cpu_data.x86 >= 6) { |
| 1664 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 1665 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { |
| 1666 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); |
| 1667 | l &= ~MSR_IA32_APICBASE_BASE; |
| 1668 | l |= MSR_IA32_APICBASE_ENABLE | addr; |
| 1669 | wrmsr(MSR_IA32_APICBASE, l, h); |
| 1670 | enabled_via_apicbase = 1; |
| 1671 | } |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1672 | } |
| 1673 | return apic_verify(); |
| 1674 | } |
| 1675 | |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1676 | /* |
| 1677 | * Detect and initialize APIC |
| 1678 | */ |
| 1679 | static int __init detect_init_APIC(void) |
| 1680 | { |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1681 | /* Disabled by kernel option? */ |
| 1682 | if (disable_apic) |
| 1683 | return -1; |
| 1684 | |
| 1685 | switch (boot_cpu_data.x86_vendor) { |
| 1686 | case X86_VENDOR_AMD: |
| 1687 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || |
Borislav Petkov | 8587706 | 2009-02-03 16:24:22 +0100 | [diff] [blame] | 1688 | (boot_cpu_data.x86 >= 15)) |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1689 | break; |
| 1690 | goto no_apic; |
| 1691 | case X86_VENDOR_INTEL: |
| 1692 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || |
| 1693 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) |
| 1694 | break; |
| 1695 | goto no_apic; |
| 1696 | default: |
| 1697 | goto no_apic; |
| 1698 | } |
| 1699 | |
| 1700 | if (!cpu_has_apic) { |
| 1701 | /* |
| 1702 | * Over-ride BIOS and try to enable the local APIC only if |
| 1703 | * "lapic" specified. |
| 1704 | */ |
| 1705 | if (!force_enable_local_apic) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1706 | pr_info("Local APIC disabled by BIOS -- " |
| 1707 | "you can enable it with \"lapic\"\n"); |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1708 | return -1; |
| 1709 | } |
Thomas Gleixner | a906fda | 2011-02-25 16:09:31 +0100 | [diff] [blame] | 1710 | if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1711 | return -1; |
| 1712 | } else { |
| 1713 | if (apic_verify()) |
| 1714 | return -1; |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1715 | } |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1716 | |
| 1717 | apic_pm_activate(); |
| 1718 | |
| 1719 | return 0; |
| 1720 | |
| 1721 | no_apic: |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1722 | pr_info("No local APIC present or hardware disabled\n"); |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1723 | return -1; |
| 1724 | } |
| 1725 | #endif |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1726 | |
| 1727 | /** |
| 1728 | * init_apic_mappings - initialize APIC mappings |
| 1729 | */ |
| 1730 | void __init init_apic_mappings(void) |
| 1731 | { |
Yinghai Lu | 4401da6 | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1732 | unsigned int new_apicid; |
| 1733 | |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 1734 | if (x2apic_mode) { |
Yinghai Lu | 4c9961d | 2008-07-11 18:44:16 -0700 | [diff] [blame] | 1735 | boot_cpu_physical_apicid = read_apic_id(); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1736 | return; |
| 1737 | } |
| 1738 | |
Yinghai Lu | 4797f6b | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1739 | /* If no local APIC can be found return early */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1740 | if (!smp_found_config && detect_init_APIC()) { |
Yinghai Lu | 4797f6b | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1741 | /* lets NOP'ify apic operations */ |
Cyrill Gorcunov | cec6be6 | 2009-05-11 17:41:40 +0400 | [diff] [blame] | 1742 | pr_info("APIC: disable apic facility\n"); |
| 1743 | apic_disable(); |
Yinghai Lu | 4797f6b | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1744 | } else { |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1745 | apic_phys = mp_lapic_addr; |
| 1746 | |
Yinghai Lu | 4797f6b | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1747 | /* |
| 1748 | * acpi lapic path already maps that address in |
| 1749 | * acpi_register_lapic_address() |
| 1750 | */ |
Eric W. Biederman | 5989cd6 | 2010-08-04 13:30:27 -0700 | [diff] [blame] | 1751 | if (!acpi_lapic && !smp_found_config) |
Yinghai Lu | 326a2e6 | 2010-12-07 00:55:38 -0800 | [diff] [blame] | 1752 | register_lapic_address(apic_phys); |
Cyrill Gorcunov | cec6be6 | 2009-05-11 17:41:40 +0400 | [diff] [blame] | 1753 | } |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1754 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1755 | /* |
| 1756 | * Fetch the APIC ID of the BSP in case we have a |
| 1757 | * default configuration (or the MP table is broken). |
| 1758 | */ |
Yinghai Lu | 4401da6 | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1759 | new_apicid = read_apic_id(); |
| 1760 | if (boot_cpu_physical_apicid != new_apicid) { |
| 1761 | boot_cpu_physical_apicid = new_apicid; |
Cyrill Gorcunov | 103428e | 2009-06-07 16:48:40 +0400 | [diff] [blame] | 1762 | /* |
| 1763 | * yeah -- we lie about apic_version |
| 1764 | * in case if apic was disabled via boot option |
| 1765 | * but it's not a problem for SMP compiled kernel |
| 1766 | * since smp_sanity_check is prepared for such a case |
| 1767 | * and disable smp mode |
| 1768 | */ |
Yinghai Lu | 4401da6 | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1769 | apic_version[new_apicid] = |
| 1770 | GET_APIC_VERSION(apic_read(APIC_LVR)); |
Cyrill Gorcunov | 08306ce | 2009-04-12 20:47:41 +0400 | [diff] [blame] | 1771 | } |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1772 | } |
| 1773 | |
Yinghai Lu | c0104d3 | 2010-12-07 00:55:17 -0800 | [diff] [blame] | 1774 | void __init register_lapic_address(unsigned long address) |
| 1775 | { |
| 1776 | mp_lapic_addr = address; |
| 1777 | |
Yinghai Lu | 0450193 | 2010-12-07 00:55:56 -0800 | [diff] [blame] | 1778 | if (!x2apic_mode) { |
| 1779 | set_fixmap_nocache(FIX_APIC_BASE, address); |
| 1780 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
| 1781 | APIC_BASE, mp_lapic_addr); |
| 1782 | } |
Yinghai Lu | c0104d3 | 2010-12-07 00:55:17 -0800 | [diff] [blame] | 1783 | if (boot_cpu_physical_apicid == -1U) { |
| 1784 | boot_cpu_physical_apicid = read_apic_id(); |
| 1785 | apic_version[boot_cpu_physical_apicid] = |
| 1786 | GET_APIC_VERSION(apic_read(APIC_LVR)); |
| 1787 | } |
| 1788 | } |
| 1789 | |
Yinghai Lu | 56d91f1 | 2010-12-16 19:09:24 -0800 | [diff] [blame] | 1790 | int apic_version[MAX_LOCAL_APIC]; |
Cyrill Gorcunov | 1b313f4 | 2008-08-18 20:45:57 +0400 | [diff] [blame] | 1791 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1792 | /* |
| 1793 | * Local APIC interrupts |
| 1794 | */ |
| 1795 | |
| 1796 | /* |
| 1797 | * This interrupt should _never_ happen with our APIC/SMP architecture |
| 1798 | */ |
Jan Beulich | 2414e02 | 2014-11-03 08:39:43 +0000 | [diff] [blame] | 1799 | static inline void __smp_spurious_interrupt(u8 vector) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1800 | { |
Yinghai Lu | dc1528d | 2008-08-24 02:01:53 -0700 | [diff] [blame] | 1801 | u32 v; |
| 1802 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1803 | /* |
| 1804 | * Check if this really is a spurious interrupt and ACK it |
| 1805 | * if it is a vectored one. Just in case... |
| 1806 | * Spurious interrupts should not be ACKed. |
| 1807 | */ |
Jan Beulich | 2414e02 | 2014-11-03 08:39:43 +0000 | [diff] [blame] | 1808 | v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); |
| 1809 | if (v & (1 << (vector & 0x1f))) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1810 | ack_APIC_irq(); |
| 1811 | |
Hiroshi Shimamoto | 915b0d0 | 2008-12-08 19:19:26 -0800 | [diff] [blame] | 1812 | inc_irq_stat(irq_spurious_count); |
| 1813 | |
Yinghai Lu | dc1528d | 2008-08-24 02:01:53 -0700 | [diff] [blame] | 1814 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
Jan Beulich | 2414e02 | 2014-11-03 08:39:43 +0000 | [diff] [blame] | 1815 | pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " |
| 1816 | "should never happen.\n", vector, smp_processor_id()); |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 1817 | } |
| 1818 | |
Andi Kleen | 1d9090e | 2013-08-05 15:02:37 -0700 | [diff] [blame] | 1819 | __visible void smp_spurious_interrupt(struct pt_regs *regs) |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 1820 | { |
| 1821 | entering_irq(); |
Jan Beulich | 2414e02 | 2014-11-03 08:39:43 +0000 | [diff] [blame] | 1822 | __smp_spurious_interrupt(~regs->orig_ax); |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 1823 | exiting_irq(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1824 | } |
| 1825 | |
Andi Kleen | 1d9090e | 2013-08-05 15:02:37 -0700 | [diff] [blame] | 1826 | __visible void smp_trace_spurious_interrupt(struct pt_regs *regs) |
Seiji Aguchi | cf910e8 | 2013-06-20 11:46:53 -0400 | [diff] [blame] | 1827 | { |
Jan Beulich | 2414e02 | 2014-11-03 08:39:43 +0000 | [diff] [blame] | 1828 | u8 vector = ~regs->orig_ax; |
| 1829 | |
Seiji Aguchi | cf910e8 | 2013-06-20 11:46:53 -0400 | [diff] [blame] | 1830 | entering_irq(); |
Jan Beulich | 2414e02 | 2014-11-03 08:39:43 +0000 | [diff] [blame] | 1831 | trace_spurious_apic_entry(vector); |
| 1832 | __smp_spurious_interrupt(vector); |
| 1833 | trace_spurious_apic_exit(vector); |
Seiji Aguchi | cf910e8 | 2013-06-20 11:46:53 -0400 | [diff] [blame] | 1834 | exiting_irq(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1835 | } |
| 1836 | |
| 1837 | /* |
| 1838 | * This interrupt should never happen with our APIC/SMP architecture |
| 1839 | */ |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 1840 | static inline void __smp_error_interrupt(struct pt_regs *regs) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1841 | { |
Richard Weinberger | 60283df | 2014-01-14 08:44:47 +0100 | [diff] [blame] | 1842 | u32 v; |
Youquan Song | 2b398bd | 2011-04-14 14:36:08 +0800 | [diff] [blame] | 1843 | u32 i = 0; |
| 1844 | static const char * const error_interrupt_reason[] = { |
| 1845 | "Send CS error", /* APIC Error Bit 0 */ |
| 1846 | "Receive CS error", /* APIC Error Bit 1 */ |
| 1847 | "Send accept error", /* APIC Error Bit 2 */ |
| 1848 | "Receive accept error", /* APIC Error Bit 3 */ |
| 1849 | "Redirectable IPI", /* APIC Error Bit 4 */ |
| 1850 | "Send illegal vector", /* APIC Error Bit 5 */ |
| 1851 | "Received illegal vector", /* APIC Error Bit 6 */ |
| 1852 | "Illegal register address", /* APIC Error Bit 7 */ |
| 1853 | }; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1854 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1855 | /* First tickle the hardware, only then report what went on. -- REW */ |
Maciej W. Rozycki | 023de4a | 2014-04-01 13:30:21 +0100 | [diff] [blame] | 1856 | if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ |
| 1857 | apic_write(APIC_ESR, 0); |
Richard Weinberger | 60283df | 2014-01-14 08:44:47 +0100 | [diff] [blame] | 1858 | v = apic_read(APIC_ESR); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1859 | ack_APIC_irq(); |
| 1860 | atomic_inc(&irq_err_count); |
| 1861 | |
Richard Weinberger | 60283df | 2014-01-14 08:44:47 +0100 | [diff] [blame] | 1862 | apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", |
| 1863 | smp_processor_id(), v); |
Youquan Song | 2b398bd | 2011-04-14 14:36:08 +0800 | [diff] [blame] | 1864 | |
Richard Weinberger | 60283df | 2014-01-14 08:44:47 +0100 | [diff] [blame] | 1865 | v &= 0xff; |
| 1866 | while (v) { |
| 1867 | if (v & 0x1) |
Youquan Song | 2b398bd | 2011-04-14 14:36:08 +0800 | [diff] [blame] | 1868 | apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); |
| 1869 | i++; |
Richard Weinberger | 60283df | 2014-01-14 08:44:47 +0100 | [diff] [blame] | 1870 | v >>= 1; |
Peter Senna Tschudin | 4b8073e | 2012-09-18 18:36:14 +0200 | [diff] [blame] | 1871 | } |
Youquan Song | 2b398bd | 2011-04-14 14:36:08 +0800 | [diff] [blame] | 1872 | |
| 1873 | apic_printk(APIC_DEBUG, KERN_CONT "\n"); |
| 1874 | |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 1875 | } |
| 1876 | |
Andi Kleen | 1d9090e | 2013-08-05 15:02:37 -0700 | [diff] [blame] | 1877 | __visible void smp_error_interrupt(struct pt_regs *regs) |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 1878 | { |
| 1879 | entering_irq(); |
| 1880 | __smp_error_interrupt(regs); |
| 1881 | exiting_irq(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1882 | } |
| 1883 | |
Andi Kleen | 1d9090e | 2013-08-05 15:02:37 -0700 | [diff] [blame] | 1884 | __visible void smp_trace_error_interrupt(struct pt_regs *regs) |
Seiji Aguchi | cf910e8 | 2013-06-20 11:46:53 -0400 | [diff] [blame] | 1885 | { |
| 1886 | entering_irq(); |
| 1887 | trace_error_apic_entry(ERROR_APIC_VECTOR); |
| 1888 | __smp_error_interrupt(regs); |
| 1889 | trace_error_apic_exit(ERROR_APIC_VECTOR); |
| 1890 | exiting_irq(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1891 | } |
| 1892 | |
Glauber Costa | b584176 | 2008-05-28 13:38:28 -0300 | [diff] [blame] | 1893 | /** |
Cyrill Gorcunov | 36c9d67 | 2008-08-18 20:45:53 +0400 | [diff] [blame] | 1894 | * connect_bsp_APIC - attach the APIC to the interrupt system |
| 1895 | */ |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 1896 | static void __init connect_bsp_APIC(void) |
Glauber Costa | b584176 | 2008-05-28 13:38:28 -0300 | [diff] [blame] | 1897 | { |
Cyrill Gorcunov | 36c9d67 | 2008-08-18 20:45:53 +0400 | [diff] [blame] | 1898 | #ifdef CONFIG_X86_32 |
| 1899 | if (pic_mode) { |
| 1900 | /* |
| 1901 | * Do not trust the local APIC being empty at bootup. |
| 1902 | */ |
| 1903 | clear_local_APIC(); |
| 1904 | /* |
| 1905 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's |
| 1906 | * local APIC to INT and NMI lines. |
| 1907 | */ |
| 1908 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " |
| 1909 | "enabling APIC mode.\n"); |
Cyrill Gorcunov | c0eaa45 | 2009-04-12 20:47:40 +0400 | [diff] [blame] | 1910 | imcr_pic_to_apic(); |
Cyrill Gorcunov | 36c9d67 | 2008-08-18 20:45:53 +0400 | [diff] [blame] | 1911 | } |
| 1912 | #endif |
Glauber Costa | b584176 | 2008-05-28 13:38:28 -0300 | [diff] [blame] | 1913 | } |
| 1914 | |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 1915 | /** |
| 1916 | * disconnect_bsp_APIC - detach the APIC from the interrupt system |
| 1917 | * @virt_wire_setup: indicates, whether virtual wire mode is selected |
| 1918 | * |
| 1919 | * Virtual wire mode is necessary to deliver legacy interrupts even when the |
| 1920 | * APIC is disabled. |
| 1921 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1922 | void disconnect_bsp_APIC(int virt_wire_setup) |
| 1923 | { |
Cyrill Gorcunov | 1b4ee4e | 2008-08-18 23:12:33 +0400 | [diff] [blame] | 1924 | unsigned int value; |
| 1925 | |
Cyrill Gorcunov | c177b0b | 2008-08-18 20:45:56 +0400 | [diff] [blame] | 1926 | #ifdef CONFIG_X86_32 |
| 1927 | if (pic_mode) { |
| 1928 | /* |
| 1929 | * Put the board back into PIC mode (has an effect only on |
| 1930 | * certain older boards). Note that APIC interrupts, including |
| 1931 | * IPIs, won't work beyond this point! The only exception are |
| 1932 | * INIT IPIs. |
| 1933 | */ |
| 1934 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " |
| 1935 | "entering PIC mode.\n"); |
Cyrill Gorcunov | c0eaa45 | 2009-04-12 20:47:40 +0400 | [diff] [blame] | 1936 | imcr_apic_to_pic(); |
Cyrill Gorcunov | c177b0b | 2008-08-18 20:45:56 +0400 | [diff] [blame] | 1937 | return; |
| 1938 | } |
| 1939 | #endif |
| 1940 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1941 | /* Go back to Virtual Wire compatibility mode */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1942 | |
| 1943 | /* For the spurious interrupt use vector F, and enable it */ |
| 1944 | value = apic_read(APIC_SPIV); |
| 1945 | value &= ~APIC_VECTOR_MASK; |
| 1946 | value |= APIC_SPIV_APIC_ENABLED; |
| 1947 | value |= 0xf; |
| 1948 | apic_write(APIC_SPIV, value); |
| 1949 | |
| 1950 | if (!virt_wire_setup) { |
| 1951 | /* |
| 1952 | * For LVT0 make it edge triggered, active high, |
| 1953 | * external and enabled |
| 1954 | */ |
| 1955 | value = apic_read(APIC_LVT0); |
| 1956 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | |
| 1957 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
| 1958 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
| 1959 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
| 1960 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); |
| 1961 | apic_write(APIC_LVT0, value); |
| 1962 | } else { |
| 1963 | /* Disable LVT0 */ |
| 1964 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
| 1965 | } |
| 1966 | |
Cyrill Gorcunov | c177b0b | 2008-08-18 20:45:56 +0400 | [diff] [blame] | 1967 | /* |
| 1968 | * For LVT1 make it edge triggered, active high, |
| 1969 | * nmi and enabled |
| 1970 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1971 | value = apic_read(APIC_LVT1); |
| 1972 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | |
| 1973 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
| 1974 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
| 1975 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
| 1976 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); |
| 1977 | apic_write(APIC_LVT1, value); |
| 1978 | } |
| 1979 | |
Jiang Liu | 7e1f85f | 2013-09-02 11:57:36 +0800 | [diff] [blame] | 1980 | int generic_processor_info(int apicid, int version) |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 1981 | { |
Vivek Goyal | 14cb6dc | 2011-07-08 13:19:26 -0400 | [diff] [blame] | 1982 | int cpu, max = nr_cpu_ids; |
| 1983 | bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, |
| 1984 | phys_cpu_present_map); |
| 1985 | |
| 1986 | /* |
HATAYAMA Daisuke | 151e0c7 | 2014-01-15 15:44:58 +0900 | [diff] [blame] | 1987 | * boot_cpu_physical_apicid is designed to have the apicid |
| 1988 | * returned by read_apic_id(), i.e, the apicid of the |
| 1989 | * currently booting-up processor. However, on some platforms, |
H. Peter Anvin | 5b4d1db | 2014-01-15 13:02:08 -0800 | [diff] [blame] | 1990 | * it is temporarily modified by the apicid reported as BSP |
HATAYAMA Daisuke | 151e0c7 | 2014-01-15 15:44:58 +0900 | [diff] [blame] | 1991 | * through MP table. Concretely: |
| 1992 | * |
| 1993 | * - arch/x86/kernel/mpparse.c: MP_processor_info() |
| 1994 | * - arch/x86/mm/amdtopology.c: amd_numa_init() |
HATAYAMA Daisuke | 151e0c7 | 2014-01-15 15:44:58 +0900 | [diff] [blame] | 1995 | * |
| 1996 | * This function is executed with the modified |
| 1997 | * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel |
| 1998 | * parameter doesn't work to disable APs on kdump 2nd kernel. |
| 1999 | * |
| 2000 | * Since fixing handling of boot_cpu_physical_apicid requires |
| 2001 | * another discussion and tests on each platform, we leave it |
| 2002 | * for now and here we use read_apic_id() directly in this |
| 2003 | * function, generic_processor_info(). |
| 2004 | */ |
| 2005 | if (disabled_cpu_apicid != BAD_APICID && |
| 2006 | disabled_cpu_apicid != read_apic_id() && |
| 2007 | disabled_cpu_apicid == apicid) { |
| 2008 | int thiscpu = num_processors + disabled_cpus; |
| 2009 | |
H. Peter Anvin | 5b4d1db | 2014-01-15 13:02:08 -0800 | [diff] [blame] | 2010 | pr_warning("APIC: Disabling requested cpu." |
HATAYAMA Daisuke | 151e0c7 | 2014-01-15 15:44:58 +0900 | [diff] [blame] | 2011 | " Processor %d/0x%x ignored.\n", |
| 2012 | thiscpu, apicid); |
| 2013 | |
| 2014 | disabled_cpus++; |
| 2015 | return -ENODEV; |
| 2016 | } |
| 2017 | |
| 2018 | /* |
Vivek Goyal | 14cb6dc | 2011-07-08 13:19:26 -0400 | [diff] [blame] | 2019 | * If boot cpu has not been detected yet, then only allow upto |
| 2020 | * nr_cpu_ids - 1 processors and keep one slot free for boot cpu |
| 2021 | */ |
| 2022 | if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && |
| 2023 | apicid != boot_cpu_physical_apicid) { |
| 2024 | int thiscpu = max + disabled_cpus - 1; |
| 2025 | |
| 2026 | pr_warning( |
| 2027 | "ACPI: NR_CPUS/possible_cpus limit of %i almost" |
| 2028 | " reached. Keeping one slot for boot cpu." |
| 2029 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); |
| 2030 | |
| 2031 | disabled_cpus++; |
Jiang Liu | 7e1f85f | 2013-09-02 11:57:36 +0800 | [diff] [blame] | 2032 | return -ENODEV; |
Vivek Goyal | 14cb6dc | 2011-07-08 13:19:26 -0400 | [diff] [blame] | 2033 | } |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2034 | |
Mike Travis | 3b11ce7 | 2008-12-17 15:21:39 -0800 | [diff] [blame] | 2035 | if (num_processors >= nr_cpu_ids) { |
Mike Travis | 3b11ce7 | 2008-12-17 15:21:39 -0800 | [diff] [blame] | 2036 | int thiscpu = max + disabled_cpus; |
| 2037 | |
| 2038 | pr_warning( |
| 2039 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." |
| 2040 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); |
| 2041 | |
| 2042 | disabled_cpus++; |
Jiang Liu | 7e1f85f | 2013-09-02 11:57:36 +0800 | [diff] [blame] | 2043 | return -EINVAL; |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2044 | } |
| 2045 | |
| 2046 | num_processors++; |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2047 | if (apicid == boot_cpu_physical_apicid) { |
| 2048 | /* |
| 2049 | * x86_bios_cpu_apicid is required to have processors listed |
| 2050 | * in same order as logical cpu numbers. Hence the first |
| 2051 | * entry is BSP, and so on. |
Yinghai Lu | e5fea86 | 2011-02-08 23:22:17 -0800 | [diff] [blame] | 2052 | * boot_cpu_init() already hold bit 0 in cpu_present_mask |
| 2053 | * for BSP. |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2054 | */ |
| 2055 | cpu = 0; |
Yinghai Lu | e5fea86 | 2011-02-08 23:22:17 -0800 | [diff] [blame] | 2056 | } else |
| 2057 | cpu = cpumask_next_zero(-1, cpu_present_mask); |
| 2058 | |
| 2059 | /* |
| 2060 | * Validate version |
| 2061 | */ |
| 2062 | if (version == 0x0) { |
| 2063 | pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", |
| 2064 | cpu, apicid); |
| 2065 | version = 0x10; |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2066 | } |
Yinghai Lu | e5fea86 | 2011-02-08 23:22:17 -0800 | [diff] [blame] | 2067 | apic_version[apicid] = version; |
| 2068 | |
| 2069 | if (version != apic_version[boot_cpu_physical_apicid]) { |
| 2070 | pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", |
| 2071 | apic_version[boot_cpu_physical_apicid], cpu, version); |
| 2072 | } |
| 2073 | |
| 2074 | physid_set(apicid, phys_cpu_present_map); |
Yinghai Lu | e0da336 | 2008-06-08 18:29:22 -0700 | [diff] [blame] | 2075 | if (apicid > max_physical_apicid) |
| 2076 | max_physical_apicid = apicid; |
| 2077 | |
Ingo Molnar | 3e5095d | 2009-01-27 17:07:08 +0100 | [diff] [blame] | 2078 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
Tejun Heo | f10fcd4 | 2009-01-13 20:41:34 +0900 | [diff] [blame] | 2079 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
| 2080 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; |
Cyrill Gorcunov | 1b313f4 | 2008-08-18 20:45:57 +0400 | [diff] [blame] | 2081 | #endif |
Tejun Heo | acb8bc0 | 2011-01-23 14:37:33 +0100 | [diff] [blame] | 2082 | #ifdef CONFIG_X86_32 |
| 2083 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = |
| 2084 | apic->x86_32_early_logical_apicid(cpu); |
| 2085 | #endif |
Mike Travis | 1de88cd | 2008-12-16 17:34:02 -0800 | [diff] [blame] | 2086 | set_cpu_possible(cpu, true); |
| 2087 | set_cpu_present(cpu, true); |
Jiang Liu | 7e1f85f | 2013-09-02 11:57:36 +0800 | [diff] [blame] | 2088 | |
| 2089 | return cpu; |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2090 | } |
| 2091 | |
Suresh Siddha | 0c81c74 | 2008-07-10 11:16:48 -0700 | [diff] [blame] | 2092 | int hard_smp_processor_id(void) |
| 2093 | { |
| 2094 | return read_apic_id(); |
| 2095 | } |
Ingo Molnar | 1dcdd3d | 2009-01-28 17:55:37 +0100 | [diff] [blame] | 2096 | |
| 2097 | void default_init_apic_ldr(void) |
| 2098 | { |
| 2099 | unsigned long val; |
| 2100 | |
| 2101 | apic_write(APIC_DFR, APIC_DFR_VALUE); |
| 2102 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; |
| 2103 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); |
| 2104 | apic_write(APIC_LDR, val); |
| 2105 | } |
| 2106 | |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 2107 | int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
| 2108 | const struct cpumask *andmask, |
| 2109 | unsigned int *apicid) |
Alexander Gordeev | 6398268 | 2012-06-05 13:23:44 +0200 | [diff] [blame] | 2110 | { |
Alexander Gordeev | ea3807e | 2012-06-14 09:49:55 +0200 | [diff] [blame] | 2111 | unsigned int cpu; |
Alexander Gordeev | 6398268 | 2012-06-05 13:23:44 +0200 | [diff] [blame] | 2112 | |
| 2113 | for_each_cpu_and(cpu, cpumask, andmask) { |
| 2114 | if (cpumask_test_cpu(cpu, cpu_online_mask)) |
| 2115 | break; |
| 2116 | } |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 2117 | |
Alexander Gordeev | ea3807e | 2012-06-14 09:49:55 +0200 | [diff] [blame] | 2118 | if (likely(cpu < nr_cpu_ids)) { |
Alexander Gordeev | a5a3915 | 2012-06-14 09:49:35 +0200 | [diff] [blame] | 2119 | *apicid = per_cpu(x86_cpu_to_apicid, cpu); |
| 2120 | return 0; |
Alexander Gordeev | a5a3915 | 2012-06-14 09:49:35 +0200 | [diff] [blame] | 2121 | } |
Alexander Gordeev | ea3807e | 2012-06-14 09:49:55 +0200 | [diff] [blame] | 2122 | |
| 2123 | return -EINVAL; |
Alexander Gordeev | 6398268 | 2012-06-05 13:23:44 +0200 | [diff] [blame] | 2124 | } |
| 2125 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 2126 | /* |
Michael S. Tsirkin | 1551df6 | 2012-07-15 15:56:46 +0300 | [diff] [blame] | 2127 | * Override the generic EOI implementation with an optimized version. |
| 2128 | * Only called during early boot when only one CPU is active and with |
| 2129 | * interrupts disabled, so we know this does not race with actual APIC driver |
| 2130 | * use. |
| 2131 | */ |
| 2132 | void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) |
| 2133 | { |
| 2134 | struct apic **drv; |
| 2135 | |
| 2136 | for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { |
| 2137 | /* Should happen once for each apic */ |
| 2138 | WARN_ON((*drv)->eoi_write == eoi_write); |
| 2139 | (*drv)->eoi_write = eoi_write; |
| 2140 | } |
| 2141 | } |
| 2142 | |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2143 | static void __init apic_bsp_up_setup(void) |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2144 | { |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2145 | #ifdef CONFIG_X86_64 |
| 2146 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
| 2147 | #else |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2148 | /* |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2149 | * Hack: In case of kdump, after a crash, kernel might be booting |
| 2150 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid |
| 2151 | * might be zero if read from MP tables. Get it from LAPIC. |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2152 | */ |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2153 | # ifdef CONFIG_CRASH_DUMP |
| 2154 | boot_cpu_physical_apicid = read_apic_id(); |
| 2155 | # endif |
| 2156 | #endif |
| 2157 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2158 | } |
| 2159 | |
| 2160 | /** |
| 2161 | * apic_bsp_setup - Setup function for local apic and io-apic |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2162 | * @upmode: Force UP mode (for APIC_init_uniprocessor) |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2163 | * |
| 2164 | * Returns: |
| 2165 | * apic_id of BSP APIC |
| 2166 | */ |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2167 | int __init apic_bsp_setup(bool upmode) |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2168 | { |
| 2169 | int id; |
| 2170 | |
| 2171 | connect_bsp_APIC(); |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2172 | if (upmode) |
| 2173 | apic_bsp_up_setup(); |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2174 | setup_local_APIC(); |
| 2175 | |
| 2176 | if (x2apic_mode) |
| 2177 | id = apic_read(APIC_LDR); |
| 2178 | else |
| 2179 | id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); |
| 2180 | |
| 2181 | enable_IO_APIC(); |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2182 | end_local_APIC_setup(); |
| 2183 | irq_remap_enable_fault_handling(); |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2184 | setup_IO_APIC(); |
Thomas Gleixner | 9c4d9c7 | 2015-01-15 21:22:45 +0000 | [diff] [blame] | 2185 | /* Setup local timer */ |
| 2186 | x86_init.timers.setup_percpu_clockev(); |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2187 | return id; |
| 2188 | } |
| 2189 | |
Michael S. Tsirkin | 1551df6 | 2012-07-15 15:56:46 +0300 | [diff] [blame] | 2190 | /* |
Thomas Gleixner | e714a91 | 2015-01-15 21:22:37 +0000 | [diff] [blame] | 2191 | * This initializes the IO-APIC and APIC hardware if this is |
| 2192 | * a UP kernel. |
| 2193 | */ |
| 2194 | int __init APIC_init_uniprocessor(void) |
| 2195 | { |
| 2196 | if (disable_apic) { |
| 2197 | pr_info("Apic disabled\n"); |
| 2198 | return -1; |
| 2199 | } |
| 2200 | #ifdef CONFIG_X86_64 |
| 2201 | if (!cpu_has_apic) { |
| 2202 | disable_apic = 1; |
| 2203 | pr_info("Apic disabled by BIOS\n"); |
| 2204 | return -1; |
| 2205 | } |
| 2206 | #else |
| 2207 | if (!smp_found_config && !cpu_has_apic) |
| 2208 | return -1; |
| 2209 | |
| 2210 | /* |
| 2211 | * Complain if the BIOS pretends there is one. |
| 2212 | */ |
| 2213 | if (!cpu_has_apic && |
| 2214 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
| 2215 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
| 2216 | boot_cpu_physical_apicid); |
| 2217 | return -1; |
| 2218 | } |
| 2219 | #endif |
| 2220 | |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2221 | if (!smp_found_config) |
| 2222 | disable_ioapic_support(); |
| 2223 | |
Thomas Gleixner | e714a91 | 2015-01-15 21:22:37 +0000 | [diff] [blame] | 2224 | default_setup_apic_routing(); |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2225 | apic_bsp_setup(true); |
Thomas Gleixner | e714a91 | 2015-01-15 21:22:37 +0000 | [diff] [blame] | 2226 | return 0; |
| 2227 | } |
| 2228 | |
Thomas Gleixner | 30b8b00 | 2015-01-15 21:22:39 +0000 | [diff] [blame] | 2229 | #ifdef CONFIG_UP_LATE_INIT |
| 2230 | void __init up_late_init(void) |
| 2231 | { |
| 2232 | APIC_init_uniprocessor(); |
| 2233 | } |
| 2234 | #endif |
| 2235 | |
Thomas Gleixner | e714a91 | 2015-01-15 21:22:37 +0000 | [diff] [blame] | 2236 | /* |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 2237 | * Power management |
| 2238 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2239 | #ifdef CONFIG_PM |
| 2240 | |
| 2241 | static struct { |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 2242 | /* |
| 2243 | * 'active' is true if the local APIC was enabled by us and |
| 2244 | * not the BIOS; this signifies that we are also responsible |
| 2245 | * for disabling it before entering apm/acpi suspend |
| 2246 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2247 | int active; |
| 2248 | /* r/w apic fields */ |
| 2249 | unsigned int apic_id; |
| 2250 | unsigned int apic_taskpri; |
| 2251 | unsigned int apic_ldr; |
| 2252 | unsigned int apic_dfr; |
| 2253 | unsigned int apic_spiv; |
| 2254 | unsigned int apic_lvtt; |
| 2255 | unsigned int apic_lvtpc; |
| 2256 | unsigned int apic_lvt0; |
| 2257 | unsigned int apic_lvt1; |
| 2258 | unsigned int apic_lvterr; |
| 2259 | unsigned int apic_tmict; |
| 2260 | unsigned int apic_tdcr; |
| 2261 | unsigned int apic_thmr; |
| 2262 | } apic_pm_state; |
| 2263 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2264 | static int lapic_suspend(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2265 | { |
| 2266 | unsigned long flags; |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2267 | int maxlvt; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2268 | |
| 2269 | if (!apic_pm_state.active) |
| 2270 | return 0; |
| 2271 | |
Thomas Gleixner | 37e650c | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 2272 | maxlvt = lapic_get_maxlvt(); |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2273 | |
Suresh Siddha | 2d7a66d | 2008-07-11 14:24:19 -0700 | [diff] [blame] | 2274 | apic_pm_state.apic_id = apic_read(APIC_ID); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2275 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
| 2276 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); |
| 2277 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); |
| 2278 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); |
| 2279 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2280 | if (maxlvt >= 4) |
| 2281 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2282 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); |
| 2283 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); |
| 2284 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); |
| 2285 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); |
| 2286 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 2287 | #ifdef CONFIG_X86_THERMAL_VECTOR |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2288 | if (maxlvt >= 5) |
| 2289 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); |
| 2290 | #endif |
Cyrill Gorcunov | 24968cf | 2008-08-16 23:21:52 +0400 | [diff] [blame] | 2291 | |
Fernando Luis Vázquez Cao | 2b94ab2 | 2006-09-26 10:52:33 +0200 | [diff] [blame] | 2292 | local_irq_save(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2293 | disable_local_APIC(); |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 2294 | |
Joerg Roedel | 70733e0 | 2012-09-26 12:44:33 +0200 | [diff] [blame] | 2295 | irq_remapping_disable(); |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 2296 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2297 | local_irq_restore(flags); |
| 2298 | return 0; |
| 2299 | } |
| 2300 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2301 | static void lapic_resume(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2302 | { |
| 2303 | unsigned int l, h; |
| 2304 | unsigned long flags; |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 2305 | int maxlvt; |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 2306 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2307 | if (!apic_pm_state.active) |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2308 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2309 | |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 2310 | local_irq_save(flags); |
Joerg Roedel | 336224b | 2012-09-26 12:44:34 +0200 | [diff] [blame] | 2311 | |
| 2312 | /* |
| 2313 | * IO-APIC and PIC have their own resume routines. |
| 2314 | * We just mask them here to make sure the interrupt |
| 2315 | * subsystem is completely quiet while we enable x2apic |
| 2316 | * and interrupt-remapping. |
| 2317 | */ |
| 2318 | mask_ioapic_entries(); |
| 2319 | legacy_pic->mask_all(); |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2320 | |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 2321 | if (x2apic_mode) { |
| 2322 | __x2apic_enable(); |
| 2323 | } else { |
Cyrill Gorcunov | 92206c9 | 2008-08-16 23:21:51 +0400 | [diff] [blame] | 2324 | /* |
| 2325 | * Make sure the APICBASE points to the right address |
| 2326 | * |
| 2327 | * FIXME! This will be wrong if we ever support suspend on |
| 2328 | * SMP! We'll need to do this as part of the CPU restore! |
| 2329 | */ |
Bryan O'Donoghue | cbf2829 | 2012-04-18 17:37:39 +0100 | [diff] [blame] | 2330 | if (boot_cpu_data.x86 >= 6) { |
| 2331 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 2332 | l &= ~MSR_IA32_APICBASE_BASE; |
| 2333 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; |
| 2334 | wrmsr(MSR_IA32_APICBASE, l, h); |
| 2335 | } |
Yinghai Lu | d5e629a | 2008-08-17 21:12:27 -0700 | [diff] [blame] | 2336 | } |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 2337 | |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 2338 | maxlvt = lapic_get_maxlvt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2339 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
| 2340 | apic_write(APIC_ID, apic_pm_state.apic_id); |
| 2341 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); |
| 2342 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); |
| 2343 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); |
| 2344 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); |
| 2345 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); |
| 2346 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); |
Paul Bolle | 71c69f7 | 2013-05-29 20:57:30 +0200 | [diff] [blame] | 2347 | #if defined(CONFIG_X86_MCE_INTEL) |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2348 | if (maxlvt >= 5) |
| 2349 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); |
| 2350 | #endif |
| 2351 | if (maxlvt >= 4) |
| 2352 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2353 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); |
| 2354 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); |
| 2355 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); |
| 2356 | apic_write(APIC_ESR, 0); |
| 2357 | apic_read(APIC_ESR); |
| 2358 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); |
| 2359 | apic_write(APIC_ESR, 0); |
| 2360 | apic_read(APIC_ESR); |
Cyrill Gorcunov | 92206c9 | 2008-08-16 23:21:51 +0400 | [diff] [blame] | 2361 | |
Joerg Roedel | 70733e0 | 2012-09-26 12:44:33 +0200 | [diff] [blame] | 2362 | irq_remapping_reenable(x2apic_mode); |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 2363 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2364 | local_irq_restore(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2365 | } |
| 2366 | |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 2367 | /* |
| 2368 | * This device has no shutdown method - fully functioning local APICs |
| 2369 | * are needed on every CPU up until machine_halt/restart/poweroff. |
| 2370 | */ |
| 2371 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2372 | static struct syscore_ops lapic_syscore_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2373 | .resume = lapic_resume, |
| 2374 | .suspend = lapic_suspend, |
| 2375 | }; |
| 2376 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 2377 | static void apic_pm_activate(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2378 | { |
| 2379 | apic_pm_state.active = 1; |
| 2380 | } |
| 2381 | |
| 2382 | static int __init init_lapic_sysfs(void) |
| 2383 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2384 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2385 | if (cpu_has_apic) |
| 2386 | register_syscore_ops(&lapic_syscore_ops); |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 2387 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2388 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2389 | } |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 2390 | |
| 2391 | /* local apic needs to resume before other devices access its registers. */ |
| 2392 | core_initcall(init_lapic_sysfs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2393 | |
| 2394 | #else /* CONFIG_PM */ |
| 2395 | |
| 2396 | static void apic_pm_activate(void) { } |
| 2397 | |
| 2398 | #endif /* CONFIG_PM */ |
| 2399 | |
Yinghai Lu | f28c0ae | 2008-08-24 02:01:49 -0700 | [diff] [blame] | 2400 | #ifdef CONFIG_X86_64 |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2401 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 2402 | static int multi_checked; |
| 2403 | static int multi; |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2404 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 2405 | static int set_multi(const struct dmi_system_id *d) |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2406 | { |
| 2407 | if (multi) |
| 2408 | return 0; |
Cyrill Gorcunov | 6f0aced | 2009-05-01 23:54:25 +0400 | [diff] [blame] | 2409 | pr_info("APIC: %s detected, Multi Chassis\n", d->ident); |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2410 | multi = 1; |
| 2411 | return 0; |
| 2412 | } |
| 2413 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 2414 | static const struct dmi_system_id multi_dmi_table[] = { |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2415 | { |
| 2416 | .callback = set_multi, |
| 2417 | .ident = "IBM System Summit2", |
| 2418 | .matches = { |
| 2419 | DMI_MATCH(DMI_SYS_VENDOR, "IBM"), |
| 2420 | DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), |
| 2421 | }, |
| 2422 | }, |
| 2423 | {} |
| 2424 | }; |
| 2425 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 2426 | static void dmi_check_multi(void) |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2427 | { |
| 2428 | if (multi_checked) |
| 2429 | return; |
| 2430 | |
| 2431 | dmi_check_system(multi_dmi_table); |
| 2432 | multi_checked = 1; |
| 2433 | } |
| 2434 | |
| 2435 | /* |
| 2436 | * apic_is_clustered_box() -- Check if we can expect good TSC |
| 2437 | * |
| 2438 | * Thus far, the major user of this is IBM's Summit2 series: |
| 2439 | * Clustered boxes may have unsynced TSC problems if they are |
| 2440 | * multi-chassis. |
| 2441 | * Use DMI to check them |
| 2442 | */ |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 2443 | int apic_is_clustered_box(void) |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2444 | { |
| 2445 | dmi_check_multi(); |
Oren Twaig | 411cf9e | 2014-06-29 13:01:08 +0300 | [diff] [blame] | 2446 | return multi; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2447 | } |
Yinghai Lu | f28c0ae | 2008-08-24 02:01:49 -0700 | [diff] [blame] | 2448 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2449 | |
| 2450 | /* |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 2451 | * APIC command line parameters |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2452 | */ |
Cyrill Gorcunov | 789fa73 | 2008-08-18 20:46:01 +0400 | [diff] [blame] | 2453 | static int __init setup_disableapic(char *arg) |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2454 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2455 | disable_apic = 1; |
Yinghai Lu | 9175fc0 | 2008-07-21 01:38:14 -0700 | [diff] [blame] | 2456 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
Andi Kleen | 2c8c0e6 | 2006-09-26 10:52:32 +0200 | [diff] [blame] | 2457 | return 0; |
| 2458 | } |
| 2459 | early_param("disableapic", setup_disableapic); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2460 | |
Andi Kleen | 2c8c0e6 | 2006-09-26 10:52:32 +0200 | [diff] [blame] | 2461 | /* same as disableapic, for compatibility */ |
Cyrill Gorcunov | 789fa73 | 2008-08-18 20:46:01 +0400 | [diff] [blame] | 2462 | static int __init setup_nolapic(char *arg) |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2463 | { |
Cyrill Gorcunov | 789fa73 | 2008-08-18 20:46:01 +0400 | [diff] [blame] | 2464 | return setup_disableapic(arg); |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2465 | } |
Andi Kleen | 2c8c0e6 | 2006-09-26 10:52:32 +0200 | [diff] [blame] | 2466 | early_param("nolapic", setup_nolapic); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2467 | |
Linus Torvalds | 2e7c283 | 2007-03-23 11:32:31 -0700 | [diff] [blame] | 2468 | static int __init parse_lapic_timer_c2_ok(char *arg) |
| 2469 | { |
| 2470 | local_apic_timer_c2_ok = 1; |
| 2471 | return 0; |
| 2472 | } |
| 2473 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); |
| 2474 | |
Cyrill Gorcunov | 36fef09 | 2008-08-15 13:51:20 +0200 | [diff] [blame] | 2475 | static int __init parse_disable_apic_timer(char *arg) |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2476 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2477 | disable_apic_timer = 1; |
Cyrill Gorcunov | 36fef09 | 2008-08-15 13:51:20 +0200 | [diff] [blame] | 2478 | return 0; |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2479 | } |
Cyrill Gorcunov | 36fef09 | 2008-08-15 13:51:20 +0200 | [diff] [blame] | 2480 | early_param("noapictimer", parse_disable_apic_timer); |
| 2481 | |
| 2482 | static int __init parse_nolapic_timer(char *arg) |
| 2483 | { |
| 2484 | disable_apic_timer = 1; |
| 2485 | return 0; |
| 2486 | } |
| 2487 | early_param("nolapic_timer", parse_nolapic_timer); |
Andi Kleen | 73dea47 | 2006-02-03 21:50:50 +0100 | [diff] [blame] | 2488 | |
Cyrill Gorcunov | 79af9be | 2008-08-18 20:46:00 +0400 | [diff] [blame] | 2489 | static int __init apic_set_verbosity(char *arg) |
| 2490 | { |
| 2491 | if (!arg) { |
| 2492 | #ifdef CONFIG_X86_64 |
| 2493 | skip_ioapic_setup = 0; |
Cyrill Gorcunov | 79af9be | 2008-08-18 20:46:00 +0400 | [diff] [blame] | 2494 | return 0; |
| 2495 | #endif |
| 2496 | return -EINVAL; |
| 2497 | } |
| 2498 | |
| 2499 | if (strcmp("debug", arg) == 0) |
| 2500 | apic_verbosity = APIC_DEBUG; |
| 2501 | else if (strcmp("verbose", arg) == 0) |
| 2502 | apic_verbosity = APIC_VERBOSE; |
| 2503 | else { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 2504 | pr_warning("APIC Verbosity level %s not recognised" |
Cyrill Gorcunov | 79af9be | 2008-08-18 20:46:00 +0400 | [diff] [blame] | 2505 | " use apic=verbose or apic=debug\n", arg); |
| 2506 | return -EINVAL; |
| 2507 | } |
| 2508 | |
| 2509 | return 0; |
| 2510 | } |
| 2511 | early_param("apic", apic_set_verbosity); |
| 2512 | |
Yinghai Lu | 1e934dd | 2008-02-22 13:37:26 -0800 | [diff] [blame] | 2513 | static int __init lapic_insert_resource(void) |
| 2514 | { |
| 2515 | if (!apic_phys) |
| 2516 | return -1; |
| 2517 | |
| 2518 | /* Put local APIC into the resource map. */ |
| 2519 | lapic_resource.start = apic_phys; |
| 2520 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; |
| 2521 | insert_resource(&iomem_resource, &lapic_resource); |
| 2522 | |
| 2523 | return 0; |
| 2524 | } |
| 2525 | |
| 2526 | /* |
| 2527 | * need call insert after e820_reserve_resources() |
| 2528 | * that is using request_resource |
| 2529 | */ |
| 2530 | late_initcall(lapic_insert_resource); |
HATAYAMA Daisuke | 151e0c7 | 2014-01-15 15:44:58 +0900 | [diff] [blame] | 2531 | |
| 2532 | static int __init apic_set_disabled_cpu_apicid(char *arg) |
| 2533 | { |
| 2534 | if (!arg || !get_option(&arg, &disabled_cpu_apicid)) |
| 2535 | return -EINVAL; |
| 2536 | |
| 2537 | return 0; |
| 2538 | } |
| 2539 | early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); |