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Stefan Roese8bc4a512008-03-01 03:25:29 +11001/*
2 * Device Tree Source for AMCC Canyonlands (460EX)
3 *
Stefan Roese88eeb722009-07-29 07:05:01 +00004 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
Stefan Roese8bc4a512008-03-01 03:25:29 +11005 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
David Gibson71f34972008-05-15 16:46:39 +100011/dts-v1/;
12
Stefan Roese8bc4a512008-03-01 03:25:29 +110013/ {
14 #address-cells = <2>;
15 #size-cells = <1>;
16 model = "amcc,canyonlands";
17 compatible = "amcc,canyonlands";
David Gibson71f34972008-05-15 16:46:39 +100018 dcr-parent = <&{/cpus/cpu@0}>;
Stefan Roese8bc4a512008-03-01 03:25:29 +110019
20 aliases {
21 ethernet0 = &EMAC0;
22 ethernet1 = &EMAC1;
23 serial0 = &UART0;
24 serial1 = &UART1;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 model = "PowerPC,460EX";
David Gibson71f34972008-05-15 16:46:39 +100034 reg = <0x00000000>;
Stefan Roese8bc4a512008-03-01 03:25:29 +110035 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
David Gibson71f34972008-05-15 16:46:39 +100037 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
39 i-cache-size = <32768>;
40 d-cache-size = <32768>;
Stefan Roese8bc4a512008-03-01 03:25:29 +110041 dcr-controller;
42 dcr-access-method = "native";
Stefan Roesecd854002008-12-05 01:58:49 +000043 next-level-cache = <&L2C0>;
Stefan Roese8bc4a512008-03-01 03:25:29 +110044 };
45 };
46
47 memory {
48 device_type = "memory";
David Gibson71f34972008-05-15 16:46:39 +100049 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
Stefan Roese8bc4a512008-03-01 03:25:29 +110050 };
51
52 UIC0: interrupt-controller0 {
53 compatible = "ibm,uic-460ex","ibm,uic";
54 interrupt-controller;
55 cell-index = <0>;
David Gibson71f34972008-05-15 16:46:39 +100056 dcr-reg = <0x0c0 0x009>;
Stefan Roese8bc4a512008-03-01 03:25:29 +110057 #address-cells = <0>;
58 #size-cells = <0>;
59 #interrupt-cells = <2>;
60 };
61
62 UIC1: interrupt-controller1 {
63 compatible = "ibm,uic-460ex","ibm,uic";
64 interrupt-controller;
65 cell-index = <1>;
David Gibson71f34972008-05-15 16:46:39 +100066 dcr-reg = <0x0d0 0x009>;
Stefan Roese8bc4a512008-03-01 03:25:29 +110067 #address-cells = <0>;
68 #size-cells = <0>;
69 #interrupt-cells = <2>;
David Gibson71f34972008-05-15 16:46:39 +100070 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
Stefan Roese8bc4a512008-03-01 03:25:29 +110071 interrupt-parent = <&UIC0>;
72 };
73
74 UIC2: interrupt-controller2 {
75 compatible = "ibm,uic-460ex","ibm,uic";
76 interrupt-controller;
77 cell-index = <2>;
David Gibson71f34972008-05-15 16:46:39 +100078 dcr-reg = <0x0e0 0x009>;
Stefan Roese8bc4a512008-03-01 03:25:29 +110079 #address-cells = <0>;
80 #size-cells = <0>;
81 #interrupt-cells = <2>;
David Gibson71f34972008-05-15 16:46:39 +100082 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
Stefan Roese8bc4a512008-03-01 03:25:29 +110083 interrupt-parent = <&UIC0>;
84 };
85
86 UIC3: interrupt-controller3 {
87 compatible = "ibm,uic-460ex","ibm,uic";
88 interrupt-controller;
89 cell-index = <3>;
David Gibson71f34972008-05-15 16:46:39 +100090 dcr-reg = <0x0f0 0x009>;
Stefan Roese8bc4a512008-03-01 03:25:29 +110091 #address-cells = <0>;
92 #size-cells = <0>;
93 #interrupt-cells = <2>;
David Gibson71f34972008-05-15 16:46:39 +100094 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
Stefan Roese8bc4a512008-03-01 03:25:29 +110095 interrupt-parent = <&UIC0>;
96 };
97
98 SDR0: sdr {
99 compatible = "ibm,sdr-460ex";
David Gibson71f34972008-05-15 16:46:39 +1000100 dcr-reg = <0x00e 0x002>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100101 };
102
103 CPR0: cpr {
104 compatible = "ibm,cpr-460ex";
David Gibson71f34972008-05-15 16:46:39 +1000105 dcr-reg = <0x00c 0x002>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100106 };
107
Victor Gallardoee2ffd82010-10-08 10:25:44 +0000108 CPM0: cpm {
109 compatible = "ibm,cpm";
110 dcr-access-method = "native";
111 dcr-reg = <0x160 0x003>;
112 unused-units = <0x00000100>;
113 idle-doze = <0x02000000>;
114 standby = <0xfeff791d>;
115 };
116
Stefan Roesecd854002008-12-05 01:58:49 +0000117 L2C0: l2c {
118 compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
119 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
120 0x030 0x008>; /* L2 cache DCR's */
121 cache-line-size = <32>; /* 32 bytes */
122 cache-size = <262144>; /* L2, 256K */
123 interrupt-parent = <&UIC1>;
124 interrupts = <11 1>;
125 };
126
Stefan Roese8bc4a512008-03-01 03:25:29 +1100127 plb {
128 compatible = "ibm,plb-460ex", "ibm,plb4";
129 #address-cells = <2>;
130 #size-cells = <1>;
131 ranges;
132 clock-frequency = <0>; /* Filled in by U-Boot */
133
134 SDRAM0: sdram {
135 compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
David Gibson71f34972008-05-15 16:46:39 +1000136 dcr-reg = <0x010 0x002>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100137 };
138
James Hsiao049359d2009-02-05 16:18:13 +1100139 CRYPTO: crypto@180000 {
140 compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
141 reg = <4 0x00180000 0x80400>;
142 interrupt-parent = <&UIC0>;
143 interrupts = <0x1d 0x4>;
144 };
145
Mike Williams57308492011-06-22 06:09:43 +0000146 HWRNG: hwrng@110000 {
147 compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
148 reg = <4 0x00110000 0x50>;
149 };
150
Stefan Roese8bc4a512008-03-01 03:25:29 +1100151 MAL0: mcmal {
152 compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
David Gibson71f34972008-05-15 16:46:39 +1000153 dcr-reg = <0x180 0x062>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100154 num-tx-chans = <2>;
David Gibson71f34972008-05-15 16:46:39 +1000155 num-rx-chans = <16>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100156 #address-cells = <0>;
157 #size-cells = <0>;
158 interrupt-parent = <&UIC2>;
David Gibson71f34972008-05-15 16:46:39 +1000159 interrupts = < /*TXEOB*/ 0x6 0x4
160 /*RXEOB*/ 0x7 0x4
161 /*SERR*/ 0x3 0x4
162 /*TXDE*/ 0x4 0x4
163 /*RXDE*/ 0x5 0x4>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100164 };
165
Stefan Roese88eeb722009-07-29 07:05:01 +0000166 USB0: ehci@bffd0400 {
167 compatible = "ibm,usb-ehci-460ex", "usb-ehci";
168 interrupt-parent = <&UIC2>;
169 interrupts = <0x1d 4>;
170 reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
171 };
Benjamin Herrenschmidt018f76e2009-02-01 16:50:55 +0000172
Stefan Roese88eeb722009-07-29 07:05:01 +0000173 USB1: usb@bffd0000 {
174 compatible = "ohci-le";
175 reg = <4 0xbffd0000 0x60>;
176 interrupt-parent = <&UIC2>;
177 interrupts = <0x1e 4>;
178 };
Benjamin Herrenschmidt018f76e2009-02-01 16:50:55 +0000179
Tirumala Marric89b3452010-12-08 14:49:05 +0000180 USBOTG0: usbotg@bff80000 {
181 compatible = "amcc,dwc-otg";
182 reg = <0x4 0xbff80000 0x10000>;
183 interrupt-parent = <&USBOTG0>;
184 #interrupt-cells = <1>;
185 #address-cells = <0>;
186 #size-cells = <0>;
187 interrupts = <0x0 0x1 0x2>;
188 interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
189 /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
190 /* DMA */ 0x2 &UIC0 0xc 0x4>;
191 };
192
Rupjyoti Sarmah31fc0bd2010-06-04 00:03:12 +0000193 SATA0: sata@bffd1000 {
194 compatible = "amcc,sata-460ex";
195 reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>;
196 interrupt-parent = <&UIC3>;
197 interrupts = <0x0 0x4 /* SATA */
198 0x5 0x4>; /* AHBDMA */
199 };
200
Stefan Roese8bc4a512008-03-01 03:25:29 +1100201 POB0: opb {
202 compatible = "ibm,opb-460ex", "ibm,opb";
203 #address-cells = <1>;
204 #size-cells = <1>;
David Gibson71f34972008-05-15 16:46:39 +1000205 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100206 clock-frequency = <0>; /* Filled in by U-Boot */
207
208 EBC0: ebc {
209 compatible = "ibm,ebc-460ex", "ibm,ebc";
David Gibson71f34972008-05-15 16:46:39 +1000210 dcr-reg = <0x012 0x002>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100211 #address-cells = <2>;
212 #size-cells = <1>;
213 clock-frequency = <0>; /* Filled in by U-Boot */
Stefan Roese50202312008-04-19 19:57:18 +1000214 /* ranges property is supplied by U-Boot */
David Gibson71f34972008-05-15 16:46:39 +1000215 interrupts = <0x6 0x4>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100216 interrupt-parent = <&UIC1>;
Stefan Roese50202312008-04-19 19:57:18 +1000217
218 nor_flash@0,0 {
219 compatible = "amd,s29gl512n", "cfi-flash";
220 bank-width = <2>;
David Gibson71f34972008-05-15 16:46:39 +1000221 reg = <0x00000000 0x00000000 0x04000000>;
Stefan Roese50202312008-04-19 19:57:18 +1000222 #address-cells = <1>;
223 #size-cells = <1>;
224 partition@0 {
225 label = "kernel";
David Gibson71f34972008-05-15 16:46:39 +1000226 reg = <0x00000000 0x001e0000>;
Stefan Roese50202312008-04-19 19:57:18 +1000227 };
228 partition@1e0000 {
229 label = "dtb";
David Gibson71f34972008-05-15 16:46:39 +1000230 reg = <0x001e0000 0x00020000>;
Stefan Roese50202312008-04-19 19:57:18 +1000231 };
232 partition@200000 {
233 label = "ramdisk";
David Gibson71f34972008-05-15 16:46:39 +1000234 reg = <0x00200000 0x01400000>;
Stefan Roese50202312008-04-19 19:57:18 +1000235 };
236 partition@1600000 {
237 label = "jffs2";
David Gibson71f34972008-05-15 16:46:39 +1000238 reg = <0x01600000 0x00400000>;
Stefan Roese50202312008-04-19 19:57:18 +1000239 };
240 partition@1a00000 {
241 label = "user";
David Gibson71f34972008-05-15 16:46:39 +1000242 reg = <0x01a00000 0x02560000>;
Stefan Roese50202312008-04-19 19:57:18 +1000243 };
244 partition@3f60000 {
245 label = "env";
David Gibson71f34972008-05-15 16:46:39 +1000246 reg = <0x03f60000 0x00040000>;
Stefan Roese50202312008-04-19 19:57:18 +1000247 };
248 partition@3fa0000 {
249 label = "u-boot";
David Gibson71f34972008-05-15 16:46:39 +1000250 reg = <0x03fa0000 0x00060000>;
Stefan Roese50202312008-04-19 19:57:18 +1000251 };
252 };
Stefan Roese88eeb722009-07-29 07:05:01 +0000253
Rupjyoti Sarmah8960f7f2010-12-15 02:27:10 +0000254 cpld@2,0 {
255 compatible = "amcc,ppc460ex-bcsr";
256 reg = <2 0x0 0x9>;
257 };
258
Stefan Roese88eeb722009-07-29 07:05:01 +0000259 ndfc@3,0 {
260 compatible = "ibm,ndfc";
261 reg = <0x00000003 0x00000000 0x00002000>;
262 ccr = <0x00001000>;
263 bank-settings = <0x80002222>;
264 #address-cells = <1>;
265 #size-cells = <1>;
266
267 nand {
268 #address-cells = <1>;
269 #size-cells = <1>;
270
271 partition@0 {
272 label = "u-boot";
273 reg = <0x00000000 0x00100000>;
274 };
275 partition@100000 {
276 label = "user";
277 reg = <0x00000000 0x03f00000>;
278 };
279 };
280 };
Stefan Roese8bc4a512008-03-01 03:25:29 +1100281 };
282
283 UART0: serial@ef600300 {
284 device_type = "serial";
285 compatible = "ns16550";
David Gibson71f34972008-05-15 16:46:39 +1000286 reg = <0xef600300 0x00000008>;
287 virtual-reg = <0xef600300>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100288 clock-frequency = <0>; /* Filled in by U-Boot */
289 current-speed = <0>; /* Filled in by U-Boot */
290 interrupt-parent = <&UIC1>;
David Gibson71f34972008-05-15 16:46:39 +1000291 interrupts = <0x1 0x4>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100292 };
293
294 UART1: serial@ef600400 {
295 device_type = "serial";
296 compatible = "ns16550";
David Gibson71f34972008-05-15 16:46:39 +1000297 reg = <0xef600400 0x00000008>;
298 virtual-reg = <0xef600400>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100299 clock-frequency = <0>; /* Filled in by U-Boot */
300 current-speed = <0>; /* Filled in by U-Boot */
301 interrupt-parent = <&UIC0>;
David Gibson71f34972008-05-15 16:46:39 +1000302 interrupts = <0x1 0x4>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100303 };
304
Stefan Roese8bc4a512008-03-01 03:25:29 +1100305 IIC0: i2c@ef600700 {
306 compatible = "ibm,iic-460ex", "ibm,iic";
David Gibson71f34972008-05-15 16:46:39 +1000307 reg = <0xef600700 0x00000014>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100308 interrupt-parent = <&UIC0>;
David Gibson71f34972008-05-15 16:46:39 +1000309 interrupts = <0x2 0x4>;
Benjamin Herrenschmidt018f76e2009-02-01 16:50:55 +0000310 #address-cells = <1>;
311 #size-cells = <0>;
312 rtc@68 {
313 compatible = "stm,m41t80";
314 reg = <0x68>;
315 interrupt-parent = <&UIC2>;
316 interrupts = <0x19 0x8>;
317 };
318 sttm@48 {
319 compatible = "ad,ad7414";
320 reg = <0x48>;
321 interrupt-parent = <&UIC1>;
322 interrupts = <0x14 0x8>;
323 };
Stefan Roese8bc4a512008-03-01 03:25:29 +1100324 };
325
326 IIC1: i2c@ef600800 {
327 compatible = "ibm,iic-460ex", "ibm,iic";
David Gibson71f34972008-05-15 16:46:39 +1000328 reg = <0xef600800 0x00000014>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100329 interrupt-parent = <&UIC0>;
David Gibson71f34972008-05-15 16:46:39 +1000330 interrupts = <0x3 0x4>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100331 };
332
Rupjyoti Sarmah8960f7f2010-12-15 02:27:10 +0000333 GPIO0: gpio@ef600b00 {
334 compatible = "ibm,ppc4xx-gpio";
335 reg = <0xef600b00 0x00000048>;
336 gpio-controller;
337 };
338
Stefan Roese8bc4a512008-03-01 03:25:29 +1100339 ZMII0: emac-zmii@ef600d00 {
340 compatible = "ibm,zmii-460ex", "ibm,zmii";
David Gibson71f34972008-05-15 16:46:39 +1000341 reg = <0xef600d00 0x0000000c>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100342 };
343
344 RGMII0: emac-rgmii@ef601500 {
345 compatible = "ibm,rgmii-460ex", "ibm,rgmii";
David Gibson71f34972008-05-15 16:46:39 +1000346 reg = <0xef601500 0x00000008>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100347 has-mdio;
348 };
349
Stefan Roesea6190a82008-04-04 00:35:06 +1100350 TAH0: emac-tah@ef601350 {
351 compatible = "ibm,tah-460ex", "ibm,tah";
David Gibson71f34972008-05-15 16:46:39 +1000352 reg = <0xef601350 0x00000030>;
Stefan Roesea6190a82008-04-04 00:35:06 +1100353 };
354
355 TAH1: emac-tah@ef601450 {
356 compatible = "ibm,tah-460ex", "ibm,tah";
David Gibson71f34972008-05-15 16:46:39 +1000357 reg = <0xef601450 0x00000030>;
Stefan Roesea6190a82008-04-04 00:35:06 +1100358 };
359
Stefan Roese8bc4a512008-03-01 03:25:29 +1100360 EMAC0: ethernet@ef600e00 {
361 device_type = "network";
Grant Erickson05781cc2008-07-08 08:03:11 +1000362 compatible = "ibm,emac-460ex", "ibm,emac4sync";
Stefan Roese8bc4a512008-03-01 03:25:29 +1100363 interrupt-parent = <&EMAC0>;
David Gibson71f34972008-05-15 16:46:39 +1000364 interrupts = <0x0 0x1>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100365 #interrupt-cells = <1>;
366 #address-cells = <0>;
367 #size-cells = <0>;
David Gibson71f34972008-05-15 16:46:39 +1000368 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
369 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
Grant Erickson05781cc2008-07-08 08:03:11 +1000370 reg = <0xef600e00 0x000000c4>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100371 local-mac-address = [000000000000]; /* Filled in by U-Boot */
372 mal-device = <&MAL0>;
373 mal-tx-channel = <0>;
374 mal-rx-channel = <0>;
375 cell-index = <0>;
David Gibson71f34972008-05-15 16:46:39 +1000376 max-frame-size = <9000>;
377 rx-fifo-size = <4096>;
378 tx-fifo-size = <2048>;
Dave Mitchell835ad8e2009-10-08 06:33:29 +0000379 rx-fifo-size-gige = <16384>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100380 phy-mode = "rgmii";
David Gibson71f34972008-05-15 16:46:39 +1000381 phy-map = <0x00000000>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100382 rgmii-device = <&RGMII0>;
383 rgmii-channel = <0>;
Stefan Roesea6190a82008-04-04 00:35:06 +1100384 tah-device = <&TAH0>;
385 tah-channel = <0>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100386 has-inverted-stacr-oc;
387 has-new-stacr-staopc;
388 };
389
390 EMAC1: ethernet@ef600f00 {
391 device_type = "network";
Grant Erickson05781cc2008-07-08 08:03:11 +1000392 compatible = "ibm,emac-460ex", "ibm,emac4sync";
Stefan Roese8bc4a512008-03-01 03:25:29 +1100393 interrupt-parent = <&EMAC1>;
David Gibson71f34972008-05-15 16:46:39 +1000394 interrupts = <0x0 0x1>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100395 #interrupt-cells = <1>;
396 #address-cells = <0>;
397 #size-cells = <0>;
David Gibson71f34972008-05-15 16:46:39 +1000398 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
399 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
Grant Erickson05781cc2008-07-08 08:03:11 +1000400 reg = <0xef600f00 0x000000c4>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100401 local-mac-address = [000000000000]; /* Filled in by U-Boot */
402 mal-device = <&MAL0>;
403 mal-tx-channel = <1>;
404 mal-rx-channel = <8>;
405 cell-index = <1>;
David Gibson71f34972008-05-15 16:46:39 +1000406 max-frame-size = <9000>;
407 rx-fifo-size = <4096>;
408 tx-fifo-size = <2048>;
Dave Mitchell835ad8e2009-10-08 06:33:29 +0000409 rx-fifo-size-gige = <16384>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100410 phy-mode = "rgmii";
David Gibson71f34972008-05-15 16:46:39 +1000411 phy-map = <0x00000000>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100412 rgmii-device = <&RGMII0>;
413 rgmii-channel = <1>;
Stefan Roesea6190a82008-04-04 00:35:06 +1100414 tah-device = <&TAH1>;
415 tah-channel = <1>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100416 has-inverted-stacr-oc;
417 has-new-stacr-staopc;
Stefan Roesea6190a82008-04-04 00:35:06 +1100418 mdio-device = <&EMAC0>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100419 };
420 };
421
422 PCIX0: pci@c0ec00000 {
423 device_type = "pci";
424 #interrupt-cells = <1>;
425 #size-cells = <2>;
426 #address-cells = <3>;
427 compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
428 primary;
429 large-inbound-windows;
430 enable-msi-hole;
David Gibson71f34972008-05-15 16:46:39 +1000431 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
432 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
433 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
434 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
435 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
Stefan Roese8bc4a512008-03-01 03:25:29 +1100436
437 /* Outbound ranges, one memory and one IO,
438 * later cannot be changed
439 */
David Gibson71f34972008-05-15 16:46:39 +1000440 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
Benjamin Herrenschmidt84d727a2008-10-09 16:58:19 +0000441 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
David Gibson71f34972008-05-15 16:46:39 +1000442 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100443
444 /* Inbound 2GB range starting at 0 */
David Gibson71f34972008-05-15 16:46:39 +1000445 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100446
447 /* This drives busses 0 to 0x3f */
David Gibson71f34972008-05-15 16:46:39 +1000448 bus-range = <0x0 0x3f>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100449
450 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
David Gibson71f34972008-05-15 16:46:39 +1000451 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
452 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100453 };
454
455 PCIE0: pciex@d00000000 {
456 device_type = "pci";
457 #interrupt-cells = <1>;
458 #size-cells = <2>;
459 #address-cells = <3>;
460 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
461 primary;
David Gibson71f34972008-05-15 16:46:39 +1000462 port = <0x0>; /* port number */
463 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
464 0x0000000c 0x08010000 0x00001000>; /* Registers */
465 dcr-reg = <0x100 0x020>;
466 sdr-base = <0x300>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100467
468 /* Outbound ranges, one memory and one IO,
469 * later cannot be changed
470 */
David Gibson71f34972008-05-15 16:46:39 +1000471 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
Benjamin Herrenschmidt84d727a2008-10-09 16:58:19 +0000472 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
David Gibson71f34972008-05-15 16:46:39 +1000473 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100474
475 /* Inbound 2GB range starting at 0 */
David Gibson71f34972008-05-15 16:46:39 +1000476 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100477
478 /* This drives busses 40 to 0x7f */
David Gibson71f34972008-05-15 16:46:39 +1000479 bus-range = <0x40 0x7f>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100480
481 /* Legacy interrupts (note the weird polarity, the bridge seems
482 * to invert PCIe legacy interrupts).
483 * We are de-swizzling here because the numbers are actually for
484 * port of the root complex virtual P2P bridge. But I want
485 * to avoid putting a node for it in the tree, so the numbers
486 * below are basically de-swizzled numbers.
487 * The real slot is on idsel 0, so the swizzling is 1:1
488 */
David Gibson71f34972008-05-15 16:46:39 +1000489 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100490 interrupt-map = <
David Gibson71f34972008-05-15 16:46:39 +1000491 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
492 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
493 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
494 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100495 };
496
497 PCIE1: pciex@d20000000 {
498 device_type = "pci";
499 #interrupt-cells = <1>;
500 #size-cells = <2>;
501 #address-cells = <3>;
502 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
503 primary;
David Gibson71f34972008-05-15 16:46:39 +1000504 port = <0x1>; /* port number */
505 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
506 0x0000000c 0x08011000 0x00001000>; /* Registers */
507 dcr-reg = <0x120 0x020>;
508 sdr-base = <0x340>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100509
510 /* Outbound ranges, one memory and one IO,
511 * later cannot be changed
512 */
David Gibson71f34972008-05-15 16:46:39 +1000513 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
Benjamin Herrenschmidt84d727a2008-10-09 16:58:19 +0000514 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
David Gibson71f34972008-05-15 16:46:39 +1000515 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100516
517 /* Inbound 2GB range starting at 0 */
David Gibson71f34972008-05-15 16:46:39 +1000518 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100519
520 /* This drives busses 80 to 0xbf */
David Gibson71f34972008-05-15 16:46:39 +1000521 bus-range = <0x80 0xbf>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100522
523 /* Legacy interrupts (note the weird polarity, the bridge seems
524 * to invert PCIe legacy interrupts).
525 * We are de-swizzling here because the numbers are actually for
526 * port of the root complex virtual P2P bridge. But I want
527 * to avoid putting a node for it in the tree, so the numbers
528 * below are basically de-swizzled numbers.
529 * The real slot is on idsel 0, so the swizzling is 1:1
530 */
David Gibson71f34972008-05-15 16:46:39 +1000531 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100532 interrupt-map = <
David Gibson71f34972008-05-15 16:46:39 +1000533 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
534 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
535 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
536 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
Stefan Roese8bc4a512008-03-01 03:25:29 +1100537 };
Rupjyoti Sarmah3fb79332011-03-29 23:10:24 +0000538
539 MSI: ppc4xx-msi@C10000000 {
540 compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
541 reg = < 0xC 0x10000000 0x100>;
542 sdr-base = <0x36C>;
543 msi-data = <0x00000000>;
544 msi-mask = <0x44440000>;
545 interrupt-count = <3>;
546 interrupts = <0 1 2 3>;
547 interrupt-parent = <&UIC3>;
548 #interrupt-cells = <1>;
549 #address-cells = <0>;
550 #size-cells = <0>;
551 interrupt-map = <0 &UIC3 0x18 1
552 1 &UIC3 0x19 1
553 2 &UIC3 0x1A 1
554 3 &UIC3 0x1B 1>;
555 };
Stefan Roese8bc4a512008-03-01 03:25:29 +1100556 };
557};