Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 1 | /* |
Bjorn Helgaas | 96291d5 | 2017-09-01 16:35:50 -0500 | [diff] [blame] | 2 | * Synopsys DesignWare PCIe host controller driver |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. |
| 5 | * http://www.samsung.com |
| 6 | * |
| 7 | * Author: Jingoo Han <jg1.han@samsung.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/irqdomain.h> |
| 15 | #include <linux/of_address.h> |
| 16 | #include <linux/of_pci.h> |
| 17 | #include <linux/pci_regs.h> |
| 18 | #include <linux/platform_device.h> |
| 19 | |
| 20 | #include "pcie-designware.h" |
| 21 | |
| 22 | static struct pci_ops dw_pcie_ops; |
| 23 | |
| 24 | static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, |
| 25 | u32 *val) |
| 26 | { |
| 27 | struct dw_pcie *pci; |
| 28 | |
| 29 | if (pp->ops->rd_own_conf) |
| 30 | return pp->ops->rd_own_conf(pp, where, size, val); |
| 31 | |
| 32 | pci = to_dw_pcie_from_pp(pp); |
| 33 | return dw_pcie_read(pci->dbi_base + where, size, val); |
| 34 | } |
| 35 | |
| 36 | static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, |
| 37 | u32 val) |
| 38 | { |
| 39 | struct dw_pcie *pci; |
| 40 | |
| 41 | if (pp->ops->wr_own_conf) |
| 42 | return pp->ops->wr_own_conf(pp, where, size, val); |
| 43 | |
| 44 | pci = to_dw_pcie_from_pp(pp); |
| 45 | return dw_pcie_write(pci->dbi_base + where, size, val); |
| 46 | } |
| 47 | |
Marc Zyngier | 413cb66 | 2018-11-13 22:57:34 +0000 | [diff] [blame] | 48 | static void dwc_irq_ack(struct irq_data *d) |
| 49 | { |
| 50 | struct msi_desc *msi = irq_data_get_msi_desc(d); |
| 51 | struct pcie_port *pp = msi_desc_to_pci_sysdata(msi); |
| 52 | int pos = d->hwirq % 32; |
| 53 | int i = d->hwirq / 32; |
| 54 | |
| 55 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, BIT(pos)); |
| 56 | } |
| 57 | |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 58 | static struct irq_chip dw_msi_irq_chip = { |
| 59 | .name = "PCI-MSI", |
Marc Zyngier | 413cb66 | 2018-11-13 22:57:34 +0000 | [diff] [blame] | 60 | .irq_ack = dwc_irq_ack, |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 61 | .irq_enable = pci_msi_unmask_irq, |
| 62 | .irq_disable = pci_msi_mask_irq, |
| 63 | .irq_mask = pci_msi_mask_irq, |
| 64 | .irq_unmask = pci_msi_unmask_irq, |
| 65 | }; |
| 66 | |
| 67 | /* MSI int handler */ |
| 68 | irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) |
| 69 | { |
Dan Carpenter | 1b497e6 | 2017-03-16 14:34:51 -0500 | [diff] [blame] | 70 | u32 val; |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 71 | int i, pos, irq; |
| 72 | irqreturn_t ret = IRQ_NONE; |
| 73 | |
| 74 | for (i = 0; i < MAX_MSI_CTRLS; i++) { |
| 75 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, |
Dan Carpenter | 1b497e6 | 2017-03-16 14:34:51 -0500 | [diff] [blame] | 76 | &val); |
Bjorn Helgaas | dbe4a09 | 2017-03-16 14:34:59 -0500 | [diff] [blame] | 77 | if (!val) |
| 78 | continue; |
| 79 | |
| 80 | ret = IRQ_HANDLED; |
| 81 | pos = 0; |
Dan Carpenter | 1b497e6 | 2017-03-16 14:34:51 -0500 | [diff] [blame] | 82 | while ((pos = find_next_bit((unsigned long *) &val, 32, |
| 83 | pos)) != 32) { |
Bjorn Helgaas | dbe4a09 | 2017-03-16 14:34:59 -0500 | [diff] [blame] | 84 | irq = irq_find_mapping(pp->irq_domain, i * 32 + pos); |
Faiz Abbas | 8c93409 | 2017-08-10 16:54:55 +0530 | [diff] [blame] | 85 | generic_handle_irq(irq); |
Bjorn Helgaas | dbe4a09 | 2017-03-16 14:34:59 -0500 | [diff] [blame] | 86 | pos++; |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 87 | } |
| 88 | } |
| 89 | |
| 90 | return ret; |
| 91 | } |
| 92 | |
| 93 | void dw_pcie_msi_init(struct pcie_port *pp) |
| 94 | { |
| 95 | u64 msi_target; |
| 96 | |
| 97 | pp->msi_data = __get_free_pages(GFP_KERNEL, 0); |
| 98 | msi_target = virt_to_phys((void *)pp->msi_data); |
| 99 | |
| 100 | /* program the msi_data */ |
| 101 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, |
| 102 | (u32)(msi_target & 0xffffffff)); |
| 103 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, |
| 104 | (u32)(msi_target >> 32 & 0xffffffff)); |
| 105 | } |
| 106 | |
| 107 | static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) |
| 108 | { |
| 109 | unsigned int res, bit, val; |
| 110 | |
| 111 | res = (irq / 32) * 12; |
| 112 | bit = irq % 32; |
| 113 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); |
| 114 | val &= ~(1 << bit); |
| 115 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); |
| 116 | } |
| 117 | |
| 118 | static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, |
| 119 | unsigned int nvec, unsigned int pos) |
| 120 | { |
| 121 | unsigned int i; |
| 122 | |
| 123 | for (i = 0; i < nvec; i++) { |
| 124 | irq_set_msi_desc_off(irq_base, i, NULL); |
| 125 | /* Disable corresponding interrupt on MSI controller */ |
| 126 | if (pp->ops->msi_clear_irq) |
| 127 | pp->ops->msi_clear_irq(pp, pos + i); |
| 128 | else |
| 129 | dw_pcie_msi_clear_irq(pp, pos + i); |
| 130 | } |
| 131 | |
| 132 | bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec)); |
| 133 | } |
| 134 | |
| 135 | static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) |
| 136 | { |
| 137 | unsigned int res, bit, val; |
| 138 | |
| 139 | res = (irq / 32) * 12; |
| 140 | bit = irq % 32; |
| 141 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); |
| 142 | val |= 1 << bit; |
| 143 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); |
| 144 | } |
| 145 | |
| 146 | static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) |
| 147 | { |
| 148 | int irq, pos0, i; |
| 149 | struct pcie_port *pp; |
| 150 | |
| 151 | pp = (struct pcie_port *)msi_desc_to_pci_sysdata(desc); |
| 152 | pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS, |
| 153 | order_base_2(no_irqs)); |
| 154 | if (pos0 < 0) |
| 155 | goto no_valid_irq; |
| 156 | |
| 157 | irq = irq_find_mapping(pp->irq_domain, pos0); |
| 158 | if (!irq) |
| 159 | goto no_valid_irq; |
| 160 | |
| 161 | /* |
| 162 | * irq_create_mapping (called from dw_pcie_host_init) pre-allocates |
| 163 | * descs so there is no need to allocate descs here. We can therefore |
| 164 | * assume that if irq_find_mapping above returns non-zero, then the |
| 165 | * descs are also successfully allocated. |
| 166 | */ |
| 167 | |
| 168 | for (i = 0; i < no_irqs; i++) { |
| 169 | if (irq_set_msi_desc_off(irq, i, desc) != 0) { |
| 170 | clear_irq_range(pp, irq, i, pos0); |
| 171 | goto no_valid_irq; |
| 172 | } |
| 173 | /*Enable corresponding interrupt in MSI interrupt controller */ |
| 174 | if (pp->ops->msi_set_irq) |
| 175 | pp->ops->msi_set_irq(pp, pos0 + i); |
| 176 | else |
| 177 | dw_pcie_msi_set_irq(pp, pos0 + i); |
| 178 | } |
| 179 | |
| 180 | *pos = pos0; |
| 181 | desc->nvec_used = no_irqs; |
| 182 | desc->msi_attrib.multiple = order_base_2(no_irqs); |
| 183 | |
| 184 | return irq; |
| 185 | |
| 186 | no_valid_irq: |
| 187 | *pos = pos0; |
| 188 | return -ENOSPC; |
| 189 | } |
| 190 | |
| 191 | static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos) |
| 192 | { |
| 193 | struct msi_msg msg; |
| 194 | u64 msi_target; |
| 195 | |
| 196 | if (pp->ops->get_msi_addr) |
| 197 | msi_target = pp->ops->get_msi_addr(pp); |
| 198 | else |
| 199 | msi_target = virt_to_phys((void *)pp->msi_data); |
| 200 | |
| 201 | msg.address_lo = (u32)(msi_target & 0xffffffff); |
| 202 | msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff); |
| 203 | |
| 204 | if (pp->ops->get_msi_data) |
| 205 | msg.data = pp->ops->get_msi_data(pp, pos); |
| 206 | else |
| 207 | msg.data = pos; |
| 208 | |
| 209 | pci_write_msi_msg(irq, &msg); |
| 210 | } |
| 211 | |
| 212 | static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, |
| 213 | struct msi_desc *desc) |
| 214 | { |
| 215 | int irq, pos; |
| 216 | struct pcie_port *pp = pdev->bus->sysdata; |
| 217 | |
| 218 | if (desc->msi_attrib.is_msix) |
| 219 | return -EINVAL; |
| 220 | |
| 221 | irq = assign_irq(1, desc, &pos); |
| 222 | if (irq < 0) |
| 223 | return irq; |
| 224 | |
| 225 | dw_msi_setup_msg(pp, irq, pos); |
| 226 | |
| 227 | return 0; |
| 228 | } |
| 229 | |
| 230 | static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev, |
| 231 | int nvec, int type) |
| 232 | { |
| 233 | #ifdef CONFIG_PCI_MSI |
| 234 | int irq, pos; |
| 235 | struct msi_desc *desc; |
| 236 | struct pcie_port *pp = pdev->bus->sysdata; |
| 237 | |
| 238 | /* MSI-X interrupts are not supported */ |
| 239 | if (type == PCI_CAP_ID_MSIX) |
| 240 | return -EINVAL; |
| 241 | |
| 242 | WARN_ON(!list_is_singular(&pdev->dev.msi_list)); |
| 243 | desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list); |
| 244 | |
| 245 | irq = assign_irq(nvec, desc, &pos); |
| 246 | if (irq < 0) |
| 247 | return irq; |
| 248 | |
| 249 | dw_msi_setup_msg(pp, irq, pos); |
| 250 | |
| 251 | return 0; |
| 252 | #else |
| 253 | return -EINVAL; |
| 254 | #endif |
| 255 | } |
| 256 | |
| 257 | static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) |
| 258 | { |
| 259 | struct irq_data *data = irq_get_irq_data(irq); |
| 260 | struct msi_desc *msi = irq_data_get_msi_desc(data); |
| 261 | struct pcie_port *pp = (struct pcie_port *)msi_desc_to_pci_sysdata(msi); |
| 262 | |
| 263 | clear_irq_range(pp, irq, 1, data->hwirq); |
| 264 | } |
| 265 | |
| 266 | static struct msi_controller dw_pcie_msi_chip = { |
| 267 | .setup_irq = dw_msi_setup_irq, |
| 268 | .setup_irqs = dw_msi_setup_irqs, |
| 269 | .teardown_irq = dw_msi_teardown_irq, |
| 270 | }; |
| 271 | |
| 272 | static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, |
| 273 | irq_hw_number_t hwirq) |
| 274 | { |
Marc Zyngier | 413cb66 | 2018-11-13 22:57:34 +0000 | [diff] [blame] | 275 | irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_edge_irq); |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 276 | irq_set_chip_data(irq, domain->host_data); |
| 277 | |
| 278 | return 0; |
| 279 | } |
| 280 | |
| 281 | static const struct irq_domain_ops msi_domain_ops = { |
| 282 | .map = dw_pcie_msi_map, |
| 283 | }; |
| 284 | |
| 285 | int dw_pcie_host_init(struct pcie_port *pp) |
| 286 | { |
| 287 | struct dw_pcie *pci = to_dw_pcie_from_pp(pp); |
| 288 | struct device *dev = pci->dev; |
| 289 | struct device_node *np = dev->of_node; |
| 290 | struct platform_device *pdev = to_platform_device(dev); |
| 291 | struct pci_bus *bus, *child; |
Lorenzo Pieralisi | 295aeb9 | 2017-06-28 15:13:56 -0500 | [diff] [blame] | 292 | struct pci_host_bridge *bridge; |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 293 | struct resource *cfg_res; |
| 294 | int i, ret; |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 295 | struct resource_entry *win, *tmp; |
| 296 | |
| 297 | cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); |
| 298 | if (cfg_res) { |
| 299 | pp->cfg0_size = resource_size(cfg_res) / 2; |
| 300 | pp->cfg1_size = resource_size(cfg_res) / 2; |
| 301 | pp->cfg0_base = cfg_res->start; |
| 302 | pp->cfg1_base = cfg_res->start + pp->cfg0_size; |
| 303 | } else if (!pp->va_cfg0_base) { |
| 304 | dev_err(dev, "missing *config* reg space\n"); |
| 305 | } |
| 306 | |
Lorenzo Pieralisi | 295aeb9 | 2017-06-28 15:13:56 -0500 | [diff] [blame] | 307 | bridge = pci_alloc_host_bridge(0); |
| 308 | if (!bridge) |
| 309 | return -ENOMEM; |
| 310 | |
| 311 | ret = of_pci_get_host_bridge_resources(np, 0, 0xff, |
| 312 | &bridge->windows, &pp->io_base); |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 313 | if (ret) |
| 314 | return ret; |
| 315 | |
Lorenzo Pieralisi | 295aeb9 | 2017-06-28 15:13:56 -0500 | [diff] [blame] | 316 | ret = devm_request_pci_bus_resources(dev, &bridge->windows); |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 317 | if (ret) |
| 318 | goto error; |
| 319 | |
| 320 | /* Get the I/O and memory ranges from DT */ |
Lorenzo Pieralisi | 295aeb9 | 2017-06-28 15:13:56 -0500 | [diff] [blame] | 321 | resource_list_for_each_entry_safe(win, tmp, &bridge->windows) { |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 322 | switch (resource_type(win->res)) { |
| 323 | case IORESOURCE_IO: |
| 324 | ret = pci_remap_iospace(win->res, pp->io_base); |
| 325 | if (ret) { |
| 326 | dev_warn(dev, "error %d: failed to map resource %pR\n", |
| 327 | ret, win->res); |
| 328 | resource_list_destroy_entry(win); |
| 329 | } else { |
| 330 | pp->io = win->res; |
| 331 | pp->io->name = "I/O"; |
| 332 | pp->io_size = resource_size(pp->io); |
| 333 | pp->io_bus_addr = pp->io->start - win->offset; |
| 334 | } |
| 335 | break; |
| 336 | case IORESOURCE_MEM: |
| 337 | pp->mem = win->res; |
| 338 | pp->mem->name = "MEM"; |
| 339 | pp->mem_size = resource_size(pp->mem); |
| 340 | pp->mem_bus_addr = pp->mem->start - win->offset; |
| 341 | break; |
| 342 | case 0: |
| 343 | pp->cfg = win->res; |
| 344 | pp->cfg0_size = resource_size(pp->cfg) / 2; |
| 345 | pp->cfg1_size = resource_size(pp->cfg) / 2; |
| 346 | pp->cfg0_base = pp->cfg->start; |
| 347 | pp->cfg1_base = pp->cfg->start + pp->cfg0_size; |
| 348 | break; |
| 349 | case IORESOURCE_BUS: |
| 350 | pp->busn = win->res; |
| 351 | break; |
| 352 | } |
| 353 | } |
| 354 | |
| 355 | if (!pci->dbi_base) { |
Lorenzo Pieralisi | cc7b0d4 | 2017-04-19 17:49:03 +0100 | [diff] [blame] | 356 | pci->dbi_base = devm_pci_remap_cfgspace(dev, |
| 357 | pp->cfg->start, |
| 358 | resource_size(pp->cfg)); |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 359 | if (!pci->dbi_base) { |
| 360 | dev_err(dev, "error with ioremap\n"); |
| 361 | ret = -ENOMEM; |
| 362 | goto error; |
| 363 | } |
| 364 | } |
| 365 | |
| 366 | pp->mem_base = pp->mem->start; |
| 367 | |
| 368 | if (!pp->va_cfg0_base) { |
Lorenzo Pieralisi | cc7b0d4 | 2017-04-19 17:49:03 +0100 | [diff] [blame] | 369 | pp->va_cfg0_base = devm_pci_remap_cfgspace(dev, |
| 370 | pp->cfg0_base, pp->cfg0_size); |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 371 | if (!pp->va_cfg0_base) { |
| 372 | dev_err(dev, "error with ioremap in function\n"); |
| 373 | ret = -ENOMEM; |
| 374 | goto error; |
| 375 | } |
| 376 | } |
| 377 | |
| 378 | if (!pp->va_cfg1_base) { |
Lorenzo Pieralisi | cc7b0d4 | 2017-04-19 17:49:03 +0100 | [diff] [blame] | 379 | pp->va_cfg1_base = devm_pci_remap_cfgspace(dev, |
| 380 | pp->cfg1_base, |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 381 | pp->cfg1_size); |
| 382 | if (!pp->va_cfg1_base) { |
| 383 | dev_err(dev, "error with ioremap\n"); |
| 384 | ret = -ENOMEM; |
| 385 | goto error; |
| 386 | } |
| 387 | } |
| 388 | |
| 389 | ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport); |
| 390 | if (ret) |
| 391 | pci->num_viewport = 2; |
| 392 | |
| 393 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
| 394 | if (!pp->ops->msi_host_init) { |
| 395 | pp->irq_domain = irq_domain_add_linear(dev->of_node, |
| 396 | MAX_MSI_IRQS, &msi_domain_ops, |
| 397 | &dw_pcie_msi_chip); |
| 398 | if (!pp->irq_domain) { |
| 399 | dev_err(dev, "irq domain init failed\n"); |
| 400 | ret = -ENXIO; |
| 401 | goto error; |
| 402 | } |
| 403 | |
| 404 | for (i = 0; i < MAX_MSI_IRQS; i++) |
| 405 | irq_create_mapping(pp->irq_domain, i); |
| 406 | } else { |
| 407 | ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip); |
| 408 | if (ret < 0) |
| 409 | goto error; |
| 410 | } |
| 411 | } |
| 412 | |
Bjorn Andersson | 4a30176 | 2017-07-15 23:39:45 -0700 | [diff] [blame] | 413 | if (pp->ops->host_init) { |
| 414 | ret = pp->ops->host_init(pp); |
| 415 | if (ret) |
| 416 | goto error; |
| 417 | } |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 418 | |
| 419 | pp->root_bus_nr = pp->busn->start; |
Lorenzo Pieralisi | 295aeb9 | 2017-06-28 15:13:56 -0500 | [diff] [blame] | 420 | |
| 421 | bridge->dev.parent = dev; |
| 422 | bridge->sysdata = pp; |
| 423 | bridge->busnr = pp->root_bus_nr; |
| 424 | bridge->ops = &dw_pcie_ops; |
Lorenzo Pieralisi | 60eca19 | 2017-06-28 15:14:07 -0500 | [diff] [blame] | 425 | bridge->map_irq = of_irq_parse_and_map_pci; |
| 426 | bridge->swizzle_irq = pci_common_swizzle; |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 427 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
Lorenzo Pieralisi | 295aeb9 | 2017-06-28 15:13:56 -0500 | [diff] [blame] | 428 | bridge->msi = &dw_pcie_msi_chip; |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 429 | dw_pcie_msi_chip.dev = dev; |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 430 | } |
| 431 | |
Lorenzo Pieralisi | 295aeb9 | 2017-06-28 15:13:56 -0500 | [diff] [blame] | 432 | ret = pci_scan_root_bus_bridge(bridge); |
| 433 | if (ret) |
| 434 | goto error; |
| 435 | |
| 436 | bus = bridge->bus; |
| 437 | |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 438 | if (pp->ops->scan_bus) |
| 439 | pp->ops->scan_bus(pp); |
| 440 | |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 441 | pci_bus_size_bridges(bus); |
| 442 | pci_bus_assign_resources(bus); |
| 443 | |
| 444 | list_for_each_entry(child, &bus->children, node) |
| 445 | pcie_bus_configure_settings(child); |
| 446 | |
| 447 | pci_bus_add_devices(bus); |
| 448 | return 0; |
| 449 | |
| 450 | error: |
Lorenzo Pieralisi | 295aeb9 | 2017-06-28 15:13:56 -0500 | [diff] [blame] | 451 | pci_free_host_bridge(bridge); |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 452 | return ret; |
| 453 | } |
| 454 | |
| 455 | static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
| 456 | u32 devfn, int where, int size, u32 *val) |
| 457 | { |
| 458 | int ret, type; |
| 459 | u32 busdev, cfg_size; |
| 460 | u64 cpu_addr; |
| 461 | void __iomem *va_cfg_base; |
| 462 | struct dw_pcie *pci = to_dw_pcie_from_pp(pp); |
| 463 | |
| 464 | if (pp->ops->rd_other_conf) |
| 465 | return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val); |
| 466 | |
| 467 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | |
| 468 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); |
| 469 | |
| 470 | if (bus->parent->number == pp->root_bus_nr) { |
| 471 | type = PCIE_ATU_TYPE_CFG0; |
| 472 | cpu_addr = pp->cfg0_base; |
| 473 | cfg_size = pp->cfg0_size; |
| 474 | va_cfg_base = pp->va_cfg0_base; |
| 475 | } else { |
| 476 | type = PCIE_ATU_TYPE_CFG1; |
| 477 | cpu_addr = pp->cfg1_base; |
| 478 | cfg_size = pp->cfg1_size; |
| 479 | va_cfg_base = pp->va_cfg1_base; |
| 480 | } |
| 481 | |
| 482 | dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, |
| 483 | type, cpu_addr, |
| 484 | busdev, cfg_size); |
| 485 | ret = dw_pcie_read(va_cfg_base + where, size, val); |
| 486 | if (pci->num_viewport <= 2) |
| 487 | dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, |
| 488 | PCIE_ATU_TYPE_IO, pp->io_base, |
| 489 | pp->io_bus_addr, pp->io_size); |
| 490 | |
| 491 | return ret; |
| 492 | } |
| 493 | |
| 494 | static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
| 495 | u32 devfn, int where, int size, u32 val) |
| 496 | { |
| 497 | int ret, type; |
| 498 | u32 busdev, cfg_size; |
| 499 | u64 cpu_addr; |
| 500 | void __iomem *va_cfg_base; |
| 501 | struct dw_pcie *pci = to_dw_pcie_from_pp(pp); |
| 502 | |
| 503 | if (pp->ops->wr_other_conf) |
| 504 | return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val); |
| 505 | |
| 506 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | |
| 507 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); |
| 508 | |
| 509 | if (bus->parent->number == pp->root_bus_nr) { |
| 510 | type = PCIE_ATU_TYPE_CFG0; |
| 511 | cpu_addr = pp->cfg0_base; |
| 512 | cfg_size = pp->cfg0_size; |
| 513 | va_cfg_base = pp->va_cfg0_base; |
| 514 | } else { |
| 515 | type = PCIE_ATU_TYPE_CFG1; |
| 516 | cpu_addr = pp->cfg1_base; |
| 517 | cfg_size = pp->cfg1_size; |
| 518 | va_cfg_base = pp->va_cfg1_base; |
| 519 | } |
| 520 | |
| 521 | dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, |
| 522 | type, cpu_addr, |
| 523 | busdev, cfg_size); |
| 524 | ret = dw_pcie_write(va_cfg_base + where, size, val); |
| 525 | if (pci->num_viewport <= 2) |
| 526 | dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, |
| 527 | PCIE_ATU_TYPE_IO, pp->io_base, |
| 528 | pp->io_bus_addr, pp->io_size); |
| 529 | |
| 530 | return ret; |
| 531 | } |
| 532 | |
| 533 | static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus, |
| 534 | int dev) |
| 535 | { |
| 536 | struct dw_pcie *pci = to_dw_pcie_from_pp(pp); |
| 537 | |
| 538 | /* If there is no link, then there is no device */ |
| 539 | if (bus->number != pp->root_bus_nr) { |
| 540 | if (!dw_pcie_link_up(pci)) |
| 541 | return 0; |
| 542 | } |
| 543 | |
| 544 | /* access only one slot on each root port */ |
| 545 | if (bus->number == pp->root_bus_nr && dev > 0) |
| 546 | return 0; |
| 547 | |
| 548 | return 1; |
| 549 | } |
| 550 | |
| 551 | static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
| 552 | int size, u32 *val) |
| 553 | { |
| 554 | struct pcie_port *pp = bus->sysdata; |
| 555 | |
| 556 | if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) { |
| 557 | *val = 0xffffffff; |
| 558 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 559 | } |
| 560 | |
| 561 | if (bus->number == pp->root_bus_nr) |
| 562 | return dw_pcie_rd_own_conf(pp, where, size, val); |
| 563 | |
| 564 | return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val); |
| 565 | } |
| 566 | |
| 567 | static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
| 568 | int where, int size, u32 val) |
| 569 | { |
| 570 | struct pcie_port *pp = bus->sysdata; |
| 571 | |
| 572 | if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) |
| 573 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 574 | |
| 575 | if (bus->number == pp->root_bus_nr) |
| 576 | return dw_pcie_wr_own_conf(pp, where, size, val); |
| 577 | |
| 578 | return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val); |
| 579 | } |
| 580 | |
| 581 | static struct pci_ops dw_pcie_ops = { |
| 582 | .read = dw_pcie_rd_conf, |
| 583 | .write = dw_pcie_wr_conf, |
| 584 | }; |
| 585 | |
| 586 | static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) |
| 587 | { |
| 588 | u32 val; |
| 589 | |
| 590 | val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); |
| 591 | if (val == 0xffffffff) |
| 592 | return 1; |
| 593 | |
| 594 | return 0; |
| 595 | } |
| 596 | |
| 597 | void dw_pcie_setup_rc(struct pcie_port *pp) |
| 598 | { |
| 599 | u32 val; |
| 600 | struct dw_pcie *pci = to_dw_pcie_from_pp(pp); |
| 601 | |
| 602 | dw_pcie_setup(pci); |
| 603 | |
| 604 | /* setup RC BARs */ |
| 605 | dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004); |
| 606 | dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); |
| 607 | |
| 608 | /* setup interrupt pins */ |
Hou Zhiqiang | d91dfe5 | 2017-08-28 18:53:00 +0800 | [diff] [blame] | 609 | dw_pcie_dbi_ro_wr_en(pci); |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 610 | val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); |
| 611 | val &= 0xffff00ff; |
| 612 | val |= 0x00000100; |
| 613 | dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); |
Hou Zhiqiang | d91dfe5 | 2017-08-28 18:53:00 +0800 | [diff] [blame] | 614 | dw_pcie_dbi_ro_wr_dis(pci); |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 615 | |
| 616 | /* setup bus numbers */ |
| 617 | val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); |
| 618 | val &= 0xff000000; |
Koen Vandeputte | 91e019a | 2018-03-07 10:46:39 -0600 | [diff] [blame] | 619 | val |= 0x00ff0100; |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 620 | dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); |
| 621 | |
| 622 | /* setup command register */ |
| 623 | val = dw_pcie_readl_dbi(pci, PCI_COMMAND); |
| 624 | val &= 0xffff0000; |
| 625 | val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
| 626 | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; |
| 627 | dw_pcie_writel_dbi(pci, PCI_COMMAND, val); |
| 628 | |
| 629 | /* |
| 630 | * If the platform provides ->rd_other_conf, it means the platform |
| 631 | * uses its own address translation component rather than ATU, so |
| 632 | * we should not program the ATU here. |
| 633 | */ |
| 634 | if (!pp->ops->rd_other_conf) { |
| 635 | /* get iATU unroll support */ |
| 636 | pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); |
| 637 | dev_dbg(pci->dev, "iATU unroll: %s\n", |
| 638 | pci->iatu_unroll_enabled ? "enabled" : "disabled"); |
| 639 | |
| 640 | dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, |
| 641 | PCIE_ATU_TYPE_MEM, pp->mem_base, |
| 642 | pp->mem_bus_addr, pp->mem_size); |
| 643 | if (pci->num_viewport > 2) |
| 644 | dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2, |
| 645 | PCIE_ATU_TYPE_IO, pp->io_base, |
| 646 | pp->io_bus_addr, pp->io_size); |
| 647 | } |
| 648 | |
| 649 | dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); |
| 650 | |
Hou Zhiqiang | d91dfe5 | 2017-08-28 18:53:00 +0800 | [diff] [blame] | 651 | /* Enable write permission for the DBI read-only register */ |
| 652 | dw_pcie_dbi_ro_wr_en(pci); |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 653 | /* program correct class for RC */ |
| 654 | dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); |
Hou Zhiqiang | d91dfe5 | 2017-08-28 18:53:00 +0800 | [diff] [blame] | 655 | /* Better disable write permission right after the update */ |
| 656 | dw_pcie_dbi_ro_wr_dis(pci); |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 657 | |
| 658 | dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); |
| 659 | val |= PORT_LOGIC_SPEED_CHANGE; |
| 660 | dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); |
| 661 | } |