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Wolfram Sangbb2fd8a2010-04-29 10:03:17 +02001/*
2 * Watchdog driver for IMX2 and later processors
3 *
4 * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
Anson Huang1a9c5ef2014-01-13 19:58:34 +08005 * Copyright (C) 2014 Freescale Semiconductor, Inc.
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +02006 *
7 * some parts adapted by similar drivers from Darius Augulis and Vladimir
8 * Zapolskiy, additional improvements by Wim Van Sebroeck.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
15 *
16 * MX1: MX2+:
17 * ---- -----
18 * Registers: 32-bit 16-bit
19 * Stopable timer: Yes No
20 * Need to enable clk: No Yes
21 * Halt on suspend: Manual Can be automatic
22 */
23
Xiubo Li30cb0422014-04-04 09:33:24 +080024#include <linux/clk.h>
Jingchang Lu334a9d82014-09-12 15:24:36 +080025#include <linux/delay.h>
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +020026#include <linux/init.h>
Vladimir Zapolskiy39487f62016-10-07 15:41:39 +030027#include <linux/interrupt.h>
Xiubo Li30cb0422014-04-04 09:33:24 +080028#include <linux/io.h>
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +020029#include <linux/kernel.h>
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +020030#include <linux/module.h>
31#include <linux/moduleparam.h>
Xiubo Lif728f4b2014-06-03 10:45:14 +080032#include <linux/of_address.h>
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +020033#include <linux/platform_device.h>
Xiubo Lia7977002014-04-04 09:33:25 +080034#include <linux/regmap.h>
Xiubo Li30cb0422014-04-04 09:33:24 +080035#include <linux/watchdog.h>
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +020036
37#define DRIVER_NAME "imx2-wdt"
38
39#define IMX2_WDT_WCR 0x00 /* Control Register */
40#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
Vladimir Zapolskiy68d4cb82016-08-31 14:52:49 +030041#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
42#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
43#define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
44#define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */
45#define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +020046
47#define IMX2_WDT_WSR 0x02 /* Service Register */
48#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
49#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
50
Oskar Schirmer474ef122012-02-16 12:17:45 +000051#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
Vladimir Zapolskiy68d4cb82016-08-31 14:52:49 +030052#define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */
Oskar Schirmer474ef122012-02-16 12:17:45 +000053
Vladimir Zapolskiy39487f62016-10-07 15:41:39 +030054#define IMX2_WDT_WICR 0x06 /* Interrupt Control Register */
55#define IMX2_WDT_WICR_WIE BIT(15) /* -> Interrupt Enable */
56#define IMX2_WDT_WICR_WTIS BIT(14) /* -> Interrupt Status */
57#define IMX2_WDT_WICR_WICT 0xFF /* -> Interrupt Count Timeout */
58
Markus Pargmann5fe65ce2014-09-08 09:14:07 +020059#define IMX2_WDT_WMCR 0x08 /* Misc Register */
60
Rasmus Villemoes2890b712019-08-12 15:13:56 +020061#define IMX2_WDT_MAX_TIME 128U
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +020062#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
63
64#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
65
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +020066struct imx2_wdt_device {
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +020067 struct clk *clk;
Xiubo Lia7977002014-04-04 09:33:25 +080068 struct regmap *regmap;
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +020069 struct watchdog_device wdog;
Tim Harveybc677ff42016-04-01 08:16:43 -070070 bool ext_reset;
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +020071};
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +020072
Wim Van Sebroeck86a1e182012-03-05 16:51:11 +010073static bool nowayout = WATCHDOG_NOWAYOUT;
74module_param(nowayout, bool, 0);
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +020075MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
76 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
77
78
79static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
80module_param(timeout, uint, 0);
81MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
82 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
83
84static const struct watchdog_info imx2_wdt_info = {
85 .identity = "imx2+ watchdog",
86 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
87};
88
Vladimir Zapolskiy39487f62016-10-07 15:41:39 +030089static const struct watchdog_info imx2_wdt_pretimeout_info = {
90 .identity = "imx2+ watchdog",
91 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
92 WDIOF_PRETIMEOUT,
93};
94
Guenter Roeck4d8b2292016-02-26 17:32:49 -080095static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
96 void *data)
Jingchang Lu334a9d82014-09-12 15:24:36 +080097{
Damien Riegel2d9d24752015-11-16 12:28:04 -050098 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
Jingchang Lu334a9d82014-09-12 15:24:36 +080099 unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
Damien Riegel2d9d24752015-11-16 12:28:04 -0500100
Tim Harveybc677ff42016-04-01 08:16:43 -0700101 /* Use internal reset or external - not both */
102 if (wdev->ext_reset)
103 wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
104 else
105 wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
106
Jingchang Lu334a9d82014-09-12 15:24:36 +0800107 /* Assert SRS signal */
Fabio Estevam9493c0d2015-10-02 00:25:28 -0300108 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
Jingchang Lu334a9d82014-09-12 15:24:36 +0800109 /*
110 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
111 * written twice), we add another two writes to ensure there must be at
112 * least two writes happen in the same one 32kHz clock period. We save
113 * the target check here, since the writes shouldn't be a huge burden
114 * for other platforms.
115 */
Fabio Estevam9493c0d2015-10-02 00:25:28 -0300116 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
117 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
Jingchang Lu334a9d82014-09-12 15:24:36 +0800118
119 /* wait for reset to assert... */
120 mdelay(500);
121
Damien Riegel2d9d24752015-11-16 12:28:04 -0500122 return 0;
Jingchang Lu334a9d82014-09-12 15:24:36 +0800123}
124
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200125static inline void imx2_wdt_setup(struct watchdog_device *wdog)
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200126{
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200127 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
Xiubo Lia7977002014-04-04 09:33:25 +0800128 u32 val;
129
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200130 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200131
Anson Huang1a9c5ef2014-01-13 19:58:34 +0800132 /* Suspend timer in low power mode, write once-only */
133 val |= IMX2_WDT_WCR_WDZST;
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200134 /* Strip the old watchdog Time-Out value */
135 val &= ~IMX2_WDT_WCR_WT;
Tim Harveybc677ff42016-04-01 08:16:43 -0700136 /* Generate internal chip-level reset if WDOG times out */
137 if (!wdev->ext_reset)
138 val &= ~IMX2_WDT_WCR_WRE;
139 /* Or if external-reset assert WDOG_B reset only on time-out */
140 else
141 val |= IMX2_WDT_WCR_WRE;
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200142 /* Keep Watchdog Disabled */
143 val &= ~IMX2_WDT_WCR_WDE;
144 /* Set the watchdog's Time-Out value */
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200145 val |= WDOG_SEC_TO_COUNT(wdog->timeout);
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200146
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200147 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200148
149 /* enable the watchdog */
150 val |= IMX2_WDT_WCR_WDE;
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200151 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200152}
153
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200154static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200155{
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200156 u32 val;
157
158 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
159
160 return val & IMX2_WDT_WCR_WDE;
161}
162
163static int imx2_wdt_ping(struct watchdog_device *wdog)
164{
165 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
166
167 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
168 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
169 return 0;
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200170}
171
Martin Kaisere06f7b62018-01-01 18:26:47 +0100172static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
173 unsigned int new_timeout)
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200174{
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200175 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200176
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200177 regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
Xiubo Lia7977002014-04-04 09:33:25 +0800178 WDOG_SEC_TO_COUNT(new_timeout));
Martin Kaisere06f7b62018-01-01 18:26:47 +0100179}
180
181static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
182 unsigned int new_timeout)
183{
Georg Hofmannc3278cc2019-04-08 21:25:54 +0200184 unsigned int actual;
Martin Kaisere06f7b62018-01-01 18:26:47 +0100185
Rasmus Villemoes2890b712019-08-12 15:13:56 +0200186 actual = min(new_timeout, IMX2_WDT_MAX_TIME);
Georg Hofmannc3278cc2019-04-08 21:25:54 +0200187 __imx2_wdt_set_timeout(wdog, actual);
Martin Kaisere06f7b62018-01-01 18:26:47 +0100188 wdog->timeout = new_timeout;
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200189 return 0;
190}
191
Vladimir Zapolskiy39487f62016-10-07 15:41:39 +0300192static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
193 unsigned int new_pretimeout)
194{
195 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
196
197 if (new_pretimeout >= IMX2_WDT_MAX_TIME)
198 return -EINVAL;
199
200 wdog->pretimeout = new_pretimeout;
201
202 regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
203 IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT,
204 IMX2_WDT_WICR_WIE | (new_pretimeout << 1));
205 return 0;
206}
207
208static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
209{
210 struct watchdog_device *wdog = wdog_arg;
211 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
212
213 regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
214 IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);
215
216 watchdog_notify_pretimeout(wdog);
217
218 return IRQ_HANDLED;
219}
220
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200221static int imx2_wdt_start(struct watchdog_device *wdog)
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200222{
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200223 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200224
Guenter Roeck11d7aba2016-02-28 13:12:20 -0800225 if (imx2_wdt_is_running(wdev))
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200226 imx2_wdt_set_timeout(wdog, wdog->timeout);
Guenter Roeck11d7aba2016-02-28 13:12:20 -0800227 else
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200228 imx2_wdt_setup(wdog);
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200229
Guenter Roeck11d7aba2016-02-28 13:12:20 -0800230 set_bit(WDOG_HW_RUNNING, &wdog->status);
231
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200232 return imx2_wdt_ping(wdog);
233}
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200234
Krzysztof Kozlowski4bd8ce32015-01-05 10:09:17 +0100235static const struct watchdog_ops imx2_wdt_ops = {
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200236 .owner = THIS_MODULE,
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200237 .start = imx2_wdt_start,
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200238 .ping = imx2_wdt_ping,
239 .set_timeout = imx2_wdt_set_timeout,
Vladimir Zapolskiy39487f62016-10-07 15:41:39 +0300240 .set_pretimeout = imx2_wdt_set_pretimeout,
Damien Riegel2d9d24752015-11-16 12:28:04 -0500241 .restart = imx2_wdt_restart,
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200242};
243
Krzysztof Kozlowski4bd8ce32015-01-05 10:09:17 +0100244static const struct regmap_config imx2_wdt_regmap_config = {
Xiubo Lia7977002014-04-04 09:33:25 +0800245 .reg_bits = 16,
246 .reg_stride = 2,
247 .val_bits = 16,
248 .max_register = 0x8,
249};
250
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200251static int __init imx2_wdt_probe(struct platform_device *pdev)
252{
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200253 struct imx2_wdt_device *wdev;
254 struct watchdog_device *wdog;
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200255 struct resource *res;
Xiubo Lia7977002014-04-04 09:33:25 +0800256 void __iomem *base;
257 int ret;
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200258 u32 val;
259
260 wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
261 if (!wdev)
262 return -ENOMEM;
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200263
264 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Xiubo Lia7977002014-04-04 09:33:25 +0800265 base = devm_ioremap_resource(&pdev->dev, res);
266 if (IS_ERR(base))
267 return PTR_ERR(base);
268
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200269 wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
270 &imx2_wdt_regmap_config);
271 if (IS_ERR(wdev->regmap)) {
Xiubo Lia7977002014-04-04 09:33:25 +0800272 dev_err(&pdev->dev, "regmap init failed\n");
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200273 return PTR_ERR(wdev->regmap);
Xiubo Lia7977002014-04-04 09:33:25 +0800274 }
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200275
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200276 wdev->clk = devm_clk_get(&pdev->dev, NULL);
277 if (IS_ERR(wdev->clk)) {
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200278 dev_err(&pdev->dev, "can't get Watchdog clock\n");
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200279 return PTR_ERR(wdev->clk);
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200280 }
281
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200282 wdog = &wdev->wdog;
283 wdog->info = &imx2_wdt_info;
284 wdog->ops = &imx2_wdt_ops;
285 wdog->min_timeout = 1;
Guenter Roeck11d7aba2016-02-28 13:12:20 -0800286 wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
Vladimir Zapolskiy81351932015-06-02 15:46:18 +0300287 wdog->parent = &pdev->dev;
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200288
Vladimir Zapolskiy39487f62016-10-07 15:41:39 +0300289 ret = platform_get_irq(pdev, 0);
290 if (ret > 0)
291 if (!devm_request_irq(&pdev->dev, ret, imx2_wdt_isr, 0,
292 dev_name(&pdev->dev), wdog))
293 wdog->info = &imx2_wdt_pretimeout_info;
294
Fabio Estevamaefb1632015-06-22 01:16:18 -0300295 ret = clk_prepare_enable(wdev->clk);
296 if (ret)
297 return ret;
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200298
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200299 regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
300 wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200301
Tim Harveybc677ff42016-04-01 08:16:43 -0700302 wdev->ext_reset = of_property_read_bool(pdev->dev.of_node,
303 "fsl,ext-reset-output");
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200304 wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
305 if (wdog->timeout != timeout)
306 dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
307 timeout, wdog->timeout);
308
309 platform_set_drvdata(pdev, wdog);
310 watchdog_set_drvdata(wdog, wdev);
311 watchdog_set_nowayout(wdog, nowayout);
Damien Riegel2d9d24752015-11-16 12:28:04 -0500312 watchdog_set_restart_priority(wdog, 128);
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200313 watchdog_init_timeout(wdog, timeout, &pdev->dev);
314
Guenter Roeck11d7aba2016-02-28 13:12:20 -0800315 if (imx2_wdt_is_running(wdev)) {
316 imx2_wdt_set_timeout(wdog, wdog->timeout);
317 set_bit(WDOG_HW_RUNNING, &wdog->status);
318 }
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200319
Markus Pargmann5fe65ce2014-09-08 09:14:07 +0200320 /*
321 * Disable the watchdog power down counter at boot. Otherwise the power
322 * down counter will pull down the #WDOG interrupt line for one clock
323 * cycle.
324 */
325 regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
326
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200327 ret = watchdog_register_device(wdog);
328 if (ret) {
329 dev_err(&pdev->dev, "cannot register watchdog device\n");
Fabio Estevamdb11cba2015-06-22 01:16:19 -0300330 goto disable_clk;
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200331 }
332
333 dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
334 wdog->timeout, nowayout);
335
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200336 return 0;
Fabio Estevamdb11cba2015-06-22 01:16:19 -0300337
338disable_clk:
339 clk_disable_unprepare(wdev->clk);
340 return ret;
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200341}
342
343static int __exit imx2_wdt_remove(struct platform_device *pdev)
344{
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200345 struct watchdog_device *wdog = platform_get_drvdata(pdev);
346 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200347
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200348 watchdog_unregister_device(wdog);
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200349
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200350 if (imx2_wdt_is_running(wdev)) {
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200351 imx2_wdt_ping(wdog);
352 dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
Jingoo Hanbdf49572013-04-29 18:15:53 +0900353 }
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200354 return 0;
355}
356
357static void imx2_wdt_shutdown(struct platform_device *pdev)
358{
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200359 struct watchdog_device *wdog = platform_get_drvdata(pdev);
360 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200361
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200362 if (imx2_wdt_is_running(wdev)) {
363 /*
Guenter Roeck11d7aba2016-02-28 13:12:20 -0800364 * We are running, configure max timeout before reboot
365 * will take place.
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200366 */
Anatolij Gustschinfaad5de2014-04-11 08:57:14 +0200367 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
368 imx2_wdt_ping(wdog);
369 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200370 }
371}
372
Xiubo Liaefbaf32014-09-22 18:00:52 +0800373#ifdef CONFIG_PM_SLEEP
Xiubo Libbd59002014-10-16 11:44:15 +0800374/* Disable watchdog if it is active or non-active but still running */
Xiubo Liaefbaf32014-09-22 18:00:52 +0800375static int imx2_wdt_suspend(struct device *dev)
376{
377 struct watchdog_device *wdog = dev_get_drvdata(dev);
378 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
379
Xiubo Libbd59002014-10-16 11:44:15 +0800380 /* The watchdog IP block is running */
381 if (imx2_wdt_is_running(wdev)) {
Martin Kaisere06f7b62018-01-01 18:26:47 +0100382 /*
383 * Don't update wdog->timeout, we'll restore the current value
384 * during resume.
385 */
386 __imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
Xiubo Libbd59002014-10-16 11:44:15 +0800387 imx2_wdt_ping(wdog);
Xiubo Libbd59002014-10-16 11:44:15 +0800388 }
Xiubo Liaefbaf32014-09-22 18:00:52 +0800389
390 clk_disable_unprepare(wdev->clk);
391
392 return 0;
393}
394
395/* Enable watchdog and configure it if necessary */
396static int imx2_wdt_resume(struct device *dev)
397{
398 struct watchdog_device *wdog = dev_get_drvdata(dev);
399 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
Fabio Estevamaefb1632015-06-22 01:16:18 -0300400 int ret;
Xiubo Liaefbaf32014-09-22 18:00:52 +0800401
Fabio Estevamaefb1632015-06-22 01:16:18 -0300402 ret = clk_prepare_enable(wdev->clk);
403 if (ret)
404 return ret;
Xiubo Liaefbaf32014-09-22 18:00:52 +0800405
406 if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
Xiubo Libbd59002014-10-16 11:44:15 +0800407 /*
408 * If the watchdog is still active and resumes
409 * from deep sleep state, need to restart the
410 * watchdog again.
Xiubo Liaefbaf32014-09-22 18:00:52 +0800411 */
412 imx2_wdt_setup(wdog);
Guenter Roeck11d7aba2016-02-28 13:12:20 -0800413 }
414 if (imx2_wdt_is_running(wdev)) {
Xiubo Liaefbaf32014-09-22 18:00:52 +0800415 imx2_wdt_set_timeout(wdog, wdog->timeout);
416 imx2_wdt_ping(wdog);
Xiubo Liaefbaf32014-09-22 18:00:52 +0800417 }
418
419 return 0;
420}
421#endif
422
423static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
424 imx2_wdt_resume);
425
Shawn Guof5a427e2011-07-18 11:15:21 +0800426static const struct of_device_id imx2_wdt_dt_ids[] = {
427 { .compatible = "fsl,imx21-wdt", },
428 { /* sentinel */ }
429};
Niels de Vos813296a2013-07-29 09:38:18 +0200430MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
Shawn Guof5a427e2011-07-18 11:15:21 +0800431
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200432static struct platform_driver imx2_wdt_driver = {
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200433 .remove = __exit_p(imx2_wdt_remove),
434 .shutdown = imx2_wdt_shutdown,
435 .driver = {
436 .name = DRIVER_NAME,
Xiubo Liaefbaf32014-09-22 18:00:52 +0800437 .pm = &imx2_wdt_pm_ops,
Shawn Guof5a427e2011-07-18 11:15:21 +0800438 .of_match_table = imx2_wdt_dt_ids,
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200439 },
440};
441
Fabio Porcedda1cb92042013-01-09 12:15:27 +0100442module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200443
444MODULE_AUTHOR("Wolfram Sang");
445MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
446MODULE_LICENSE("GPL v2");
Wolfram Sangbb2fd8a2010-04-29 10:03:17 +0200447MODULE_ALIAS("platform:" DRIVER_NAME);