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Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001/*
2 * Driver for the Synopsys DesignWare AHB DMA Controller
3 *
4 * Copyright (C) 2005-2007 Atmel Corporation
Viresh Kumaraecb7b62011-05-24 14:04:09 +05305 * Copyright (C) 2010-2011 ST Microelectronics
Andy Shevchenkoa9f4d1b2017-01-17 13:57:30 +02006 * Copyright (C) 2016 Intel Corporation
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
Andy Shevchenko2d248812017-01-17 13:57:29 +020013#include <linux/bitops.h>
Andy Shevchenko9cade1a2013-06-05 15:26:45 +030014#include <linux/interrupt.h>
Andy Shevchenko0fdb5672013-01-10 10:53:03 +020015#include <linux/dmaengine.h>
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070016
Andy Shevchenkoa9f4d1b2017-01-17 13:57:30 +020017#include <linux/io-64-nonatomic-hi-lo.h>
18
Eugeniy Paltsevbd2c6632016-11-25 17:59:07 +030019#include "internal.h"
20
Arnd Bergmannf9c6a652013-02-27 21:36:03 +000021#define DW_DMA_MAX_NR_REQUESTS 16
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070022
Viresh Kumara1c46012012-02-01 16:12:28 +053023/* flow controller */
24enum dw_dma_fc {
25 DW_DMA_FC_D_M2M,
26 DW_DMA_FC_D_M2P,
27 DW_DMA_FC_D_P2M,
28 DW_DMA_FC_D_P2P,
29 DW_DMA_FC_P_P2M,
30 DW_DMA_FC_SP_P2P,
31 DW_DMA_FC_P_M2P,
32 DW_DMA_FC_DP_P2P,
33};
34
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070035/*
36 * Redefine this macro to handle differences between 32- and 64-bit
37 * addressing, big vs. little endian, etc.
38 */
39#define DW_REG(name) u32 name; u32 __pad_##name
40
41/* Hardware register definitions. */
42struct dw_dma_chan_regs {
43 DW_REG(SAR); /* Source Address Register */
44 DW_REG(DAR); /* Destination Address Register */
45 DW_REG(LLP); /* Linked List Pointer */
46 u32 CTL_LO; /* Control Register Low */
47 u32 CTL_HI; /* Control Register High */
48 DW_REG(SSTAT);
49 DW_REG(DSTAT);
50 DW_REG(SSTATAR);
51 DW_REG(DSTATAR);
52 u32 CFG_LO; /* Configuration Register Low */
53 u32 CFG_HI; /* Configuration Register High */
54 DW_REG(SGR);
55 DW_REG(DSR);
56};
57
58struct dw_dma_irq_regs {
59 DW_REG(XFER);
60 DW_REG(BLOCK);
61 DW_REG(SRC_TRAN);
62 DW_REG(DST_TRAN);
63 DW_REG(ERROR);
64};
65
66struct dw_dma_regs {
67 /* per-channel registers */
68 struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
69
70 /* irq handling */
71 struct dw_dma_irq_regs RAW; /* r */
72 struct dw_dma_irq_regs STATUS; /* r (raw & mask) */
73 struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */
74 struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */
75
76 DW_REG(STATUS_INT); /* r */
77
78 /* software handshaking */
79 DW_REG(REQ_SRC);
80 DW_REG(REQ_DST);
81 DW_REG(SGL_REQ_SRC);
82 DW_REG(SGL_REQ_DST);
83 DW_REG(LAST_SRC);
84 DW_REG(LAST_DST);
85
86 /* miscellaneous */
87 DW_REG(CFG);
88 DW_REG(CH_EN);
89 DW_REG(ID);
90 DW_REG(TEST);
91
Andy Shevchenkoa9f4d1b2017-01-17 13:57:30 +020092 /* iDMA 32-bit support */
93 DW_REG(CLASS_PRIORITY0);
94 DW_REG(CLASS_PRIORITY1);
Andy Shevchenko2a9fe9a2012-09-21 15:05:45 +030095
Andy Shevchenko745664e2012-06-19 13:34:01 +030096 /* optional encoded params, 0x3c8..0x3f7 */
Andy Shevchenko2a9fe9a2012-09-21 15:05:45 +030097 u32 __reserved;
98
99 /* per-channel configuration registers */
100 u32 DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
101 u32 MULTI_BLK_TYPE;
102 u32 MAX_BLK_SIZE;
103
104 /* top-level parameters */
105 u32 DW_PARAMS;
Andy Shevchenkoa9f4d1b2017-01-17 13:57:30 +0200106
107 /* component ID */
108 u32 COMP_TYPE;
109 u32 COMP_VERSION;
110
111 /* iDMA 32-bit support */
112 DW_REG(FIFO_PARTITION0);
113 DW_REG(FIFO_PARTITION1);
114
115 DW_REG(SAI_ERR);
116 DW_REG(GLOBAL_CFG);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700117};
118
Andy Shevchenko2a9fe9a2012-09-21 15:05:45 +0300119/* Bitfields in DW_PARAMS */
120#define DW_PARAMS_NR_CHAN 8 /* number of channels */
121#define DW_PARAMS_NR_MASTER 11 /* number of AHB masters */
122#define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n))
123#define DW_PARAMS_DATA_WIDTH1 15 /* master 1 data width */
124#define DW_PARAMS_DATA_WIDTH2 17 /* master 2 data width */
125#define DW_PARAMS_DATA_WIDTH3 19 /* master 3 data width */
126#define DW_PARAMS_DATA_WIDTH4 21 /* master 4 data width */
127#define DW_PARAMS_EN 28 /* encoded parameters */
128
129/* Bitfields in DWC_PARAMS */
130#define DWC_PARAMS_MBLK_EN 11 /* multi block transfer */
131
Andy Shevchenko46e8c832014-09-23 17:18:10 +0300132/* bursts size */
133enum dw_dma_msize {
134 DW_DMA_MSIZE_1,
135 DW_DMA_MSIZE_4,
136 DW_DMA_MSIZE_8,
137 DW_DMA_MSIZE_16,
138 DW_DMA_MSIZE_32,
139 DW_DMA_MSIZE_64,
140 DW_DMA_MSIZE_128,
141 DW_DMA_MSIZE_256,
142};
143
Mans Rullgard2a0fae02016-03-18 16:24:44 +0200144/* Bitfields in LLP */
145#define DWC_LLP_LMS(x) ((x) & 3) /* list master select */
146#define DWC_LLP_LOC(x) ((x) & ~3) /* next lli */
147
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700148/* Bitfields in CTL_LO */
149#define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */
150#define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */
151#define DWC_CTLL_SRC_WIDTH(n) ((n)<<4)
152#define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */
153#define DWC_CTLL_DST_DEC (1<<7)
154#define DWC_CTLL_DST_FIX (2<<7)
Jie Yangc9784a42016-01-07 08:39:33 +0800155#define DWC_CTLL_SRC_INC (0<<9) /* SAR update/not */
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700156#define DWC_CTLL_SRC_DEC (1<<9)
157#define DWC_CTLL_SRC_FIX (2<<9)
158#define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */
159#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
160#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */
161#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */
Viresh KUMARee665092011-03-04 15:42:51 +0530162#define DWC_CTLL_FC(n) ((n) << 20)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700163#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */
164#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
165#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
166#define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */
167/* plus 4 transfer types for peripheral-as-flow-controller */
168#define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */
169#define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */
170#define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */
171#define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */
172
173/* Bitfields in CTL_HI */
Andy Shevchenko2d248812017-01-17 13:57:29 +0200174#define DWC_CTLH_BLOCK_TS_MASK GENMASK(11, 0)
175#define DWC_CTLH_BLOCK_TS(x) ((x) & DWC_CTLH_BLOCK_TS_MASK)
176#define DWC_CTLH_DONE (1 << 12)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700177
Andy Shevchenko46e8c832014-09-23 17:18:10 +0300178/* Bitfields in CFG_LO */
Viresh Kumar93317e82011-03-03 15:47:22 +0530179#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */
180#define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700181#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */
182#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */
183#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */
184#define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */
Andy Shevchenko46e8c832014-09-23 17:18:10 +0300185#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
186#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
187#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
188#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
189#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
190#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
191#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
192#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
193#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
194#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700195#define DWC_CFGL_MAX_BURST(x) ((x) << 20)
196#define DWC_CFGL_RELOAD_SAR (1 << 30)
197#define DWC_CFGL_RELOAD_DAR (1 << 31)
198
Andy Shevchenko46e8c832014-09-23 17:18:10 +0300199/* Bitfields in CFG_HI */
200#define DWC_CFGH_FCMODE (1 << 0)
201#define DWC_CFGH_FIFO_MODE (1 << 1)
202#define DWC_CFGH_PROTCTL(x) ((x) << 2)
Christian Lamparter2d91b552018-11-17 17:17:21 +0100203#define DWC_CFGH_PROTCTL_DATA (0 << 2) /* data access - always set */
204#define DWC_CFGH_PROTCTL_PRIV (1 << 2) /* privileged -> AHB HPROT[1] */
205#define DWC_CFGH_PROTCTL_BUFFER (2 << 2) /* bufferable -> AHB HPROT[2] */
206#define DWC_CFGH_PROTCTL_CACHE (4 << 2) /* cacheable -> AHB HPROT[3] */
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700207#define DWC_CFGH_DS_UPD_EN (1 << 5)
208#define DWC_CFGH_SS_UPD_EN (1 << 6)
Andy Shevchenko46e8c832014-09-23 17:18:10 +0300209#define DWC_CFGH_SRC_PER(x) ((x) << 7)
210#define DWC_CFGH_DST_PER(x) ((x) << 11)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700211
212/* Bitfields in SGR */
213#define DWC_SGR_SGI(x) ((x) << 0)
214#define DWC_SGR_SGC(x) ((x) << 20)
215
216/* Bitfields in DSR */
217#define DWC_DSR_DSI(x) ((x) << 0)
218#define DWC_DSR_DSC(x) ((x) << 20)
219
220/* Bitfields in CFG */
221#define DW_CFG_DMA_EN (1 << 0)
222
Andy Shevchenkoa9f4d1b2017-01-17 13:57:30 +0200223/* iDMA 32-bit support */
224
225/* Bitfields in CTL_HI */
226#define IDMA32C_CTLH_BLOCK_TS_MASK GENMASK(16, 0)
227#define IDMA32C_CTLH_BLOCK_TS(x) ((x) & IDMA32C_CTLH_BLOCK_TS_MASK)
228#define IDMA32C_CTLH_DONE (1 << 17)
229
230/* Bitfields in CFG_LO */
231#define IDMA32C_CFGL_DST_BURST_ALIGN (1 << 0) /* dst burst align */
232#define IDMA32C_CFGL_SRC_BURST_ALIGN (1 << 1) /* src burst align */
233#define IDMA32C_CFGL_CH_DRAIN (1 << 10) /* drain FIFO */
234#define IDMA32C_CFGL_DST_OPT_BL (1 << 20) /* optimize dst burst length */
235#define IDMA32C_CFGL_SRC_OPT_BL (1 << 21) /* optimize src burst length */
236
237/* Bitfields in CFG_HI */
238#define IDMA32C_CFGH_SRC_PER(x) ((x) << 0)
239#define IDMA32C_CFGH_DST_PER(x) ((x) << 4)
240#define IDMA32C_CFGH_RD_ISSUE_THD(x) ((x) << 8)
241#define IDMA32C_CFGH_RW_ISSUE_THD(x) ((x) << 18)
242#define IDMA32C_CFGH_SRC_PER_EXT(x) ((x) << 28) /* src peripheral extension */
243#define IDMA32C_CFGH_DST_PER_EXT(x) ((x) << 30) /* dst peripheral extension */
244
245/* Bitfields in FIFO_PARTITION */
246#define IDMA32C_FP_PSIZE_CH0(x) ((x) << 0)
247#define IDMA32C_FP_PSIZE_CH1(x) ((x) << 13)
248#define IDMA32C_FP_UPDATE (1 << 26)
249
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200250enum dw_dmac_flags {
251 DW_DMA_IS_CYCLIC = 0,
Andy Shevchenkofed25742012-09-21 15:05:49 +0300252 DW_DMA_IS_SOFT_LLP = 1,
Andy Shevchenko5e09f982016-03-18 16:24:51 +0200253 DW_DMA_IS_PAUSED = 2,
Andy Shevchenko423f9cb2016-03-18 16:24:52 +0200254 DW_DMA_IS_INITIALIZED = 3,
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200255};
256
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700257struct dw_dma_chan {
Andy Shevchenko0fdb5672013-01-10 10:53:03 +0200258 struct dma_chan chan;
259 void __iomem *ch_regs;
260 u8 mask;
261 u8 priority;
262 enum dma_transfer_direction direction;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700263
Andy Shevchenkofed25742012-09-21 15:05:49 +0300264 /* software emulation of the LLP transfers */
Andy Shevchenkofed25742012-09-21 15:05:49 +0300265 struct list_head *tx_node_active;
266
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700267 spinlock_t lock;
268
269 /* these other elements are all protected by lock */
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200270 unsigned long flags;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700271 struct list_head active_list;
272 struct list_head queue;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700273
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700274 unsigned int descs_allocated;
Viresh Kumar327e6972012-02-01 16:12:26 +0530275
Andy Shevchenko4a63a8b2012-09-21 15:05:47 +0300276 /* hardware configuration */
277 unsigned int block_size;
Andy Shevchenkofed25742012-09-21 15:05:49 +0300278 bool nollp;
Arnd Bergmannf7760762013-03-26 16:53:57 +0200279
280 /* custom slave configuration */
Andy Shevchenko9217a5b2016-08-17 19:20:20 +0300281 struct dw_dma_slave dws;
Andy Shevchenko4a63a8b2012-09-21 15:05:47 +0300282
Vinod Koul295d3e12014-12-22 20:24:14 +0530283 /* configuration passed via .device_config */
Viresh Kumar327e6972012-02-01 16:12:26 +0530284 struct dma_slave_config dma_sconfig;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700285};
286
287static inline struct dw_dma_chan_regs __iomem *
288__dwc_regs(struct dw_dma_chan *dwc)
289{
290 return dwc->ch_regs;
291}
292
293#define channel_readl(dwc, name) \
Andy Shevchenko14bebd02017-05-09 19:18:37 +0300294 readl(&(__dwc_regs(dwc)->name))
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700295#define channel_writel(dwc, name, val) \
Andy Shevchenko14bebd02017-05-09 19:18:37 +0300296 writel((val), &(__dwc_regs(dwc)->name))
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700297
298static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
299{
300 return container_of(chan, struct dw_dma_chan, chan);
301}
302
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700303struct dw_dma {
304 struct dma_device dma;
Andy Shevchenko08d62f52017-01-17 13:57:26 +0200305 char name[20];
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700306 void __iomem *regs;
Andy Shevchenkof8122a82013-01-16 15:48:50 +0200307 struct dma_pool *desc_pool;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700308 struct tasklet_struct tasklet;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700309
Andy Shevchenko000871c2014-03-05 15:48:12 +0200310 /* channels */
311 struct dw_dma_chan *chan;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700312 u8 all_chan_mask;
Andy Shevchenko99d9bf42014-09-23 17:18:14 +0300313 u8 in_use;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700314
Andy Shevchenko161c3d02016-04-27 14:15:39 +0300315 /* platform data */
316 struct dw_dma_platform_data *pdata;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700317};
318
319static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
320{
321 return dw->regs;
322}
323
324#define dma_readl(dw, name) \
Andy Shevchenko14bebd02017-05-09 19:18:37 +0300325 readl(&(__dw_regs(dw)->name))
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700326#define dma_writel(dw, name, val) \
Andy Shevchenko14bebd02017-05-09 19:18:37 +0300327 writel((val), &(__dw_regs(dw)->name))
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700328
Andy Shevchenkoa9f4d1b2017-01-17 13:57:30 +0200329#define idma32_readq(dw, name) \
330 hi_lo_readq(&(__dw_regs(dw)->name))
331#define idma32_writeq(dw, name, val) \
332 hi_lo_writeq((val), &(__dw_regs(dw)->name))
333
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700334#define channel_set_bit(dw, reg, mask) \
335 dma_writel(dw, reg, ((mask) << 8) | (mask))
336#define channel_clear_bit(dw, reg, mask) \
337 dma_writel(dw, reg, ((mask) << 8) | 0)
338
339static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
340{
341 return container_of(ddev, struct dw_dma, dma);
342}
343
344/* LLI == Linked List Item; a.k.a. DMA block descriptor */
345struct dw_lli {
346 /* values that are not changed by hardware */
Andy Shevchenko14bebd02017-05-09 19:18:37 +0300347 __le32 sar;
348 __le32 dar;
349 __le32 llp; /* chain to next lli */
350 __le32 ctllo;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700351 /* values that may get written back: */
Andy Shevchenko14bebd02017-05-09 19:18:37 +0300352 __le32 ctlhi;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700353 /* sstat and dstat can snapshot peripheral register state.
354 * silicon config may discard either or both...
355 */
Andy Shevchenko14bebd02017-05-09 19:18:37 +0300356 __le32 sstat;
357 __le32 dstat;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700358};
359
360struct dw_desc {
361 /* FIRST values the hardware uses */
362 struct dw_lli lli;
363
Mans Rullgarddf1f3a22016-03-18 16:24:43 +0200364#define lli_set(d, reg, v) ((d)->lli.reg |= cpu_to_le32(v))
365#define lli_clear(d, reg, v) ((d)->lli.reg &= ~cpu_to_le32(v))
366#define lli_read(d, reg) le32_to_cpu((d)->lli.reg)
367#define lli_write(d, reg, v) ((d)->lli.reg = cpu_to_le32(v))
Mans Rullgarddf1f3a22016-03-18 16:24:43 +0200368
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700369 /* THEN values for driver housekeeping */
370 struct list_head desc_node;
Dan Williamse0bd0f82009-09-08 17:53:02 -0700371 struct list_head tx_list;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700372 struct dma_async_tx_descriptor txd;
373 size_t len;
Andy Shevchenko30d38a32013-01-25 11:48:01 +0200374 size_t total_len;
Andy Shevchenkob68fd092016-03-18 16:24:53 +0200375 u32 residue;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700376};
377
Andy Shevchenkoe63a47a32012-10-18 17:34:12 +0300378#define to_dw_desc(h) list_entry(h, struct dw_desc, desc_node)
379
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700380static inline struct dw_desc *
381txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
382{
383 return container_of(txd, struct dw_desc, txd);
384}