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Tony Lindgren1dbae812005-11-10 14:26:51 +00001/*
Tony Lindgren0f622e82011-03-29 15:54:50 -07002 * linux/arch/arm/mach-omap2/timer.c
Tony Lindgren1dbae812005-11-10 14:26:51 +00003 *
4 * OMAP2 GP timer support.
5 *
Paul Walmsleyf2480762009-04-23 21:11:10 -06006 * Copyright (C) 2009 Nokia Corporation
7 *
Kevin Hilman5a3a3882007-11-12 23:24:02 -08008 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
11 *
12 * Original driver:
Tony Lindgren1dbae812005-11-10 14:26:51 +000013 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
Jan Engelhardt96de0e22007-10-19 23:21:04 +020015 * Juha Yrjölä <juha.yrjola@nokia.com>
Timo Teras77900a22006-06-26 16:16:12 -070016 * OMAP Dual-mode timer framework support by Timo Teras
Tony Lindgren1dbae812005-11-10 14:26:51 +000017 *
18 * Some parts based off of TI's 24xx code:
19 *
Santosh Shilimkar44169072009-05-28 14:16:04 -070020 * Copyright (C) 2004-2009 Texas Instruments, Inc.
Tony Lindgren1dbae812005-11-10 14:26:51 +000021 *
22 * Roughly modelled after the OMAP1 MPU timer code.
Santosh Shilimkar44169072009-05-28 14:16:04 -070023 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
Tony Lindgren1dbae812005-11-10 14:26:51 +000024 *
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
27 * for more details.
28 */
29#include <linux/init.h>
30#include <linux/time.h>
31#include <linux/interrupt.h>
32#include <linux/err.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000033#include <linux/clk.h>
Timo Teras77900a22006-06-26 16:16:12 -070034#include <linux/delay.h>
Dirk Behmee6687292006-12-06 17:14:00 -080035#include <linux/irq.h>
Kevin Hilman5a3a3882007-11-12 23:24:02 -080036#include <linux/clocksource.h>
37#include <linux/clockchips.h>
Tarun Kanti DebBarmac345c8b2011-09-20 17:00:18 +053038#include <linux/slab.h>
Santosh Shilimkareed0de22012-07-04 18:32:32 +053039#include <linux/of.h>
Jon Hunter9725f442012-05-14 10:41:37 -050040#include <linux/of_address.h>
41#include <linux/of_irq.h>
Jon Hunter40fc3bb2012-09-28 11:34:49 -050042#include <linux/platform_device.h>
43#include <linux/platform_data/dmtimer-omap.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070044#include <linux/sched_clock.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000045
Tony Lindgren1dbae812005-11-10 14:26:51 +000046#include <asm/mach/time.h>
Marc Zyngiera45c9832012-01-10 19:44:19 +000047#include <asm/smp_twd.h>
Tony Lindgren7d7e1eb2012-08-27 17:43:01 -070048
Tony Lindgren2a296c82012-10-02 17:41:35 -070049#include "omap_hwmod.h"
Tony Lindgren25c7d492012-10-02 17:25:48 -070050#include "omap_device.h"
Tony Lindgren5c2e8852012-10-29 16:45:47 -070051#include <plat/counter-32k.h>
Tony Lindgren7d7e1eb2012-08-27 17:43:01 -070052#include <plat/dmtimer.h>
Tony Lindgren1d5aef42012-10-03 16:36:40 -070053#include "omap-pm.h"
Tarun Kanti DebBarmab4811132011-09-20 17:00:24 +053054
Tony Lindgrendbc04162012-08-31 10:59:07 -070055#include "soc.h"
Tony Lindgren7d7e1eb2012-08-27 17:43:01 -070056#include "common.h"
Lennart Sorensenafc9d592015-01-05 15:45:45 -080057#include "control.h"
Tarun Kanti DebBarmab4811132011-09-20 17:00:24 +053058#include "powerdomain.h"
R Sricharan5523e402013-10-10 13:13:48 +053059#include "omap-secure.h"
Tony Lindgren1dbae812005-11-10 14:26:51 +000060
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +053061#define REALTIME_COUNTER_BASE 0x48243200
62#define INCREMENTER_NUMERATOR_OFFSET 0x10
63#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
64#define NUMERATOR_DENUMERATOR_MASK 0xfffff000
65
Tony Lindgrenaa561882011-03-29 15:54:48 -070066/* Clockevent code */
67
68static struct omap_dm_timer clkev;
Kevin Hilman5a3a3882007-11-12 23:24:02 -080069static struct clock_event_device clockevent_gpt;
Tony Lindgren1dbae812005-11-10 14:26:51 +000070
Dave Gerlach12b28ba2017-03-28 20:57:55 -050071/* Clockevent hwmod for am335x and am437x suspend */
72static struct omap_hwmod *clockevent_gpt_hwmod;
73
Tony Lindgrend5da94b2013-10-11 17:28:04 -070074#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
R Sricharan5523e402013-10-10 13:13:48 +053075static unsigned long arch_timer_freq;
76
77void set_cntfreq(void)
78{
79 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
80}
Tony Lindgrend5da94b2013-10-11 17:28:04 -070081#endif
Tony Lindgren1dbae812005-11-10 14:26:51 +000082
Linus Torvalds0cd61b62006-10-06 10:53:39 -070083static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
Tony Lindgren1dbae812005-11-10 14:26:51 +000084{
Kevin Hilman5a3a3882007-11-12 23:24:02 -080085 struct clock_event_device *evt = &clockevent_gpt;
Tony Lindgren1dbae812005-11-10 14:26:51 +000086
Tony Lindgrenee17f112011-09-16 15:44:20 -070087 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
Kevin Hilman5a3a3882007-11-12 23:24:02 -080088
89 evt->event_handler(evt);
Tony Lindgren1dbae812005-11-10 14:26:51 +000090 return IRQ_HANDLED;
91}
92
93static struct irqaction omap2_gp_timer_irq = {
Vaibhav Hiremathf36921b2012-05-09 10:07:05 -070094 .name = "gp_timer",
Michael Opdenackerfe806d02013-09-07 09:19:25 +020095 .flags = IRQF_TIMER | IRQF_IRQPOLL,
Tony Lindgren1dbae812005-11-10 14:26:51 +000096 .handler = omap2_gp_timer_interrupt,
97};
98
Kevin Hilman5a3a3882007-11-12 23:24:02 -080099static int omap2_gp_timer_set_next_event(unsigned long cycles,
100 struct clock_event_device *evt)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000101{
Tony Lindgrenee17f112011-09-16 15:44:20 -0700102 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
Jon Hunter971d0252012-09-27 11:49:45 -0500103 0xffffffff - cycles, OMAP_TIMER_POSTED);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000104
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800105 return 0;
106}
107
Viresh Kumar74364612015-02-27 13:39:52 +0530108static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
109{
110 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
111 return 0;
112}
113
114static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800115{
116 u32 period;
117
Jon Hunter971d0252012-09-27 11:49:45 -0500118 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800119
Viresh Kumar74364612015-02-27 13:39:52 +0530120 period = clkev.rate / HZ;
121 period -= 1;
122 /* Looks like we need to first set the load value separately */
123 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
124 OMAP_TIMER_POSTED);
125 __omap_dm_timer_load_start(&clkev,
126 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
127 0xffffffff - period, OMAP_TIMER_POSTED);
128 return 0;
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800129}
130
Dave Gerlach12b28ba2017-03-28 20:57:55 -0500131static void omap_clkevt_idle(struct clock_event_device *unused)
132{
133 if (!clockevent_gpt_hwmod)
134 return;
135
136 omap_hwmod_idle(clockevent_gpt_hwmod);
137}
138
139static void omap_clkevt_unidle(struct clock_event_device *unused)
140{
141 if (!clockevent_gpt_hwmod)
142 return;
143
144 omap_hwmod_enable(clockevent_gpt_hwmod);
145 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
146}
147
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800148static struct clock_event_device clockevent_gpt = {
Viresh Kumar74364612015-02-27 13:39:52 +0530149 .features = CLOCK_EVT_FEAT_PERIODIC |
150 CLOCK_EVT_FEAT_ONESHOT,
151 .rating = 300,
152 .set_next_event = omap2_gp_timer_set_next_event,
153 .set_state_shutdown = omap2_gp_timer_shutdown,
154 .set_state_periodic = omap2_gp_timer_set_periodic,
155 .set_state_oneshot = omap2_gp_timer_shutdown,
156 .tick_resume = omap2_gp_timer_shutdown,
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800157};
158
Uwe Kleine-König31957602014-09-10 10:26:17 +0200159static const struct of_device_id omap_timer_match[] __initconst = {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500160 { .compatible = "ti,omap2420-timer", },
161 { .compatible = "ti,omap3430-timer", },
162 { .compatible = "ti,omap4430-timer", },
163 { .compatible = "ti,omap5430-timer", },
Tony Lindgren132754e2015-01-14 17:37:16 -0800164 { .compatible = "ti,dm814-timer", },
165 { .compatible = "ti,dm816-timer", },
Jon Hunter002e1ec2013-03-19 12:38:18 -0500166 { .compatible = "ti,am335x-timer", },
167 { .compatible = "ti,am335x-timer-1ms", },
Jon Hunterad24bde2012-06-20 15:55:24 -0500168 { }
169};
170
171/**
Jon Hunter9725f442012-05-14 10:41:37 -0500172 * omap_get_timer_dt - get a timer using device-tree
173 * @match - device-tree match structure for matching a device type
174 * @property - optional timer property to match
175 *
176 * Helper function to get a timer during early boot using device-tree for use
177 * as kernel system timer. Optionally, the property argument can be used to
178 * select a timer with a specific property. Once a timer is found then mark
179 * the timer node in device-tree as disabled, to prevent the kernel from
180 * registering this timer as a platform device and so no one else can use it.
181 */
Uwe Kleine-König31957602014-09-10 10:26:17 +0200182static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
Jon Hunter9725f442012-05-14 10:41:37 -0500183 const char *property)
184{
185 struct device_node *np;
186
187 for_each_matching_node(np, match) {
Pantelis Antoniou034bf092013-01-08 15:31:42 +0200188 if (!of_device_is_available(np))
Jon Hunter9725f442012-05-14 10:41:37 -0500189 continue;
Jon Hunter9725f442012-05-14 10:41:37 -0500190
Pantelis Antoniou034bf092013-01-08 15:31:42 +0200191 if (property && !of_get_property(np, property, NULL))
Jon Hunter9725f442012-05-14 10:41:37 -0500192 continue;
Jon Hunter9725f442012-05-14 10:41:37 -0500193
Jon Hunter2eb03932013-01-28 17:53:57 -0600194 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
195 of_get_property(np, "ti,timer-dsp", NULL) ||
196 of_get_property(np, "ti,timer-pwm", NULL) ||
197 of_get_property(np, "ti,timer-secure", NULL)))
198 continue;
199
Qi Hou7ffe1002018-01-11 12:54:43 +0800200 if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
201 struct property *prop;
202
203 prop = kzalloc(sizeof(*prop), GFP_KERNEL);
204 if (!prop)
205 return NULL;
206 prop->name = "status";
207 prop->value = "disabled";
208 prop->length = strlen(prop->value);
209 of_add_property(np, prop);
210 }
Jon Hunter9725f442012-05-14 10:41:37 -0500211 return np;
212 }
213
214 return NULL;
215}
216
217/**
Jon Hunterad24bde2012-06-20 15:55:24 -0500218 * omap_dmtimer_init - initialisation function when device tree is used
219 *
Suman Annaed5a4c62015-10-05 18:28:22 -0500220 * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
221 * cannot be used by the kernel as they are reserved. Therefore, to prevent the
Jon Hunterad24bde2012-06-20 15:55:24 -0500222 * kernel registering these devices remove them dynamically from the device
223 * tree on boot.
224 */
Vaibhav Hiremathbf85f202012-11-28 15:56:41 -0600225static void __init omap_dmtimer_init(void)
Jon Hunterad24bde2012-06-20 15:55:24 -0500226{
227 struct device_node *np;
228
Suman Annaed5a4c62015-10-05 18:28:22 -0500229 if (!cpu_is_omap34xx() && !soc_is_dra7xx())
Jon Hunterad24bde2012-06-20 15:55:24 -0500230 return;
231
232 /* If we are a secure device, remove any secure timer nodes */
233 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
Jon Hunter9725f442012-05-14 10:41:37 -0500234 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
Markus Elfring9a0cb982015-06-30 14:00:16 +0200235 of_node_put(np);
Jon Hunterad24bde2012-06-20 15:55:24 -0500236 }
237}
238
Jon Hunterbfd6d022012-09-27 12:47:43 -0500239/**
240 * omap_dm_timer_get_errata - get errata flags for a timer
241 *
242 * Get the timer errata flags that are specific to the OMAP device being used.
243 */
Vaibhav Hiremathbf85f202012-11-28 15:56:41 -0600244static u32 __init omap_dm_timer_get_errata(void)
Jon Hunterbfd6d022012-09-27 12:47:43 -0500245{
246 if (cpu_is_omap24xx())
247 return 0;
248
249 return OMAP_TIMER_ERRATA_I103_I767;
250}
251
Tony Lindgrenaa561882011-03-29 15:54:48 -0700252static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
Jon Huntere95ea432013-01-29 13:55:25 -0600253 const char *fck_source,
254 const char *property,
255 const char **timer_name,
256 int posted)
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800257{
Afzal Mohammed37bd6ca2013-05-28 11:54:48 +0530258 const char *oh_name = NULL;
Jon Hunter9725f442012-05-14 10:41:37 -0500259 struct device_node *np;
Tony Lindgrenaa561882011-03-29 15:54:48 -0700260 struct omap_hwmod *oh;
Jon Huntera7990a12013-03-12 17:17:57 -0500261 struct clk *src;
Jon Hunterf88095b2012-11-09 17:07:39 -0600262 int r = 0;
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800263
Tony Lindgren8d39ff32017-05-31 15:51:30 -0700264 np = omap_get_timer_dt(omap_timer_match, property);
265 if (!np)
266 return -ENODEV;
Jon Hunter9725f442012-05-14 10:41:37 -0500267
Tony Lindgren8d39ff32017-05-31 15:51:30 -0700268 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
269 if (!oh_name)
270 return -ENODEV;
Jon Hunter9725f442012-05-14 10:41:37 -0500271
Tony Lindgren8d39ff32017-05-31 15:51:30 -0700272 timer->irq = irq_of_parse_and_map(np, 0);
273 if (!timer->irq)
274 return -ENXIO;
Jon Hunter9725f442012-05-14 10:41:37 -0500275
Tony Lindgren8d39ff32017-05-31 15:51:30 -0700276 timer->io_base = of_iomap(np, 0);
Jon Hunter9725f442012-05-14 10:41:37 -0500277
Tony Lindgren67d00472017-06-12 03:27:30 -0700278 timer->fclk = of_clk_get_by_name(np, "fck");
Jon Hunter9725f442012-05-14 10:41:37 -0500279
Tony Lindgren8d39ff32017-05-31 15:51:30 -0700280 of_node_put(np);
Jon Hunter9725f442012-05-14 10:41:37 -0500281
Jon Hunter9725f442012-05-14 10:41:37 -0500282 oh = omap_hwmod_lookup(oh_name);
Tony Lindgrenaa561882011-03-29 15:54:48 -0700283 if (!oh)
284 return -ENODEV;
Paul Walmsleyf2480762009-04-23 21:11:10 -0600285
Jon Huntere95ea432013-01-29 13:55:25 -0600286 *timer_name = oh->name;
287
Tony Lindgrenaa561882011-03-29 15:54:48 -0700288 if (!timer->io_base)
289 return -ENXIO;
290
Tero Kristoe98580e2016-06-30 16:15:01 +0300291 omap_hwmod_setup_one(oh_name);
292
Tony Lindgrenaa561882011-03-29 15:54:48 -0700293 /* After the dmtimer is using hwmod these clocks won't be needed */
Tero Kristo138f7ca2017-05-31 17:59:58 +0300294 if (IS_ERR_OR_NULL(timer->fclk))
295 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
Tony Lindgrenaa561882011-03-29 15:54:48 -0700296 if (IS_ERR(timer->fclk))
Jon Huntera7990a12013-03-12 17:17:57 -0500297 return PTR_ERR(timer->fclk);
Tony Lindgrenaa561882011-03-29 15:54:48 -0700298
Jon Huntera7990a12013-03-12 17:17:57 -0500299 src = clk_get(NULL, fck_source);
300 if (IS_ERR(src))
301 return PTR_ERR(src);
Tony Lindgrenaa561882011-03-29 15:54:48 -0700302
Tony Lindgren874b3002015-09-01 13:59:25 -0700303 WARN(clk_set_parent(timer->fclk, src) < 0,
304 "Cannot set timer parent clock, no PLL clock driver?");
Jon Hunterb1538832012-09-28 11:43:30 -0500305
Jon Huntera7990a12013-03-12 17:17:57 -0500306 clk_put(src);
307
Jon Hunterb1538832012-09-28 11:43:30 -0500308 omap_hwmod_enable(oh);
Tony Lindgrenee17f112011-09-16 15:44:20 -0700309 __omap_dm_timer_init_regs(timer);
Jon Hunterbfd6d022012-09-27 12:47:43 -0500310
311 if (posted)
312 __omap_dm_timer_enable_posted(timer);
313
314 /* Check that the intended posted configuration matches the actual */
315 if (posted != timer->posted)
316 return -EINVAL;
Tony Lindgrenaa561882011-03-29 15:54:48 -0700317
318 timer->rate = clk_get_rate(timer->fclk);
Tony Lindgrenaa561882011-03-29 15:54:48 -0700319 timer->reserved = 1;
Paul Walmsley38698be2011-02-23 00:14:08 -0700320
Jon Hunterf88095b2012-11-09 17:07:39 -0600321 return r;
Tony Lindgrenaa561882011-03-29 15:54:48 -0700322}
Paul Walmsleyf2480762009-04-23 21:11:10 -0600323
Grygorii Strashko0b3e6fc2015-12-14 22:34:05 +0200324#if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
325void tick_broadcast(const struct cpumask *mask)
326{
327}
328#endif
329
Tony Lindgrenaa561882011-03-29 15:54:48 -0700330static void __init omap2_gp_clockevent_init(int gptimer_id,
Jon Hunter9725f442012-05-14 10:41:37 -0500331 const char *fck_source,
332 const char *property)
Tony Lindgrenaa561882011-03-29 15:54:48 -0700333{
334 int res;
Paul Walmsleyf2480762009-04-23 21:11:10 -0600335
Jon Hunter8f6924d2013-02-01 16:40:09 -0600336 clkev.id = gptimer_id;
Jon Hunterbfd6d022012-09-27 12:47:43 -0500337 clkev.errata = omap_dm_timer_get_errata();
338
339 /*
340 * For clock-event timers we never read the timer counter and
341 * so we are not impacted by errata i103 and i767. Therefore,
342 * we can safely ignore this errata for clock-event timers.
343 */
344 __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
345
Jon Hunter8f6924d2013-02-01 16:40:09 -0600346 res = omap_dm_timer_init_one(&clkev, fck_source, property,
Jon Huntere95ea432013-01-29 13:55:25 -0600347 &clockevent_gpt.name, OMAP_TIMER_POSTED);
Tony Lindgrenaa561882011-03-29 15:54:48 -0700348 BUG_ON(res);
Paul Walmsleyf2480762009-04-23 21:11:10 -0600349
Paul Walmsleya032d332012-08-03 09:21:10 -0600350 omap2_gp_timer_irq.dev_id = &clkev;
Tony Lindgrenaa561882011-03-29 15:54:48 -0700351 setup_irq(clkev.irq, &omap2_gp_timer_irq);
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800352
Tony Lindgrenee17f112011-09-16 15:44:20 -0700353 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
Tony Lindgrenaa561882011-03-29 15:54:48 -0700354
Santosh Shilimkar11d6ec22012-03-17 15:00:16 +0530355 clockevent_gpt.cpumask = cpu_possible_mask;
356 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
Shawn Guo838a2ae2013-01-12 11:50:05 +0000357 clockevents_config_and_register(&clockevent_gpt, clkev.rate,
358 3, /* Timer internal resynch latency */
359 0xffffffff);
Tony Lindgrenaa561882011-03-29 15:54:48 -0700360
Dave Gerlach12b28ba2017-03-28 20:57:55 -0500361 if (soc_is_am33xx() || soc_is_am43xx()) {
362 clockevent_gpt.suspend = omap_clkevt_idle;
363 clockevent_gpt.resume = omap_clkevt_unidle;
364
365 clockevent_gpt_hwmod =
366 omap_hwmod_lookup(clockevent_gpt.name);
367 }
368
Jon Huntere95ea432013-01-29 13:55:25 -0600369 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
370 clkev.rate);
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800371}
372
Paul Walmsleyf2480762009-04-23 21:11:10 -0600373/* Clocksource code */
Tony Lindgren3d05a3e2011-03-29 15:54:49 -0700374static struct omap_dm_timer clksrc;
Oussama Ghorbel332f1932014-04-14 17:49:30 +0100375static bool use_gptimer_clksrc __initdata;
Tony Lindgren3d05a3e2011-03-29 15:54:49 -0700376
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800377/*
378 * clocksource
379 */
Thomas Gleixnera5a1d1c2016-12-21 20:32:01 +0100380static u64 clocksource_read_cycles(struct clocksource *cs)
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800381{
Thomas Gleixnera5a1d1c2016-12-21 20:32:01 +0100382 return (u64)__omap_dm_timer_read_counter(&clksrc,
Jon Hunterbfd6d022012-09-27 12:47:43 -0500383 OMAP_TIMER_NONPOSTED);
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800384}
385
386static struct clocksource clocksource_gpt = {
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800387 .rating = 300,
388 .read = clocksource_read_cycles,
389 .mask = CLOCKSOURCE_MASK(32),
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800390 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
391};
392
Stephen Boydf99ba472013-11-15 15:26:18 -0800393static u64 notrace dmtimer_read_sched_clock(void)
Paul Walmsleycbc94382011-02-22 19:59:49 -0700394{
Tony Lindgren3d05a3e2011-03-29 15:54:49 -0700395 if (clksrc.reserved)
Jon Hunter971d0252012-09-27 11:49:45 -0500396 return __omap_dm_timer_read_counter(&clksrc,
Jon Hunterbfd6d022012-09-27 12:47:43 -0500397 OMAP_TIMER_NONPOSTED);
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800398
Marc Zyngier2f0778af2011-12-15 12:19:23 +0100399 return 0;
Tony Lindgren3d05a3e2011-03-29 15:54:49 -0700400}
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800401
Uwe Kleine-König31957602014-09-10 10:26:17 +0200402static const struct of_device_id omap_counter_match[] __initconst = {
Jon Hunter258e84a2012-11-15 13:09:03 -0600403 { .compatible = "ti,omap-counter32k", },
404 { }
405};
406
Tony Lindgren3d05a3e2011-03-29 15:54:49 -0700407/* Setup free-running counter for clocksource */
Jon Huntere0c3e272012-11-27 15:24:12 -0600408static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
Vaibhav Hiremath1fe97c82012-05-09 10:07:05 -0700409{
410 int ret;
Jon Hunter9883f7c2012-10-09 14:12:26 -0500411 struct device_node *np = NULL;
Vaibhav Hiremath1fe97c82012-05-09 10:07:05 -0700412 struct omap_hwmod *oh;
Vaibhav Hiremath1fe97c82012-05-09 10:07:05 -0700413 const char *oh_name = "counter_32k";
414
415 /*
Tony Lindgren8d39ff32017-05-31 15:51:30 -0700416 * See if the 32kHz counter is supported.
Jon Hunter9883f7c2012-10-09 14:12:26 -0500417 */
Tony Lindgren8d39ff32017-05-31 15:51:30 -0700418 np = omap_get_timer_dt(omap_counter_match, NULL);
419 if (!np)
420 return -ENODEV;
Jon Hunter9883f7c2012-10-09 14:12:26 -0500421
Tony Lindgren8d39ff32017-05-31 15:51:30 -0700422 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
423 if (!oh_name)
424 return -ENODEV;
Jon Hunter9883f7c2012-10-09 14:12:26 -0500425
426 /*
Vaibhav Hiremath1fe97c82012-05-09 10:07:05 -0700427 * First check hwmod data is available for sync32k counter
428 */
429 oh = omap_hwmod_lookup(oh_name);
430 if (!oh || oh->slaves_cnt == 0)
431 return -ENODEV;
432
433 omap_hwmod_setup_one(oh_name);
434
Vaibhav Hiremath1fe97c82012-05-09 10:07:05 -0700435 ret = omap_hwmod_enable(oh);
436 if (ret) {
437 pr_warn("%s: failed to enable counter_32k module (%d)\n",
438 __func__, ret);
439 return ret;
440 }
441
Vaibhav Hiremath1fe97c82012-05-09 10:07:05 -0700442 return ret;
443}
444
445static void __init omap2_gptimer_clocksource_init(int gptimer_id,
Jon Hunter2eb03932013-01-28 17:53:57 -0600446 const char *fck_source,
447 const char *property)
Tony Lindgren3d05a3e2011-03-29 15:54:49 -0700448{
449 int res;
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800450
Jon Hunter8f6924d2013-02-01 16:40:09 -0600451 clksrc.id = gptimer_id;
Jon Hunterbfd6d022012-09-27 12:47:43 -0500452 clksrc.errata = omap_dm_timer_get_errata();
453
Jon Hunter8f6924d2013-02-01 16:40:09 -0600454 res = omap_dm_timer_init_one(&clksrc, fck_source, property,
Jon Huntere95ea432013-01-29 13:55:25 -0600455 &clocksource_gpt.name,
Jon Hunterbfd6d022012-09-27 12:47:43 -0500456 OMAP_TIMER_NONPOSTED);
Tony Lindgren3d05a3e2011-03-29 15:54:49 -0700457 BUG_ON(res);
Paul Walmsleycbc94382011-02-22 19:59:49 -0700458
Tony Lindgrenee17f112011-09-16 15:44:20 -0700459 __omap_dm_timer_load_start(&clksrc,
Jon Hunter971d0252012-09-27 11:49:45 -0500460 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
Jon Hunterbfd6d022012-09-27 12:47:43 -0500461 OMAP_TIMER_NONPOSTED);
Stephen Boydf99ba472013-11-15 15:26:18 -0800462 sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
Tony Lindgren3d05a3e2011-03-29 15:54:49 -0700463
464 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
465 pr_err("Could not register clocksource %s\n",
466 clocksource_gpt.name);
Vaibhav Hiremath1fe97c82012-05-09 10:07:05 -0700467 else
Jon Huntere95ea432013-01-29 13:55:25 -0600468 pr_info("OMAP clocksource: %s at %lu Hz\n",
469 clocksource_gpt.name, clksrc.rate);
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800470}
Vaibhav Hiremath1fe97c82012-05-09 10:07:05 -0700471
Felipe Balbi3afbb9a2015-09-29 13:12:55 -0500472static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
473 const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
474 const char *clksrc_prop, bool gptimer)
475{
476 omap_clk_init();
477 omap_dmtimer_init();
478 omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
479
480 /* Enable the use of clocksource="gp_timer" kernel parameter */
481 if (use_gptimer_clksrc || gptimer)
482 omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
483 clksrc_prop);
484 else
485 omap2_sync32k_clocksource_init();
486}
487
Felipe Balbi6f82e252015-09-29 13:26:45 -0500488void __init omap_init_time(void)
Felipe Balbi3afbb9a2015-09-29 13:12:55 -0500489{
490 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
491 2, "timer_sys_ck", NULL, false);
Felipe Balbi9c46ffc2015-09-29 13:15:02 -0500492
Daniel Lezcanoba5d08c2017-05-26 17:40:46 +0200493 timer_probe();
Felipe Balbi3afbb9a2015-09-29 13:12:55 -0500494}
495
496#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
497void __init omap3_secure_sync32k_timer_init(void)
498{
499 __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
500 2, "timer_sys_ck", NULL, false);
Tero Kristo970f9092016-06-16 15:25:18 +0300501
Daniel Lezcanoba5d08c2017-05-26 17:40:46 +0200502 timer_probe();
Felipe Balbi3afbb9a2015-09-29 13:12:55 -0500503}
504#endif /* CONFIG_ARCH_OMAP3 */
505
Grygorii Strashkof86a2c82016-12-05 09:27:44 +0530506#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
507 defined(CONFIG_SOC_AM43XX)
Felipe Balbi3afbb9a2015-09-29 13:12:55 -0500508void __init omap3_gptimer_timer_init(void)
509{
510 __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
511 1, "timer_sys_ck", "ti,timer-alwon", true);
Grygorii Strashkof86a2c82016-12-05 09:27:44 +0530512 if (of_have_populated_dt())
Daniel Lezcanoba5d08c2017-05-26 17:40:46 +0200513 timer_probe();
Felipe Balbi3afbb9a2015-09-29 13:12:55 -0500514}
515#endif
516
517#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
Grygorii Strashkof86a2c82016-12-05 09:27:44 +0530518 defined(CONFIG_SOC_DRA7XX)
Felipe Balbi3afbb9a2015-09-29 13:12:55 -0500519static void __init omap4_sync32k_timer_init(void)
520{
521 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
522 2, "sys_clkin_ck", NULL, false);
523}
524
525void __init omap4_local_timer_init(void)
526{
527 omap4_sync32k_timer_init();
Daniel Lezcanoba5d08c2017-05-26 17:40:46 +0200528 timer_probe();
Felipe Balbi3afbb9a2015-09-29 13:12:55 -0500529}
530#endif
531
532#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
533
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530534/*
535 * The realtime counter also called master counter, is a free-running
536 * counter, which is related to real time. It produces the count used
537 * by the CPU local timer peripherals in the MPU cluster. The timer counts
538 * at a rate of 6.144 MHz. Because the device operates on different clocks
539 * in different power modes, the master counter shifts operation between
540 * clocks, adjusting the increment per clock in hardware accordingly to
541 * maintain a constant count rate.
542 */
543static void __init realtime_counter_init(void)
544{
Felipe Balbi3afbb9a2015-09-29 13:12:55 -0500545#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530546 void __iomem *base;
547 static struct clk *sys_clk;
548 unsigned long rate;
Lennart Sorensenafc9d592015-01-05 15:45:45 -0800549 unsigned int reg;
550 unsigned long long num, den;
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530551
552 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
553 if (!base) {
554 pr_err("%s: ioremap failed\n", __func__);
555 return;
556 }
Tony Lindgren7f585bb2013-04-03 10:47:59 -0700557 sys_clk = clk_get(NULL, "sys_clkin");
Wei Yongjun533b2982012-10-08 15:01:41 -0700558 if (IS_ERR(sys_clk)) {
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530559 pr_err("%s: failed to get system clock handle\n", __func__);
560 iounmap(base);
561 return;
562 }
563
564 rate = clk_get_rate(sys_clk);
Chen Hui5f9aeda2022-11-08 22:19:17 +0800565 clk_put(sys_clk);
Lennart Sorensenafc9d592015-01-05 15:45:45 -0800566
567 if (soc_is_dra7xx()) {
568 /*
569 * Errata i856 says the 32.768KHz crystal does not start at
570 * power on, so the CPU falls back to an emulated 32KHz clock
571 * based on sysclk / 610 instead. This causes the master counter
572 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
573 * (OR sysclk * 75 / 244)
574 *
575 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
576 * Of course any board built without a populated 32.768KHz
577 * crystal would also need this fix even if the CPU is fixed
578 * later.
579 *
580 * Either case can be detected by using the two speedselect bits
581 * If they are not 0, then the 32.768KHz clock driving the
582 * coarse counter that corrects the fine counter every time it
583 * ticks is actually rate/610 rather than 32.768KHz and we
584 * should compensate to avoid the 570ppm (at 20MHz, much worse
585 * at other rates) too fast system time.
586 */
587 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
588 if (reg & DRA7_SPEEDSELECT_MASK) {
589 num = 75;
590 den = 244;
591 goto sysclk1_based;
592 }
593 }
594
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530595 /* Numerator/denumerator values refer TRM Realtime Counter section */
596 switch (rate) {
Lennart Sorensen572b24e2015-01-05 15:45:45 -0800597 case 12000000:
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530598 num = 64;
599 den = 125;
600 break;
Lennart Sorensen572b24e2015-01-05 15:45:45 -0800601 case 13000000:
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530602 num = 768;
603 den = 1625;
604 break;
605 case 19200000:
606 num = 8;
607 den = 25;
608 break;
Sricharan R38a19812013-09-18 16:50:11 +0530609 case 20000000:
610 num = 192;
611 den = 625;
612 break;
Lennart Sorensen572b24e2015-01-05 15:45:45 -0800613 case 26000000:
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530614 num = 384;
615 den = 1625;
616 break;
Lennart Sorensen572b24e2015-01-05 15:45:45 -0800617 case 27000000:
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530618 num = 256;
619 den = 1125;
620 break;
621 case 38400000:
622 default:
623 /* Program it for 38.4 MHz */
624 num = 4;
625 den = 25;
626 break;
627 }
628
Lennart Sorensenafc9d592015-01-05 15:45:45 -0800629sysclk1_based:
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530630 /* Program numerator and denumerator registers */
Victor Kamenskyedfaf052014-04-15 20:37:46 +0300631 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530632 NUMERATOR_DENUMERATOR_MASK;
633 reg |= num;
Victor Kamenskyedfaf052014-04-15 20:37:46 +0300634 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530635
Victor Kamenskyedfaf052014-04-15 20:37:46 +0300636 reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530637 NUMERATOR_DENUMERATOR_MASK;
638 reg |= den;
Victor Kamenskyedfaf052014-04-15 20:37:46 +0300639 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530640
Lennart Sorensenafc9d592015-01-05 15:45:45 -0800641 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
R Sricharan5523e402013-10-10 13:13:48 +0530642 set_cntfreq();
643
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530644 iounmap(base);
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530645#endif
Tony Lindgrene74984e2011-03-29 15:54:48 -0700646}
647
Stephen Warren6bb27d72012-11-08 12:40:59 -0700648void __init omap5_realtime_timer_init(void)
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530649{
Jon Hunter00ea4d52013-01-11 20:23:09 -0600650 omap4_sync32k_timer_init();
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530651 realtime_counter_init();
Santosh Shilimkar3c7c5da2012-08-13 14:39:03 +0530652
Daniel Lezcanoba5d08c2017-05-26 17:40:46 +0200653 timer_probe();
Santosh Shilimkarfa6d79d2012-08-13 14:24:24 +0530654}
Simon Barth0b8214f2013-10-08 10:50:33 +0200655#endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
R Sricharan37b32802012-05-02 13:07:12 +0530656
Tarun Kanti DebBarmac345c8b2011-09-20 17:00:18 +0530657/**
Vaibhav Hiremath1fe97c82012-05-09 10:07:05 -0700658 * omap2_override_clocksource - clocksource override with user configuration
659 *
660 * Allows user to override default clocksource, using kernel parameter
661 * clocksource="gp_timer" (For all OMAP2PLUS architectures)
662 *
663 * Note that, here we are using same standard kernel parameter "clocksource=",
664 * and not introducing any OMAP specific interface.
665 */
666static int __init omap2_override_clocksource(char *str)
667{
668 if (!str)
669 return 0;
670 /*
671 * For OMAP architecture, we only have two options
672 * - sync_32k (default)
673 * - gp_timer (sys_clk based)
674 */
675 if (!strcmp(str, "gp_timer"))
676 use_gptimer_clksrc = true;
677
678 return 0;
679}
680early_param("clocksource", omap2_override_clocksource);