Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 1 | /* |
Tony Lindgren | 0f622e8 | 2011-03-29 15:54:50 -0700 | [diff] [blame] | 2 | * linux/arch/arm/mach-omap2/timer.c |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 3 | * |
| 4 | * OMAP2 GP timer support. |
| 5 | * |
Paul Walmsley | f248076 | 2009-04-23 21:11:10 -0600 | [diff] [blame] | 6 | * Copyright (C) 2009 Nokia Corporation |
| 7 | * |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 8 | * Update to use new clocksource/clockevent layers |
| 9 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> |
| 10 | * Copyright (C) 2007 MontaVista Software, Inc. |
| 11 | * |
| 12 | * Original driver: |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 13 | * Copyright (C) 2005 Nokia Corporation |
| 14 | * Author: Paul Mundt <paul.mundt@nokia.com> |
Jan Engelhardt | 96de0e2 | 2007-10-19 23:21:04 +0200 | [diff] [blame] | 15 | * Juha Yrjölä <juha.yrjola@nokia.com> |
Timo Teras | 77900a2 | 2006-06-26 16:16:12 -0700 | [diff] [blame] | 16 | * OMAP Dual-mode timer framework support by Timo Teras |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 17 | * |
| 18 | * Some parts based off of TI's 24xx code: |
| 19 | * |
Santosh Shilimkar | 4416907 | 2009-05-28 14:16:04 -0700 | [diff] [blame] | 20 | * Copyright (C) 2004-2009 Texas Instruments, Inc. |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 21 | * |
| 22 | * Roughly modelled after the OMAP1 MPU timer code. |
Santosh Shilimkar | 4416907 | 2009-05-28 14:16:04 -0700 | [diff] [blame] | 23 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 24 | * |
| 25 | * This file is subject to the terms and conditions of the GNU General Public |
| 26 | * License. See the file "COPYING" in the main directory of this archive |
| 27 | * for more details. |
| 28 | */ |
| 29 | #include <linux/init.h> |
| 30 | #include <linux/time.h> |
| 31 | #include <linux/interrupt.h> |
| 32 | #include <linux/err.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 33 | #include <linux/clk.h> |
Timo Teras | 77900a2 | 2006-06-26 16:16:12 -0700 | [diff] [blame] | 34 | #include <linux/delay.h> |
Dirk Behme | e668729 | 2006-12-06 17:14:00 -0800 | [diff] [blame] | 35 | #include <linux/irq.h> |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 36 | #include <linux/clocksource.h> |
| 37 | #include <linux/clockchips.h> |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 38 | #include <linux/slab.h> |
Santosh Shilimkar | eed0de2 | 2012-07-04 18:32:32 +0530 | [diff] [blame] | 39 | #include <linux/of.h> |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 40 | #include <linux/of_address.h> |
| 41 | #include <linux/of_irq.h> |
Jon Hunter | 40fc3bb | 2012-09-28 11:34:49 -0500 | [diff] [blame] | 42 | #include <linux/platform_device.h> |
| 43 | #include <linux/platform_data/dmtimer-omap.h> |
Stephen Boyd | 38ff87f | 2013-06-01 23:39:40 -0700 | [diff] [blame] | 44 | #include <linux/sched_clock.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 45 | |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 46 | #include <asm/mach/time.h> |
Marc Zyngier | a45c983 | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 47 | #include <asm/smp_twd.h> |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 48 | |
Tony Lindgren | 2a296c8 | 2012-10-02 17:41:35 -0700 | [diff] [blame] | 49 | #include "omap_hwmod.h" |
Tony Lindgren | 25c7d49 | 2012-10-02 17:25:48 -0700 | [diff] [blame] | 50 | #include "omap_device.h" |
Tony Lindgren | 5c2e885 | 2012-10-29 16:45:47 -0700 | [diff] [blame] | 51 | #include <plat/counter-32k.h> |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 52 | #include <plat/dmtimer.h> |
Tony Lindgren | 1d5aef4 | 2012-10-03 16:36:40 -0700 | [diff] [blame] | 53 | #include "omap-pm.h" |
Tarun Kanti DebBarma | b481113 | 2011-09-20 17:00:24 +0530 | [diff] [blame] | 54 | |
Tony Lindgren | dbc0416 | 2012-08-31 10:59:07 -0700 | [diff] [blame] | 55 | #include "soc.h" |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 56 | #include "common.h" |
Lennart Sorensen | afc9d59 | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 57 | #include "control.h" |
Tarun Kanti DebBarma | b481113 | 2011-09-20 17:00:24 +0530 | [diff] [blame] | 58 | #include "powerdomain.h" |
R Sricharan | 5523e40 | 2013-10-10 13:13:48 +0530 | [diff] [blame] | 59 | #include "omap-secure.h" |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 60 | |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 61 | #define REALTIME_COUNTER_BASE 0x48243200 |
| 62 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 |
| 63 | #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 |
| 64 | #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 |
| 65 | |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 66 | /* Clockevent code */ |
| 67 | |
| 68 | static struct omap_dm_timer clkev; |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 69 | static struct clock_event_device clockevent_gpt; |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 70 | |
Dave Gerlach | 12b28ba | 2017-03-28 20:57:55 -0500 | [diff] [blame] | 71 | /* Clockevent hwmod for am335x and am437x suspend */ |
| 72 | static struct omap_hwmod *clockevent_gpt_hwmod; |
| 73 | |
Tony Lindgren | d5da94b | 2013-10-11 17:28:04 -0700 | [diff] [blame] | 74 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
R Sricharan | 5523e40 | 2013-10-10 13:13:48 +0530 | [diff] [blame] | 75 | static unsigned long arch_timer_freq; |
| 76 | |
| 77 | void set_cntfreq(void) |
| 78 | { |
| 79 | omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); |
| 80 | } |
Tony Lindgren | d5da94b | 2013-10-11 17:28:04 -0700 | [diff] [blame] | 81 | #endif |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 82 | |
Linus Torvalds | 0cd61b6 | 2006-10-06 10:53:39 -0700 | [diff] [blame] | 83 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 84 | { |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 85 | struct clock_event_device *evt = &clockevent_gpt; |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 86 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 87 | __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 88 | |
| 89 | evt->event_handler(evt); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 90 | return IRQ_HANDLED; |
| 91 | } |
| 92 | |
| 93 | static struct irqaction omap2_gp_timer_irq = { |
Vaibhav Hiremath | f36921b | 2012-05-09 10:07:05 -0700 | [diff] [blame] | 94 | .name = "gp_timer", |
Michael Opdenacker | fe806d0 | 2013-09-07 09:19:25 +0200 | [diff] [blame] | 95 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 96 | .handler = omap2_gp_timer_interrupt, |
| 97 | }; |
| 98 | |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 99 | static int omap2_gp_timer_set_next_event(unsigned long cycles, |
| 100 | struct clock_event_device *evt) |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 101 | { |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 102 | __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, |
Jon Hunter | 971d025 | 2012-09-27 11:49:45 -0500 | [diff] [blame] | 103 | 0xffffffff - cycles, OMAP_TIMER_POSTED); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 104 | |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 105 | return 0; |
| 106 | } |
| 107 | |
Viresh Kumar | 7436461 | 2015-02-27 13:39:52 +0530 | [diff] [blame] | 108 | static int omap2_gp_timer_shutdown(struct clock_event_device *evt) |
| 109 | { |
| 110 | __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | static int omap2_gp_timer_set_periodic(struct clock_event_device *evt) |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 115 | { |
| 116 | u32 period; |
| 117 | |
Jon Hunter | 971d025 | 2012-09-27 11:49:45 -0500 | [diff] [blame] | 118 | __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 119 | |
Viresh Kumar | 7436461 | 2015-02-27 13:39:52 +0530 | [diff] [blame] | 120 | period = clkev.rate / HZ; |
| 121 | period -= 1; |
| 122 | /* Looks like we need to first set the load value separately */ |
| 123 | __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period, |
| 124 | OMAP_TIMER_POSTED); |
| 125 | __omap_dm_timer_load_start(&clkev, |
| 126 | OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, |
| 127 | 0xffffffff - period, OMAP_TIMER_POSTED); |
| 128 | return 0; |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 129 | } |
| 130 | |
Dave Gerlach | 12b28ba | 2017-03-28 20:57:55 -0500 | [diff] [blame] | 131 | static void omap_clkevt_idle(struct clock_event_device *unused) |
| 132 | { |
| 133 | if (!clockevent_gpt_hwmod) |
| 134 | return; |
| 135 | |
| 136 | omap_hwmod_idle(clockevent_gpt_hwmod); |
| 137 | } |
| 138 | |
| 139 | static void omap_clkevt_unidle(struct clock_event_device *unused) |
| 140 | { |
| 141 | if (!clockevent_gpt_hwmod) |
| 142 | return; |
| 143 | |
| 144 | omap_hwmod_enable(clockevent_gpt_hwmod); |
| 145 | __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); |
| 146 | } |
| 147 | |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 148 | static struct clock_event_device clockevent_gpt = { |
Viresh Kumar | 7436461 | 2015-02-27 13:39:52 +0530 | [diff] [blame] | 149 | .features = CLOCK_EVT_FEAT_PERIODIC | |
| 150 | CLOCK_EVT_FEAT_ONESHOT, |
| 151 | .rating = 300, |
| 152 | .set_next_event = omap2_gp_timer_set_next_event, |
| 153 | .set_state_shutdown = omap2_gp_timer_shutdown, |
| 154 | .set_state_periodic = omap2_gp_timer_set_periodic, |
| 155 | .set_state_oneshot = omap2_gp_timer_shutdown, |
| 156 | .tick_resume = omap2_gp_timer_shutdown, |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 157 | }; |
| 158 | |
Uwe Kleine-König | 3195760 | 2014-09-10 10:26:17 +0200 | [diff] [blame] | 159 | static const struct of_device_id omap_timer_match[] __initconst = { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 160 | { .compatible = "ti,omap2420-timer", }, |
| 161 | { .compatible = "ti,omap3430-timer", }, |
| 162 | { .compatible = "ti,omap4430-timer", }, |
| 163 | { .compatible = "ti,omap5430-timer", }, |
Tony Lindgren | 132754e | 2015-01-14 17:37:16 -0800 | [diff] [blame] | 164 | { .compatible = "ti,dm814-timer", }, |
| 165 | { .compatible = "ti,dm816-timer", }, |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 166 | { .compatible = "ti,am335x-timer", }, |
| 167 | { .compatible = "ti,am335x-timer-1ms", }, |
Jon Hunter | ad24bde | 2012-06-20 15:55:24 -0500 | [diff] [blame] | 168 | { } |
| 169 | }; |
| 170 | |
| 171 | /** |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 172 | * omap_get_timer_dt - get a timer using device-tree |
| 173 | * @match - device-tree match structure for matching a device type |
| 174 | * @property - optional timer property to match |
| 175 | * |
| 176 | * Helper function to get a timer during early boot using device-tree for use |
| 177 | * as kernel system timer. Optionally, the property argument can be used to |
| 178 | * select a timer with a specific property. Once a timer is found then mark |
| 179 | * the timer node in device-tree as disabled, to prevent the kernel from |
| 180 | * registering this timer as a platform device and so no one else can use it. |
| 181 | */ |
Uwe Kleine-König | 3195760 | 2014-09-10 10:26:17 +0200 | [diff] [blame] | 182 | static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match, |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 183 | const char *property) |
| 184 | { |
| 185 | struct device_node *np; |
| 186 | |
| 187 | for_each_matching_node(np, match) { |
Pantelis Antoniou | 034bf09 | 2013-01-08 15:31:42 +0200 | [diff] [blame] | 188 | if (!of_device_is_available(np)) |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 189 | continue; |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 190 | |
Pantelis Antoniou | 034bf09 | 2013-01-08 15:31:42 +0200 | [diff] [blame] | 191 | if (property && !of_get_property(np, property, NULL)) |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 192 | continue; |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 193 | |
Jon Hunter | 2eb0393 | 2013-01-28 17:53:57 -0600 | [diff] [blame] | 194 | if (!property && (of_get_property(np, "ti,timer-alwon", NULL) || |
| 195 | of_get_property(np, "ti,timer-dsp", NULL) || |
| 196 | of_get_property(np, "ti,timer-pwm", NULL) || |
| 197 | of_get_property(np, "ti,timer-secure", NULL))) |
| 198 | continue; |
| 199 | |
Qi Hou | 7ffe100 | 2018-01-11 12:54:43 +0800 | [diff] [blame] | 200 | if (!of_device_is_compatible(np, "ti,omap-counter32k")) { |
| 201 | struct property *prop; |
| 202 | |
| 203 | prop = kzalloc(sizeof(*prop), GFP_KERNEL); |
| 204 | if (!prop) |
| 205 | return NULL; |
| 206 | prop->name = "status"; |
| 207 | prop->value = "disabled"; |
| 208 | prop->length = strlen(prop->value); |
| 209 | of_add_property(np, prop); |
| 210 | } |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 211 | return np; |
| 212 | } |
| 213 | |
| 214 | return NULL; |
| 215 | } |
| 216 | |
| 217 | /** |
Jon Hunter | ad24bde | 2012-06-20 15:55:24 -0500 | [diff] [blame] | 218 | * omap_dmtimer_init - initialisation function when device tree is used |
| 219 | * |
Suman Anna | ed5a4c6 | 2015-10-05 18:28:22 -0500 | [diff] [blame] | 220 | * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure" |
| 221 | * cannot be used by the kernel as they are reserved. Therefore, to prevent the |
Jon Hunter | ad24bde | 2012-06-20 15:55:24 -0500 | [diff] [blame] | 222 | * kernel registering these devices remove them dynamically from the device |
| 223 | * tree on boot. |
| 224 | */ |
Vaibhav Hiremath | bf85f20 | 2012-11-28 15:56:41 -0600 | [diff] [blame] | 225 | static void __init omap_dmtimer_init(void) |
Jon Hunter | ad24bde | 2012-06-20 15:55:24 -0500 | [diff] [blame] | 226 | { |
| 227 | struct device_node *np; |
| 228 | |
Suman Anna | ed5a4c6 | 2015-10-05 18:28:22 -0500 | [diff] [blame] | 229 | if (!cpu_is_omap34xx() && !soc_is_dra7xx()) |
Jon Hunter | ad24bde | 2012-06-20 15:55:24 -0500 | [diff] [blame] | 230 | return; |
| 231 | |
| 232 | /* If we are a secure device, remove any secure timer nodes */ |
| 233 | if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 234 | np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); |
Markus Elfring | 9a0cb98 | 2015-06-30 14:00:16 +0200 | [diff] [blame] | 235 | of_node_put(np); |
Jon Hunter | ad24bde | 2012-06-20 15:55:24 -0500 | [diff] [blame] | 236 | } |
| 237 | } |
| 238 | |
Jon Hunter | bfd6d02 | 2012-09-27 12:47:43 -0500 | [diff] [blame] | 239 | /** |
| 240 | * omap_dm_timer_get_errata - get errata flags for a timer |
| 241 | * |
| 242 | * Get the timer errata flags that are specific to the OMAP device being used. |
| 243 | */ |
Vaibhav Hiremath | bf85f20 | 2012-11-28 15:56:41 -0600 | [diff] [blame] | 244 | static u32 __init omap_dm_timer_get_errata(void) |
Jon Hunter | bfd6d02 | 2012-09-27 12:47:43 -0500 | [diff] [blame] | 245 | { |
| 246 | if (cpu_is_omap24xx()) |
| 247 | return 0; |
| 248 | |
| 249 | return OMAP_TIMER_ERRATA_I103_I767; |
| 250 | } |
| 251 | |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 252 | static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, |
Jon Hunter | e95ea43 | 2013-01-29 13:55:25 -0600 | [diff] [blame] | 253 | const char *fck_source, |
| 254 | const char *property, |
| 255 | const char **timer_name, |
| 256 | int posted) |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 257 | { |
Afzal Mohammed | 37bd6ca | 2013-05-28 11:54:48 +0530 | [diff] [blame] | 258 | const char *oh_name = NULL; |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 259 | struct device_node *np; |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 260 | struct omap_hwmod *oh; |
Jon Hunter | a7990a1 | 2013-03-12 17:17:57 -0500 | [diff] [blame] | 261 | struct clk *src; |
Jon Hunter | f88095b | 2012-11-09 17:07:39 -0600 | [diff] [blame] | 262 | int r = 0; |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 263 | |
Tony Lindgren | 8d39ff3 | 2017-05-31 15:51:30 -0700 | [diff] [blame] | 264 | np = omap_get_timer_dt(omap_timer_match, property); |
| 265 | if (!np) |
| 266 | return -ENODEV; |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 267 | |
Tony Lindgren | 8d39ff3 | 2017-05-31 15:51:30 -0700 | [diff] [blame] | 268 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); |
| 269 | if (!oh_name) |
| 270 | return -ENODEV; |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 271 | |
Tony Lindgren | 8d39ff3 | 2017-05-31 15:51:30 -0700 | [diff] [blame] | 272 | timer->irq = irq_of_parse_and_map(np, 0); |
| 273 | if (!timer->irq) |
| 274 | return -ENXIO; |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 275 | |
Tony Lindgren | 8d39ff3 | 2017-05-31 15:51:30 -0700 | [diff] [blame] | 276 | timer->io_base = of_iomap(np, 0); |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 277 | |
Tony Lindgren | 67d0047 | 2017-06-12 03:27:30 -0700 | [diff] [blame] | 278 | timer->fclk = of_clk_get_by_name(np, "fck"); |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 279 | |
Tony Lindgren | 8d39ff3 | 2017-05-31 15:51:30 -0700 | [diff] [blame] | 280 | of_node_put(np); |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 281 | |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 282 | oh = omap_hwmod_lookup(oh_name); |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 283 | if (!oh) |
| 284 | return -ENODEV; |
Paul Walmsley | f248076 | 2009-04-23 21:11:10 -0600 | [diff] [blame] | 285 | |
Jon Hunter | e95ea43 | 2013-01-29 13:55:25 -0600 | [diff] [blame] | 286 | *timer_name = oh->name; |
| 287 | |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 288 | if (!timer->io_base) |
| 289 | return -ENXIO; |
| 290 | |
Tero Kristo | e98580e | 2016-06-30 16:15:01 +0300 | [diff] [blame] | 291 | omap_hwmod_setup_one(oh_name); |
| 292 | |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 293 | /* After the dmtimer is using hwmod these clocks won't be needed */ |
Tero Kristo | 138f7ca | 2017-05-31 17:59:58 +0300 | [diff] [blame] | 294 | if (IS_ERR_OR_NULL(timer->fclk)) |
| 295 | timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 296 | if (IS_ERR(timer->fclk)) |
Jon Hunter | a7990a1 | 2013-03-12 17:17:57 -0500 | [diff] [blame] | 297 | return PTR_ERR(timer->fclk); |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 298 | |
Jon Hunter | a7990a1 | 2013-03-12 17:17:57 -0500 | [diff] [blame] | 299 | src = clk_get(NULL, fck_source); |
| 300 | if (IS_ERR(src)) |
| 301 | return PTR_ERR(src); |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 302 | |
Tony Lindgren | 874b300 | 2015-09-01 13:59:25 -0700 | [diff] [blame] | 303 | WARN(clk_set_parent(timer->fclk, src) < 0, |
| 304 | "Cannot set timer parent clock, no PLL clock driver?"); |
Jon Hunter | b153883 | 2012-09-28 11:43:30 -0500 | [diff] [blame] | 305 | |
Jon Hunter | a7990a1 | 2013-03-12 17:17:57 -0500 | [diff] [blame] | 306 | clk_put(src); |
| 307 | |
Jon Hunter | b153883 | 2012-09-28 11:43:30 -0500 | [diff] [blame] | 308 | omap_hwmod_enable(oh); |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 309 | __omap_dm_timer_init_regs(timer); |
Jon Hunter | bfd6d02 | 2012-09-27 12:47:43 -0500 | [diff] [blame] | 310 | |
| 311 | if (posted) |
| 312 | __omap_dm_timer_enable_posted(timer); |
| 313 | |
| 314 | /* Check that the intended posted configuration matches the actual */ |
| 315 | if (posted != timer->posted) |
| 316 | return -EINVAL; |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 317 | |
| 318 | timer->rate = clk_get_rate(timer->fclk); |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 319 | timer->reserved = 1; |
Paul Walmsley | 38698be | 2011-02-23 00:14:08 -0700 | [diff] [blame] | 320 | |
Jon Hunter | f88095b | 2012-11-09 17:07:39 -0600 | [diff] [blame] | 321 | return r; |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 322 | } |
Paul Walmsley | f248076 | 2009-04-23 21:11:10 -0600 | [diff] [blame] | 323 | |
Grygorii Strashko | 0b3e6fc | 2015-12-14 22:34:05 +0200 | [diff] [blame] | 324 | #if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) |
| 325 | void tick_broadcast(const struct cpumask *mask) |
| 326 | { |
| 327 | } |
| 328 | #endif |
| 329 | |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 330 | static void __init omap2_gp_clockevent_init(int gptimer_id, |
Jon Hunter | 9725f44 | 2012-05-14 10:41:37 -0500 | [diff] [blame] | 331 | const char *fck_source, |
| 332 | const char *property) |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 333 | { |
| 334 | int res; |
Paul Walmsley | f248076 | 2009-04-23 21:11:10 -0600 | [diff] [blame] | 335 | |
Jon Hunter | 8f6924d | 2013-02-01 16:40:09 -0600 | [diff] [blame] | 336 | clkev.id = gptimer_id; |
Jon Hunter | bfd6d02 | 2012-09-27 12:47:43 -0500 | [diff] [blame] | 337 | clkev.errata = omap_dm_timer_get_errata(); |
| 338 | |
| 339 | /* |
| 340 | * For clock-event timers we never read the timer counter and |
| 341 | * so we are not impacted by errata i103 and i767. Therefore, |
| 342 | * we can safely ignore this errata for clock-event timers. |
| 343 | */ |
| 344 | __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); |
| 345 | |
Jon Hunter | 8f6924d | 2013-02-01 16:40:09 -0600 | [diff] [blame] | 346 | res = omap_dm_timer_init_one(&clkev, fck_source, property, |
Jon Hunter | e95ea43 | 2013-01-29 13:55:25 -0600 | [diff] [blame] | 347 | &clockevent_gpt.name, OMAP_TIMER_POSTED); |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 348 | BUG_ON(res); |
Paul Walmsley | f248076 | 2009-04-23 21:11:10 -0600 | [diff] [blame] | 349 | |
Paul Walmsley | a032d33 | 2012-08-03 09:21:10 -0600 | [diff] [blame] | 350 | omap2_gp_timer_irq.dev_id = &clkev; |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 351 | setup_irq(clkev.irq, &omap2_gp_timer_irq); |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 352 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 353 | __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 354 | |
Santosh Shilimkar | 11d6ec2 | 2012-03-17 15:00:16 +0530 | [diff] [blame] | 355 | clockevent_gpt.cpumask = cpu_possible_mask; |
| 356 | clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); |
Shawn Guo | 838a2ae | 2013-01-12 11:50:05 +0000 | [diff] [blame] | 357 | clockevents_config_and_register(&clockevent_gpt, clkev.rate, |
| 358 | 3, /* Timer internal resynch latency */ |
| 359 | 0xffffffff); |
Tony Lindgren | aa56188 | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 360 | |
Dave Gerlach | 12b28ba | 2017-03-28 20:57:55 -0500 | [diff] [blame] | 361 | if (soc_is_am33xx() || soc_is_am43xx()) { |
| 362 | clockevent_gpt.suspend = omap_clkevt_idle; |
| 363 | clockevent_gpt.resume = omap_clkevt_unidle; |
| 364 | |
| 365 | clockevent_gpt_hwmod = |
| 366 | omap_hwmod_lookup(clockevent_gpt.name); |
| 367 | } |
| 368 | |
Jon Hunter | e95ea43 | 2013-01-29 13:55:25 -0600 | [diff] [blame] | 369 | pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, |
| 370 | clkev.rate); |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 371 | } |
| 372 | |
Paul Walmsley | f248076 | 2009-04-23 21:11:10 -0600 | [diff] [blame] | 373 | /* Clocksource code */ |
Tony Lindgren | 3d05a3e | 2011-03-29 15:54:49 -0700 | [diff] [blame] | 374 | static struct omap_dm_timer clksrc; |
Oussama Ghorbel | 332f193 | 2014-04-14 17:49:30 +0100 | [diff] [blame] | 375 | static bool use_gptimer_clksrc __initdata; |
Tony Lindgren | 3d05a3e | 2011-03-29 15:54:49 -0700 | [diff] [blame] | 376 | |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 377 | /* |
| 378 | * clocksource |
| 379 | */ |
Thomas Gleixner | a5a1d1c | 2016-12-21 20:32:01 +0100 | [diff] [blame] | 380 | static u64 clocksource_read_cycles(struct clocksource *cs) |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 381 | { |
Thomas Gleixner | a5a1d1c | 2016-12-21 20:32:01 +0100 | [diff] [blame] | 382 | return (u64)__omap_dm_timer_read_counter(&clksrc, |
Jon Hunter | bfd6d02 | 2012-09-27 12:47:43 -0500 | [diff] [blame] | 383 | OMAP_TIMER_NONPOSTED); |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 384 | } |
| 385 | |
| 386 | static struct clocksource clocksource_gpt = { |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 387 | .rating = 300, |
| 388 | .read = clocksource_read_cycles, |
| 389 | .mask = CLOCKSOURCE_MASK(32), |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 390 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 391 | }; |
| 392 | |
Stephen Boyd | f99ba47 | 2013-11-15 15:26:18 -0800 | [diff] [blame] | 393 | static u64 notrace dmtimer_read_sched_clock(void) |
Paul Walmsley | cbc9438 | 2011-02-22 19:59:49 -0700 | [diff] [blame] | 394 | { |
Tony Lindgren | 3d05a3e | 2011-03-29 15:54:49 -0700 | [diff] [blame] | 395 | if (clksrc.reserved) |
Jon Hunter | 971d025 | 2012-09-27 11:49:45 -0500 | [diff] [blame] | 396 | return __omap_dm_timer_read_counter(&clksrc, |
Jon Hunter | bfd6d02 | 2012-09-27 12:47:43 -0500 | [diff] [blame] | 397 | OMAP_TIMER_NONPOSTED); |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 398 | |
Marc Zyngier | 2f0778af | 2011-12-15 12:19:23 +0100 | [diff] [blame] | 399 | return 0; |
Tony Lindgren | 3d05a3e | 2011-03-29 15:54:49 -0700 | [diff] [blame] | 400 | } |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 401 | |
Uwe Kleine-König | 3195760 | 2014-09-10 10:26:17 +0200 | [diff] [blame] | 402 | static const struct of_device_id omap_counter_match[] __initconst = { |
Jon Hunter | 258e84a | 2012-11-15 13:09:03 -0600 | [diff] [blame] | 403 | { .compatible = "ti,omap-counter32k", }, |
| 404 | { } |
| 405 | }; |
| 406 | |
Tony Lindgren | 3d05a3e | 2011-03-29 15:54:49 -0700 | [diff] [blame] | 407 | /* Setup free-running counter for clocksource */ |
Jon Hunter | e0c3e27 | 2012-11-27 15:24:12 -0600 | [diff] [blame] | 408 | static int __init __maybe_unused omap2_sync32k_clocksource_init(void) |
Vaibhav Hiremath | 1fe97c8 | 2012-05-09 10:07:05 -0700 | [diff] [blame] | 409 | { |
| 410 | int ret; |
Jon Hunter | 9883f7c | 2012-10-09 14:12:26 -0500 | [diff] [blame] | 411 | struct device_node *np = NULL; |
Vaibhav Hiremath | 1fe97c8 | 2012-05-09 10:07:05 -0700 | [diff] [blame] | 412 | struct omap_hwmod *oh; |
Vaibhav Hiremath | 1fe97c8 | 2012-05-09 10:07:05 -0700 | [diff] [blame] | 413 | const char *oh_name = "counter_32k"; |
| 414 | |
| 415 | /* |
Tony Lindgren | 8d39ff3 | 2017-05-31 15:51:30 -0700 | [diff] [blame] | 416 | * See if the 32kHz counter is supported. |
Jon Hunter | 9883f7c | 2012-10-09 14:12:26 -0500 | [diff] [blame] | 417 | */ |
Tony Lindgren | 8d39ff3 | 2017-05-31 15:51:30 -0700 | [diff] [blame] | 418 | np = omap_get_timer_dt(omap_counter_match, NULL); |
| 419 | if (!np) |
| 420 | return -ENODEV; |
Jon Hunter | 9883f7c | 2012-10-09 14:12:26 -0500 | [diff] [blame] | 421 | |
Tony Lindgren | 8d39ff3 | 2017-05-31 15:51:30 -0700 | [diff] [blame] | 422 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); |
| 423 | if (!oh_name) |
| 424 | return -ENODEV; |
Jon Hunter | 9883f7c | 2012-10-09 14:12:26 -0500 | [diff] [blame] | 425 | |
| 426 | /* |
Vaibhav Hiremath | 1fe97c8 | 2012-05-09 10:07:05 -0700 | [diff] [blame] | 427 | * First check hwmod data is available for sync32k counter |
| 428 | */ |
| 429 | oh = omap_hwmod_lookup(oh_name); |
| 430 | if (!oh || oh->slaves_cnt == 0) |
| 431 | return -ENODEV; |
| 432 | |
| 433 | omap_hwmod_setup_one(oh_name); |
| 434 | |
Vaibhav Hiremath | 1fe97c8 | 2012-05-09 10:07:05 -0700 | [diff] [blame] | 435 | ret = omap_hwmod_enable(oh); |
| 436 | if (ret) { |
| 437 | pr_warn("%s: failed to enable counter_32k module (%d)\n", |
| 438 | __func__, ret); |
| 439 | return ret; |
| 440 | } |
| 441 | |
Vaibhav Hiremath | 1fe97c8 | 2012-05-09 10:07:05 -0700 | [diff] [blame] | 442 | return ret; |
| 443 | } |
| 444 | |
| 445 | static void __init omap2_gptimer_clocksource_init(int gptimer_id, |
Jon Hunter | 2eb0393 | 2013-01-28 17:53:57 -0600 | [diff] [blame] | 446 | const char *fck_source, |
| 447 | const char *property) |
Tony Lindgren | 3d05a3e | 2011-03-29 15:54:49 -0700 | [diff] [blame] | 448 | { |
| 449 | int res; |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 450 | |
Jon Hunter | 8f6924d | 2013-02-01 16:40:09 -0600 | [diff] [blame] | 451 | clksrc.id = gptimer_id; |
Jon Hunter | bfd6d02 | 2012-09-27 12:47:43 -0500 | [diff] [blame] | 452 | clksrc.errata = omap_dm_timer_get_errata(); |
| 453 | |
Jon Hunter | 8f6924d | 2013-02-01 16:40:09 -0600 | [diff] [blame] | 454 | res = omap_dm_timer_init_one(&clksrc, fck_source, property, |
Jon Hunter | e95ea43 | 2013-01-29 13:55:25 -0600 | [diff] [blame] | 455 | &clocksource_gpt.name, |
Jon Hunter | bfd6d02 | 2012-09-27 12:47:43 -0500 | [diff] [blame] | 456 | OMAP_TIMER_NONPOSTED); |
Tony Lindgren | 3d05a3e | 2011-03-29 15:54:49 -0700 | [diff] [blame] | 457 | BUG_ON(res); |
Paul Walmsley | cbc9438 | 2011-02-22 19:59:49 -0700 | [diff] [blame] | 458 | |
Tony Lindgren | ee17f11 | 2011-09-16 15:44:20 -0700 | [diff] [blame] | 459 | __omap_dm_timer_load_start(&clksrc, |
Jon Hunter | 971d025 | 2012-09-27 11:49:45 -0500 | [diff] [blame] | 460 | OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, |
Jon Hunter | bfd6d02 | 2012-09-27 12:47:43 -0500 | [diff] [blame] | 461 | OMAP_TIMER_NONPOSTED); |
Stephen Boyd | f99ba47 | 2013-11-15 15:26:18 -0800 | [diff] [blame] | 462 | sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate); |
Tony Lindgren | 3d05a3e | 2011-03-29 15:54:49 -0700 | [diff] [blame] | 463 | |
| 464 | if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) |
| 465 | pr_err("Could not register clocksource %s\n", |
| 466 | clocksource_gpt.name); |
Vaibhav Hiremath | 1fe97c8 | 2012-05-09 10:07:05 -0700 | [diff] [blame] | 467 | else |
Jon Hunter | e95ea43 | 2013-01-29 13:55:25 -0600 | [diff] [blame] | 468 | pr_info("OMAP clocksource: %s at %lu Hz\n", |
| 469 | clocksource_gpt.name, clksrc.rate); |
Kevin Hilman | 5a3a388 | 2007-11-12 23:24:02 -0800 | [diff] [blame] | 470 | } |
Vaibhav Hiremath | 1fe97c8 | 2012-05-09 10:07:05 -0700 | [diff] [blame] | 471 | |
Felipe Balbi | 3afbb9a | 2015-09-29 13:12:55 -0500 | [diff] [blame] | 472 | static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src, |
| 473 | const char *clkev_prop, int clksrc_nr, const char *clksrc_src, |
| 474 | const char *clksrc_prop, bool gptimer) |
| 475 | { |
| 476 | omap_clk_init(); |
| 477 | omap_dmtimer_init(); |
| 478 | omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop); |
| 479 | |
| 480 | /* Enable the use of clocksource="gp_timer" kernel parameter */ |
| 481 | if (use_gptimer_clksrc || gptimer) |
| 482 | omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src, |
| 483 | clksrc_prop); |
| 484 | else |
| 485 | omap2_sync32k_clocksource_init(); |
| 486 | } |
| 487 | |
Felipe Balbi | 6f82e25 | 2015-09-29 13:26:45 -0500 | [diff] [blame] | 488 | void __init omap_init_time(void) |
Felipe Balbi | 3afbb9a | 2015-09-29 13:12:55 -0500 | [diff] [blame] | 489 | { |
| 490 | __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", |
| 491 | 2, "timer_sys_ck", NULL, false); |
Felipe Balbi | 9c46ffc | 2015-09-29 13:15:02 -0500 | [diff] [blame] | 492 | |
Daniel Lezcano | ba5d08c | 2017-05-26 17:40:46 +0200 | [diff] [blame] | 493 | timer_probe(); |
Felipe Balbi | 3afbb9a | 2015-09-29 13:12:55 -0500 | [diff] [blame] | 494 | } |
| 495 | |
| 496 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) |
| 497 | void __init omap3_secure_sync32k_timer_init(void) |
| 498 | { |
| 499 | __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure", |
| 500 | 2, "timer_sys_ck", NULL, false); |
Tero Kristo | 970f909 | 2016-06-16 15:25:18 +0300 | [diff] [blame] | 501 | |
Daniel Lezcano | ba5d08c | 2017-05-26 17:40:46 +0200 | [diff] [blame] | 502 | timer_probe(); |
Felipe Balbi | 3afbb9a | 2015-09-29 13:12:55 -0500 | [diff] [blame] | 503 | } |
| 504 | #endif /* CONFIG_ARCH_OMAP3 */ |
| 505 | |
Grygorii Strashko | f86a2c8 | 2016-12-05 09:27:44 +0530 | [diff] [blame] | 506 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \ |
| 507 | defined(CONFIG_SOC_AM43XX) |
Felipe Balbi | 3afbb9a | 2015-09-29 13:12:55 -0500 | [diff] [blame] | 508 | void __init omap3_gptimer_timer_init(void) |
| 509 | { |
| 510 | __omap_sync32k_timer_init(2, "timer_sys_ck", NULL, |
| 511 | 1, "timer_sys_ck", "ti,timer-alwon", true); |
Grygorii Strashko | f86a2c8 | 2016-12-05 09:27:44 +0530 | [diff] [blame] | 512 | if (of_have_populated_dt()) |
Daniel Lezcano | ba5d08c | 2017-05-26 17:40:46 +0200 | [diff] [blame] | 513 | timer_probe(); |
Felipe Balbi | 3afbb9a | 2015-09-29 13:12:55 -0500 | [diff] [blame] | 514 | } |
| 515 | #endif |
| 516 | |
| 517 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ |
Grygorii Strashko | f86a2c8 | 2016-12-05 09:27:44 +0530 | [diff] [blame] | 518 | defined(CONFIG_SOC_DRA7XX) |
Felipe Balbi | 3afbb9a | 2015-09-29 13:12:55 -0500 | [diff] [blame] | 519 | static void __init omap4_sync32k_timer_init(void) |
| 520 | { |
| 521 | __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", |
| 522 | 2, "sys_clkin_ck", NULL, false); |
| 523 | } |
| 524 | |
| 525 | void __init omap4_local_timer_init(void) |
| 526 | { |
| 527 | omap4_sync32k_timer_init(); |
Daniel Lezcano | ba5d08c | 2017-05-26 17:40:46 +0200 | [diff] [blame] | 528 | timer_probe(); |
Felipe Balbi | 3afbb9a | 2015-09-29 13:12:55 -0500 | [diff] [blame] | 529 | } |
| 530 | #endif |
| 531 | |
| 532 | #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) |
| 533 | |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 534 | /* |
| 535 | * The realtime counter also called master counter, is a free-running |
| 536 | * counter, which is related to real time. It produces the count used |
| 537 | * by the CPU local timer peripherals in the MPU cluster. The timer counts |
| 538 | * at a rate of 6.144 MHz. Because the device operates on different clocks |
| 539 | * in different power modes, the master counter shifts operation between |
| 540 | * clocks, adjusting the increment per clock in hardware accordingly to |
| 541 | * maintain a constant count rate. |
| 542 | */ |
| 543 | static void __init realtime_counter_init(void) |
| 544 | { |
Felipe Balbi | 3afbb9a | 2015-09-29 13:12:55 -0500 | [diff] [blame] | 545 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 546 | void __iomem *base; |
| 547 | static struct clk *sys_clk; |
| 548 | unsigned long rate; |
Lennart Sorensen | afc9d59 | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 549 | unsigned int reg; |
| 550 | unsigned long long num, den; |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 551 | |
| 552 | base = ioremap(REALTIME_COUNTER_BASE, SZ_32); |
| 553 | if (!base) { |
| 554 | pr_err("%s: ioremap failed\n", __func__); |
| 555 | return; |
| 556 | } |
Tony Lindgren | 7f585bb | 2013-04-03 10:47:59 -0700 | [diff] [blame] | 557 | sys_clk = clk_get(NULL, "sys_clkin"); |
Wei Yongjun | 533b298 | 2012-10-08 15:01:41 -0700 | [diff] [blame] | 558 | if (IS_ERR(sys_clk)) { |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 559 | pr_err("%s: failed to get system clock handle\n", __func__); |
| 560 | iounmap(base); |
| 561 | return; |
| 562 | } |
| 563 | |
| 564 | rate = clk_get_rate(sys_clk); |
Chen Hui | 5f9aeda | 2022-11-08 22:19:17 +0800 | [diff] [blame] | 565 | clk_put(sys_clk); |
Lennart Sorensen | afc9d59 | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 566 | |
| 567 | if (soc_is_dra7xx()) { |
| 568 | /* |
| 569 | * Errata i856 says the 32.768KHz crystal does not start at |
| 570 | * power on, so the CPU falls back to an emulated 32KHz clock |
| 571 | * based on sysclk / 610 instead. This causes the master counter |
| 572 | * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 |
| 573 | * (OR sysclk * 75 / 244) |
| 574 | * |
| 575 | * This affects at least the DRA7/AM572x 1.0, 1.1 revisions. |
| 576 | * Of course any board built without a populated 32.768KHz |
| 577 | * crystal would also need this fix even if the CPU is fixed |
| 578 | * later. |
| 579 | * |
| 580 | * Either case can be detected by using the two speedselect bits |
| 581 | * If they are not 0, then the 32.768KHz clock driving the |
| 582 | * coarse counter that corrects the fine counter every time it |
| 583 | * ticks is actually rate/610 rather than 32.768KHz and we |
| 584 | * should compensate to avoid the 570ppm (at 20MHz, much worse |
| 585 | * at other rates) too fast system time. |
| 586 | */ |
| 587 | reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP); |
| 588 | if (reg & DRA7_SPEEDSELECT_MASK) { |
| 589 | num = 75; |
| 590 | den = 244; |
| 591 | goto sysclk1_based; |
| 592 | } |
| 593 | } |
| 594 | |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 595 | /* Numerator/denumerator values refer TRM Realtime Counter section */ |
| 596 | switch (rate) { |
Lennart Sorensen | 572b24e | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 597 | case 12000000: |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 598 | num = 64; |
| 599 | den = 125; |
| 600 | break; |
Lennart Sorensen | 572b24e | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 601 | case 13000000: |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 602 | num = 768; |
| 603 | den = 1625; |
| 604 | break; |
| 605 | case 19200000: |
| 606 | num = 8; |
| 607 | den = 25; |
| 608 | break; |
Sricharan R | 38a1981 | 2013-09-18 16:50:11 +0530 | [diff] [blame] | 609 | case 20000000: |
| 610 | num = 192; |
| 611 | den = 625; |
| 612 | break; |
Lennart Sorensen | 572b24e | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 613 | case 26000000: |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 614 | num = 384; |
| 615 | den = 1625; |
| 616 | break; |
Lennart Sorensen | 572b24e | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 617 | case 27000000: |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 618 | num = 256; |
| 619 | den = 1125; |
| 620 | break; |
| 621 | case 38400000: |
| 622 | default: |
| 623 | /* Program it for 38.4 MHz */ |
| 624 | num = 4; |
| 625 | den = 25; |
| 626 | break; |
| 627 | } |
| 628 | |
Lennart Sorensen | afc9d59 | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 629 | sysclk1_based: |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 630 | /* Program numerator and denumerator registers */ |
Victor Kamensky | edfaf05 | 2014-04-15 20:37:46 +0300 | [diff] [blame] | 631 | reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) & |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 632 | NUMERATOR_DENUMERATOR_MASK; |
| 633 | reg |= num; |
Victor Kamensky | edfaf05 | 2014-04-15 20:37:46 +0300 | [diff] [blame] | 634 | writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET); |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 635 | |
Victor Kamensky | edfaf05 | 2014-04-15 20:37:46 +0300 | [diff] [blame] | 636 | reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 637 | NUMERATOR_DENUMERATOR_MASK; |
| 638 | reg |= den; |
Victor Kamensky | edfaf05 | 2014-04-15 20:37:46 +0300 | [diff] [blame] | 639 | writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 640 | |
Lennart Sorensen | afc9d59 | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 641 | arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den); |
R Sricharan | 5523e40 | 2013-10-10 13:13:48 +0530 | [diff] [blame] | 642 | set_cntfreq(); |
| 643 | |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 644 | iounmap(base); |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 645 | #endif |
Tony Lindgren | e74984e | 2011-03-29 15:54:48 -0700 | [diff] [blame] | 646 | } |
| 647 | |
Stephen Warren | 6bb27d7 | 2012-11-08 12:40:59 -0700 | [diff] [blame] | 648 | void __init omap5_realtime_timer_init(void) |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 649 | { |
Jon Hunter | 00ea4d5 | 2013-01-11 20:23:09 -0600 | [diff] [blame] | 650 | omap4_sync32k_timer_init(); |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 651 | realtime_counter_init(); |
Santosh Shilimkar | 3c7c5da | 2012-08-13 14:39:03 +0530 | [diff] [blame] | 652 | |
Daniel Lezcano | ba5d08c | 2017-05-26 17:40:46 +0200 | [diff] [blame] | 653 | timer_probe(); |
Santosh Shilimkar | fa6d79d | 2012-08-13 14:24:24 +0530 | [diff] [blame] | 654 | } |
Simon Barth | 0b8214f | 2013-10-08 10:50:33 +0200 | [diff] [blame] | 655 | #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */ |
R Sricharan | 37b3280 | 2012-05-02 13:07:12 +0530 | [diff] [blame] | 656 | |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 657 | /** |
Vaibhav Hiremath | 1fe97c8 | 2012-05-09 10:07:05 -0700 | [diff] [blame] | 658 | * omap2_override_clocksource - clocksource override with user configuration |
| 659 | * |
| 660 | * Allows user to override default clocksource, using kernel parameter |
| 661 | * clocksource="gp_timer" (For all OMAP2PLUS architectures) |
| 662 | * |
| 663 | * Note that, here we are using same standard kernel parameter "clocksource=", |
| 664 | * and not introducing any OMAP specific interface. |
| 665 | */ |
| 666 | static int __init omap2_override_clocksource(char *str) |
| 667 | { |
| 668 | if (!str) |
| 669 | return 0; |
| 670 | /* |
| 671 | * For OMAP architecture, we only have two options |
| 672 | * - sync_32k (default) |
| 673 | * - gp_timer (sys_clk based) |
| 674 | */ |
| 675 | if (!strcmp(str, "gp_timer")) |
| 676 | use_gptimer_clksrc = true; |
| 677 | |
| 678 | return 0; |
| 679 | } |
| 680 | early_param("clocksource", omap2_override_clocksource); |