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Paul Mackerras047ea782005-11-19 20:17:32 +11001#ifndef _ASM_POWERPC_MMU_H_
2#define _ASM_POWERPC_MMU_H_
Arnd Bergmann88ced032005-12-16 22:43:46 +01003#ifdef __KERNEL__
Paul Mackerras047ea782005-11-19 20:17:32 +11004
Benjamin Herrenschmidtcd3db0c2010-07-06 15:39:02 -07005#include <linux/types.h>
6
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +00007#include <asm/asm-compat.h>
8#include <asm/feature-fixups.h>
9
10/*
11 * MMU features bit definitions
12 */
13
14/*
Aneesh Kumar K.V5a25b6f2016-07-27 13:19:01 +100015 * MMU families
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +000016 */
17#define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
18#define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
19#define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
20#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
21#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
Michael Ellermancd680982014-07-08 17:10:45 +100022#define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +000023
Aneesh Kumar K.V5a25b6f2016-07-27 13:19:01 +100024/* Radix page table supported and enabled */
25#define MMU_FTR_TYPE_RADIX ASM_CONST(0x00000040)
26
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +000027/*
Aneesh Kumar K.V5a25b6f2016-07-27 13:19:01 +100028 * Individual features below.
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +000029 */
Aneesh Kumar K.V5a25b6f2016-07-27 13:19:01 +100030
Aneesh Kumar K.Vaccfad72016-07-13 15:05:24 +053031/*
Aneesh Kumar K.Ve6f81a92017-03-29 17:21:53 +110032 * Support for 68 bit VA space. We added that from ISA 2.05
33 */
34#define MMU_FTR_68_BIT_VA ASM_CONST(0x00002000)
35/*
Aneesh Kumar K.V984d7a12016-11-24 15:09:54 +053036 * Kernel read only support.
37 * We added the ppp value 0b110 in ISA 2.04.
38 */
39#define MMU_FTR_KERNEL_RO ASM_CONST(0x00004000)
40
41/*
Aneesh Kumar K.Vaccfad72016-07-13 15:05:24 +053042 * We need to clear top 16bits of va (from the remaining 64 bits )in
43 * tlbie* instructions
44 */
45#define MMU_FTR_TLBIE_CROP_VA ASM_CONST(0x00008000)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +000046
47/* Enable use of high BAT registers */
48#define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000)
49
50/* Enable >32-bit physical addresses on 32-bit processor, only used
51 * by CONFIG_6xx currently as BookE supports that from day 1
52 */
53#define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000)
54
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +000055/* Enable use of broadcast TLB invalidations. We don't always set it
56 * on processors that support it due to other constraints with the
57 * use of such invalidations
58 */
59#define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000)
60
Kumar Galac3071952009-02-10 22:26:06 -060061/* Enable use of tlbilx invalidate instructions.
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +000062 */
Kumar Galac3071952009-02-10 22:26:06 -060063#define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000)
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +000064
65/* This indicates that the processor cannot handle multiple outstanding
66 * broadcast tlbivax or tlbsync. This makes the code use a spinlock
67 * around such invalidate forms.
68 */
69#define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000)
70
Kumar Gala2319f122009-03-19 03:55:41 +000071/* This indicates that the processor doesn't handle way selection
72 * properly and needs SW to track and update the LRU state. This
73 * is specific to an errata on e300c2/c3/c4 class parts
74 */
75#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
76
Kumar Galadf5d6ec2009-08-24 15:52:48 +000077/* Enable use of TLB reservation. Processor should support tlbsrx.
78 * instruction and MAS0[WQ].
79 */
80#define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000)
81
82/* Use paired MAS registers (MAS7||MAS3, etc.)
83 */
84#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
85
Michael Ellerman13b3d132014-07-10 12:29:20 +100086/* Doesn't support the B bit (1T segment) in SLBIE
Matt Evans44ae3ab2011-04-06 19:48:50 +000087 */
Michael Ellerman13b3d132014-07-10 12:29:20 +100088#define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000)
Matt Evans44ae3ab2011-04-06 19:48:50 +000089
90/* Support 16M large pages
91 */
92#define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
93
94/* Supports TLBIEL variant
95 */
96#define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
97
98/* Supports tlbies w/o locking
99 */
100#define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
101
102/* Large pages can be marked CI
103 */
104#define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
105
106/* 1T segments available
107 */
108#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
109
Matt Evans44ae3ab2011-04-06 19:48:50 +0000110/* MMU feature bit sets for various CPUs */
111#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
112 MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
113#define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
Aneesh Kumar K.Vaccfad72016-07-13 15:05:24 +0530114#define MMU_FTRS_PPC970 MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA
Matt Evans44ae3ab2011-04-06 19:48:50 +0000115#define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
Aneesh Kumar K.Ve6f81a92017-03-29 17:21:53 +1100116#define MMU_FTRS_POWER6 MMU_FTRS_POWER5 | MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA
117#define MMU_FTRS_POWER7 MMU_FTRS_POWER6
118#define MMU_FTRS_POWER8 MMU_FTRS_POWER6
119#define MMU_FTRS_POWER9 MMU_FTRS_POWER6
Matt Evans44ae3ab2011-04-06 19:48:50 +0000120#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
121 MMU_FTR_CI_LARGE_PAGE
122#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
123 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000124#ifndef __ASSEMBLY__
Kevin Hao4db73272016-07-23 14:42:41 +0530125#include <linux/bug.h>
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000126#include <asm/cputable.h>
127
Becky Bruce3160b092011-06-28 14:54:47 -0500128#ifdef CONFIG_PPC_FSL_BOOK3E
129#include <asm/percpu.h>
130DECLARE_PER_CPU(int, next_tlbcam_idx);
131#endif
132
Michael Ellerman773edea2016-05-11 15:30:47 +1000133enum {
134 MMU_FTRS_POSSIBLE = MMU_FTR_HPTE_TABLE | MMU_FTR_TYPE_8xx |
135 MMU_FTR_TYPE_40x | MMU_FTR_TYPE_44x | MMU_FTR_TYPE_FSL_E |
136 MMU_FTR_TYPE_47x | MMU_FTR_USE_HIGH_BATS | MMU_FTR_BIG_PHYS |
137 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_USE_TLBILX |
138 MMU_FTR_LOCK_BCAST_INVAL | MMU_FTR_NEED_DTLB_SW_LRU |
139 MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS |
140 MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
141 MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
Aneesh Kumar K.Vaccfad72016-07-13 15:05:24 +0530142 MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
Aneesh Kumar K.Ve6f81a92017-03-29 17:21:53 +1100143 MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA |
Aneesh Kumar K.Va8ed87c2016-04-29 23:26:06 +1000144#ifdef CONFIG_PPC_RADIX_MMU
Aneesh Kumar K.V5a25b6f2016-07-27 13:19:01 +1000145 MMU_FTR_TYPE_RADIX |
Aneesh Kumar K.Va8ed87c2016-04-29 23:26:06 +1000146#endif
147 0,
Michael Ellerman773edea2016-05-11 15:30:47 +1000148};
149
Michael Ellermana141cca2016-07-27 20:48:36 +1000150static inline bool early_mmu_has_feature(unsigned long feature)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000151{
Michael Ellermana81dc9d2016-07-27 13:39:42 +1000152 return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature);
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000153}
154
Kevin Haoc12e6f22016-07-23 14:42:42 +0530155#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
156#include <linux/jump_label.h>
157
158#define NUM_MMU_FTR_KEYS 32
159
160extern struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS];
161
162extern void mmu_feature_keys_init(void);
163
164static __always_inline bool mmu_has_feature(unsigned long feature)
165{
166 int i;
167
Michael Ellermanb5fa0f72017-01-24 16:36:57 +1100168#ifndef __clang__ /* clang can't cope with this */
Kevin Haoc12e6f22016-07-23 14:42:42 +0530169 BUILD_BUG_ON(!__builtin_constant_p(feature));
Michael Ellermanb5fa0f72017-01-24 16:36:57 +1100170#endif
Kevin Haoc12e6f22016-07-23 14:42:42 +0530171
Aneesh Kumar K.Vc812c7d2016-07-23 14:42:43 +0530172#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG
173 if (!static_key_initialized) {
174 printk("Warning! mmu_has_feature() used prior to jump label init!\n");
175 dump_stack();
176 return early_mmu_has_feature(feature);
177 }
178#endif
179
Kevin Haoc12e6f22016-07-23 14:42:42 +0530180 if (!(MMU_FTRS_POSSIBLE & feature))
181 return false;
182
183 i = __builtin_ctzl(feature);
184 return static_branch_likely(&mmu_feature_keys[i]);
185}
186
187static inline void mmu_clear_feature(unsigned long feature)
188{
189 int i;
190
191 i = __builtin_ctzl(feature);
192 cur_cpu_spec->mmu_features &= ~feature;
193 static_branch_disable(&mmu_feature_keys[i]);
194}
195#else
196
197static inline void mmu_feature_keys_init(void)
198{
199
200}
201
Michael Ellermana141cca2016-07-27 20:48:36 +1000202static inline bool mmu_has_feature(unsigned long feature)
203{
204 return early_mmu_has_feature(feature);
205}
206
Dave Kleikamp91b191c2011-07-04 18:38:03 +0000207static inline void mmu_clear_feature(unsigned long feature)
208{
209 cur_cpu_spec->mmu_features &= ~feature;
210}
Kevin Haoc12e6f22016-07-23 14:42:42 +0530211#endif /* CONFIG_JUMP_LABEL */
Dave Kleikamp91b191c2011-07-04 18:38:03 +0000212
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000213extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
214
Benjamin Herrenschmidtcd3db0c2010-07-06 15:39:02 -0700215#ifdef CONFIG_PPC64
216/* This is our real memory area size on ppc64 server, on embedded, we
217 * make it match the size our of bolted TLB area
218 */
219extern u64 ppc64_rma_size;
Benjamin Herrenschmidtfe036a02016-08-19 14:22:37 +0530220
221/* Cleanup function used by kexec */
222extern void mmu_cleanup_all(void);
223extern void radix__mmu_cleanup_all(void);
Paul Mackerras9d661952016-11-21 16:00:58 +1100224
225/* Functions for creating and updating partition table on POWER9 */
226extern void mmu_partition_table_init(void);
227extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
228 unsigned long dw1);
Benjamin Herrenschmidtcd3db0c2010-07-06 15:39:02 -0700229#endif /* CONFIG_PPC64 */
230
Aneesh Kumar K.V78f1dbd2012-09-10 02:52:57 +0000231struct mm_struct;
232#ifdef CONFIG_DEBUG_VM
233extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
234#else /* CONFIG_DEBUG_VM */
235static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
236{
237}
238#endif /* !CONFIG_DEBUG_VM */
239
Michael Ellermanbab4c8d2016-07-27 13:37:58 +1000240#ifdef CONFIG_PPC_RADIX_MMU
241static inline bool radix_enabled(void)
242{
243 return mmu_has_feature(MMU_FTR_TYPE_RADIX);
244}
Michael Ellermana141cca2016-07-27 20:48:36 +1000245
246static inline bool early_radix_enabled(void)
247{
248 return early_mmu_has_feature(MMU_FTR_TYPE_RADIX);
249}
Michael Ellermanbab4c8d2016-07-27 13:37:58 +1000250#else
251static inline bool radix_enabled(void)
252{
253 return false;
254}
Michael Ellermana141cca2016-07-27 20:48:36 +1000255
256static inline bool early_radix_enabled(void)
257{
258 return false;
259}
Michael Ellermanbab4c8d2016-07-27 13:37:58 +1000260#endif
261
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000262#endif /* !__ASSEMBLY__ */
263
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +1000264/* The kernel use the constants below to index in the page sizes array.
265 * The use of fixed constants for this purpose is better for performances
266 * of the low level hash refill handlers.
267 *
268 * A non supported page size has a "shift" field set to 0
269 *
270 * Any new page size being implemented can get a new entry in here. Whether
271 * the kernel will use it or not is a different matter though. The actual page
272 * size used by hugetlbfs is not defined here and may be made variable
273 *
274 * Note: This array ended up being a false good idea as it's growing to the
275 * point where I wonder if we should replace it with something different,
276 * to think about, feedback welcome. --BenH.
277 */
278
Scott Wooda8b91e42012-06-14 13:40:55 +0000279/* These are #defines as they have to be used in assembly */
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +1000280#define MMU_PAGE_4K 0
281#define MMU_PAGE_16K 1
282#define MMU_PAGE_64K 2
283#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
284#define MMU_PAGE_256K 4
Christophe Leroy4b9142862016-12-07 08:47:28 +0100285#define MMU_PAGE_512K 5
286#define MMU_PAGE_1M 6
287#define MMU_PAGE_2M 7
288#define MMU_PAGE_4M 8
289#define MMU_PAGE_8M 9
290#define MMU_PAGE_16M 10
291#define MMU_PAGE_64M 11
292#define MMU_PAGE_256M 12
293#define MMU_PAGE_1G 13
294#define MMU_PAGE_16G 14
295#define MMU_PAGE_64G 15
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +1000296
Aneesh Kumar K.Ve6f81a92017-03-29 17:21:53 +1100297/*
298 * N.B. we need to change the type of hpte_page_sizes if this gets to be > 16
299 * Also we need to change he type of mm_context.low/high_slices_psize.
300 */
Christophe Leroy4b9142862016-12-07 08:47:28 +0100301#define MMU_PAGE_COUNT 16
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000302
Aneesh Kumar K.V11a6f6a2016-04-29 23:25:41 +1000303#ifdef CONFIG_PPC_BOOK3S_64
304#include <asm/book3s/64/mmu.h>
305#else /* CONFIG_PPC_BOOK3S_64 */
306
Aneesh Kumar K.V756d08d2016-04-29 23:25:57 +1000307#ifndef __ASSEMBLY__
308/* MMU initialization */
309extern void early_init_mmu(void);
310extern void early_init_mmu_secondary(void);
311extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
312 phys_addr_t first_memblock_size);
Michael Ellerman1a01dc82016-07-26 20:09:30 +1000313static inline void mmu_early_init_devtree(void) { }
Aneesh Kumar K.V756d08d2016-04-29 23:25:57 +1000314#endif /* __ASSEMBLY__ */
Aneesh Kumar K.V11a6f6a2016-04-29 23:25:41 +1000315#endif
316
317#if defined(CONFIG_PPC_STD_MMU_32)
David Gibson4db68bf2007-06-13 14:52:54 +1000318/* 32-bit classic hash table MMU */
Aneesh Kumar K.Vf64e8082016-03-01 12:59:20 +0530319#include <asm/book3s/32/mmu-hash.h>
Josh Boyer4d922c82007-08-20 07:28:48 -0500320#elif defined(CONFIG_40x)
321/* 40x-style software loaded TLB */
322# include <asm/mmu-40x.h>
David Gibson57d79092007-04-30 14:06:25 +1000323#elif defined(CONFIG_44x)
324/* 44x-style software loaded TLB */
325# include <asm/mmu-44x.h>
Kumar Gala70fe3af2009-02-12 16:12:40 -0600326#elif defined(CONFIG_PPC_BOOK3E_MMU)
327/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
328# include <asm/mmu-book3e.h>
David Gibson31202342007-06-22 14:58:55 +1000329#elif defined (CONFIG_PPC_8xx)
330/* Motorola/Freescale 8xx software loaded TLB */
331# include <asm/mmu-8xx.h>
David Gibson1f8d4192005-05-05 16:15:13 -0700332#endif
David Gibson1f8d4192005-05-05 16:15:13 -0700333
Arnd Bergmann88ced032005-12-16 22:43:46 +0100334#endif /* __KERNEL__ */
Paul Mackerras047ea782005-11-19 20:17:32 +1100335#endif /* _ASM_POWERPC_MMU_H_ */