Paul Mackerras | 047ea78 | 2005-11-19 20:17:32 +1100 | [diff] [blame] | 1 | #ifndef _ASM_POWERPC_MMU_H_ |
| 2 | #define _ASM_POWERPC_MMU_H_ |
Arnd Bergmann | 88ced03 | 2005-12-16 22:43:46 +0100 | [diff] [blame] | 3 | #ifdef __KERNEL__ |
Paul Mackerras | 047ea78 | 2005-11-19 20:17:32 +1100 | [diff] [blame] | 4 | |
Benjamin Herrenschmidt | cd3db0c | 2010-07-06 15:39:02 -0700 | [diff] [blame] | 5 | #include <linux/types.h> |
| 6 | |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 7 | #include <asm/asm-compat.h> |
| 8 | #include <asm/feature-fixups.h> |
| 9 | |
| 10 | /* |
| 11 | * MMU features bit definitions |
| 12 | */ |
| 13 | |
| 14 | /* |
Aneesh Kumar K.V | 5a25b6f | 2016-07-27 13:19:01 +1000 | [diff] [blame] | 15 | * MMU families |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 16 | */ |
| 17 | #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001) |
| 18 | #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002) |
| 19 | #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004) |
| 20 | #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008) |
| 21 | #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010) |
Michael Ellerman | cd68098 | 2014-07-08 17:10:45 +1000 | [diff] [blame] | 22 | #define MMU_FTR_TYPE_47x ASM_CONST(0x00000020) |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 23 | |
Aneesh Kumar K.V | 5a25b6f | 2016-07-27 13:19:01 +1000 | [diff] [blame] | 24 | /* Radix page table supported and enabled */ |
| 25 | #define MMU_FTR_TYPE_RADIX ASM_CONST(0x00000040) |
| 26 | |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 27 | /* |
Aneesh Kumar K.V | 5a25b6f | 2016-07-27 13:19:01 +1000 | [diff] [blame] | 28 | * Individual features below. |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 29 | */ |
Aneesh Kumar K.V | 5a25b6f | 2016-07-27 13:19:01 +1000 | [diff] [blame] | 30 | |
Aneesh Kumar K.V | accfad7 | 2016-07-13 15:05:24 +0530 | [diff] [blame] | 31 | /* |
Aneesh Kumar K.V | e6f81a9 | 2017-03-29 17:21:53 +1100 | [diff] [blame] | 32 | * Support for 68 bit VA space. We added that from ISA 2.05 |
| 33 | */ |
| 34 | #define MMU_FTR_68_BIT_VA ASM_CONST(0x00002000) |
| 35 | /* |
Aneesh Kumar K.V | 984d7a1 | 2016-11-24 15:09:54 +0530 | [diff] [blame] | 36 | * Kernel read only support. |
| 37 | * We added the ppp value 0b110 in ISA 2.04. |
| 38 | */ |
| 39 | #define MMU_FTR_KERNEL_RO ASM_CONST(0x00004000) |
| 40 | |
| 41 | /* |
Aneesh Kumar K.V | accfad7 | 2016-07-13 15:05:24 +0530 | [diff] [blame] | 42 | * We need to clear top 16bits of va (from the remaining 64 bits )in |
| 43 | * tlbie* instructions |
| 44 | */ |
| 45 | #define MMU_FTR_TLBIE_CROP_VA ASM_CONST(0x00008000) |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 46 | |
| 47 | /* Enable use of high BAT registers */ |
| 48 | #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000) |
| 49 | |
| 50 | /* Enable >32-bit physical addresses on 32-bit processor, only used |
| 51 | * by CONFIG_6xx currently as BookE supports that from day 1 |
| 52 | */ |
| 53 | #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000) |
| 54 | |
Benjamin Herrenschmidt | f048aac | 2008-12-18 19:13:38 +0000 | [diff] [blame] | 55 | /* Enable use of broadcast TLB invalidations. We don't always set it |
| 56 | * on processors that support it due to other constraints with the |
| 57 | * use of such invalidations |
| 58 | */ |
| 59 | #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000) |
| 60 | |
Kumar Gala | c307195 | 2009-02-10 22:26:06 -0600 | [diff] [blame] | 61 | /* Enable use of tlbilx invalidate instructions. |
Benjamin Herrenschmidt | f048aac | 2008-12-18 19:13:38 +0000 | [diff] [blame] | 62 | */ |
Kumar Gala | c307195 | 2009-02-10 22:26:06 -0600 | [diff] [blame] | 63 | #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000) |
Benjamin Herrenschmidt | f048aac | 2008-12-18 19:13:38 +0000 | [diff] [blame] | 64 | |
| 65 | /* This indicates that the processor cannot handle multiple outstanding |
| 66 | * broadcast tlbivax or tlbsync. This makes the code use a spinlock |
| 67 | * around such invalidate forms. |
| 68 | */ |
| 69 | #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000) |
| 70 | |
Kumar Gala | 2319f12 | 2009-03-19 03:55:41 +0000 | [diff] [blame] | 71 | /* This indicates that the processor doesn't handle way selection |
| 72 | * properly and needs SW to track and update the LRU state. This |
| 73 | * is specific to an errata on e300c2/c3/c4 class parts |
| 74 | */ |
| 75 | #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) |
| 76 | |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 77 | /* Enable use of TLB reservation. Processor should support tlbsrx. |
| 78 | * instruction and MAS0[WQ]. |
| 79 | */ |
| 80 | #define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000) |
| 81 | |
| 82 | /* Use paired MAS registers (MAS7||MAS3, etc.) |
| 83 | */ |
| 84 | #define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000) |
| 85 | |
Michael Ellerman | 13b3d13 | 2014-07-10 12:29:20 +1000 | [diff] [blame] | 86 | /* Doesn't support the B bit (1T segment) in SLBIE |
Matt Evans | 44ae3ab | 2011-04-06 19:48:50 +0000 | [diff] [blame] | 87 | */ |
Michael Ellerman | 13b3d13 | 2014-07-10 12:29:20 +1000 | [diff] [blame] | 88 | #define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000) |
Matt Evans | 44ae3ab | 2011-04-06 19:48:50 +0000 | [diff] [blame] | 89 | |
| 90 | /* Support 16M large pages |
| 91 | */ |
| 92 | #define MMU_FTR_16M_PAGE ASM_CONST(0x04000000) |
| 93 | |
| 94 | /* Supports TLBIEL variant |
| 95 | */ |
| 96 | #define MMU_FTR_TLBIEL ASM_CONST(0x08000000) |
| 97 | |
| 98 | /* Supports tlbies w/o locking |
| 99 | */ |
| 100 | #define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000) |
| 101 | |
| 102 | /* Large pages can be marked CI |
| 103 | */ |
| 104 | #define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000) |
| 105 | |
| 106 | /* 1T segments available |
| 107 | */ |
| 108 | #define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000) |
| 109 | |
Matt Evans | 44ae3ab | 2011-04-06 19:48:50 +0000 | [diff] [blame] | 110 | /* MMU feature bit sets for various CPUs */ |
| 111 | #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \ |
| 112 | MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2 |
| 113 | #define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2 |
Aneesh Kumar K.V | accfad7 | 2016-07-13 15:05:24 +0530 | [diff] [blame] | 114 | #define MMU_FTRS_PPC970 MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA |
Matt Evans | 44ae3ab | 2011-04-06 19:48:50 +0000 | [diff] [blame] | 115 | #define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE |
Aneesh Kumar K.V | e6f81a9 | 2017-03-29 17:21:53 +1100 | [diff] [blame] | 116 | #define MMU_FTRS_POWER6 MMU_FTRS_POWER5 | MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA |
| 117 | #define MMU_FTRS_POWER7 MMU_FTRS_POWER6 |
| 118 | #define MMU_FTRS_POWER8 MMU_FTRS_POWER6 |
| 119 | #define MMU_FTRS_POWER9 MMU_FTRS_POWER6 |
Matt Evans | 44ae3ab | 2011-04-06 19:48:50 +0000 | [diff] [blame] | 120 | #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ |
| 121 | MMU_FTR_CI_LARGE_PAGE |
| 122 | #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ |
| 123 | MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 124 | #ifndef __ASSEMBLY__ |
Kevin Hao | 4db7327 | 2016-07-23 14:42:41 +0530 | [diff] [blame] | 125 | #include <linux/bug.h> |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 126 | #include <asm/cputable.h> |
| 127 | |
Becky Bruce | 3160b09 | 2011-06-28 14:54:47 -0500 | [diff] [blame] | 128 | #ifdef CONFIG_PPC_FSL_BOOK3E |
| 129 | #include <asm/percpu.h> |
| 130 | DECLARE_PER_CPU(int, next_tlbcam_idx); |
| 131 | #endif |
| 132 | |
Michael Ellerman | 773edea | 2016-05-11 15:30:47 +1000 | [diff] [blame] | 133 | enum { |
| 134 | MMU_FTRS_POSSIBLE = MMU_FTR_HPTE_TABLE | MMU_FTR_TYPE_8xx | |
| 135 | MMU_FTR_TYPE_40x | MMU_FTR_TYPE_44x | MMU_FTR_TYPE_FSL_E | |
| 136 | MMU_FTR_TYPE_47x | MMU_FTR_USE_HIGH_BATS | MMU_FTR_BIG_PHYS | |
| 137 | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_USE_TLBILX | |
| 138 | MMU_FTR_LOCK_BCAST_INVAL | MMU_FTR_NEED_DTLB_SW_LRU | |
| 139 | MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS | |
| 140 | MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL | |
| 141 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE | |
Aneesh Kumar K.V | accfad7 | 2016-07-13 15:05:24 +0530 | [diff] [blame] | 142 | MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA | |
Aneesh Kumar K.V | e6f81a9 | 2017-03-29 17:21:53 +1100 | [diff] [blame] | 143 | MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA | |
Aneesh Kumar K.V | a8ed87c | 2016-04-29 23:26:06 +1000 | [diff] [blame] | 144 | #ifdef CONFIG_PPC_RADIX_MMU |
Aneesh Kumar K.V | 5a25b6f | 2016-07-27 13:19:01 +1000 | [diff] [blame] | 145 | MMU_FTR_TYPE_RADIX | |
Aneesh Kumar K.V | a8ed87c | 2016-04-29 23:26:06 +1000 | [diff] [blame] | 146 | #endif |
| 147 | 0, |
Michael Ellerman | 773edea | 2016-05-11 15:30:47 +1000 | [diff] [blame] | 148 | }; |
| 149 | |
Michael Ellerman | a141cca | 2016-07-27 20:48:36 +1000 | [diff] [blame] | 150 | static inline bool early_mmu_has_feature(unsigned long feature) |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 151 | { |
Michael Ellerman | a81dc9d | 2016-07-27 13:39:42 +1000 | [diff] [blame] | 152 | return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature); |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 153 | } |
| 154 | |
Kevin Hao | c12e6f2 | 2016-07-23 14:42:42 +0530 | [diff] [blame] | 155 | #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS |
| 156 | #include <linux/jump_label.h> |
| 157 | |
| 158 | #define NUM_MMU_FTR_KEYS 32 |
| 159 | |
| 160 | extern struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS]; |
| 161 | |
| 162 | extern void mmu_feature_keys_init(void); |
| 163 | |
| 164 | static __always_inline bool mmu_has_feature(unsigned long feature) |
| 165 | { |
| 166 | int i; |
| 167 | |
Michael Ellerman | b5fa0f7 | 2017-01-24 16:36:57 +1100 | [diff] [blame] | 168 | #ifndef __clang__ /* clang can't cope with this */ |
Kevin Hao | c12e6f2 | 2016-07-23 14:42:42 +0530 | [diff] [blame] | 169 | BUILD_BUG_ON(!__builtin_constant_p(feature)); |
Michael Ellerman | b5fa0f7 | 2017-01-24 16:36:57 +1100 | [diff] [blame] | 170 | #endif |
Kevin Hao | c12e6f2 | 2016-07-23 14:42:42 +0530 | [diff] [blame] | 171 | |
Aneesh Kumar K.V | c812c7d | 2016-07-23 14:42:43 +0530 | [diff] [blame] | 172 | #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG |
| 173 | if (!static_key_initialized) { |
| 174 | printk("Warning! mmu_has_feature() used prior to jump label init!\n"); |
| 175 | dump_stack(); |
| 176 | return early_mmu_has_feature(feature); |
| 177 | } |
| 178 | #endif |
| 179 | |
Kevin Hao | c12e6f2 | 2016-07-23 14:42:42 +0530 | [diff] [blame] | 180 | if (!(MMU_FTRS_POSSIBLE & feature)) |
| 181 | return false; |
| 182 | |
| 183 | i = __builtin_ctzl(feature); |
| 184 | return static_branch_likely(&mmu_feature_keys[i]); |
| 185 | } |
| 186 | |
| 187 | static inline void mmu_clear_feature(unsigned long feature) |
| 188 | { |
| 189 | int i; |
| 190 | |
| 191 | i = __builtin_ctzl(feature); |
| 192 | cur_cpu_spec->mmu_features &= ~feature; |
| 193 | static_branch_disable(&mmu_feature_keys[i]); |
| 194 | } |
| 195 | #else |
| 196 | |
| 197 | static inline void mmu_feature_keys_init(void) |
| 198 | { |
| 199 | |
| 200 | } |
| 201 | |
Michael Ellerman | a141cca | 2016-07-27 20:48:36 +1000 | [diff] [blame] | 202 | static inline bool mmu_has_feature(unsigned long feature) |
| 203 | { |
| 204 | return early_mmu_has_feature(feature); |
| 205 | } |
| 206 | |
Dave Kleikamp | 91b191c | 2011-07-04 18:38:03 +0000 | [diff] [blame] | 207 | static inline void mmu_clear_feature(unsigned long feature) |
| 208 | { |
| 209 | cur_cpu_spec->mmu_features &= ~feature; |
| 210 | } |
Kevin Hao | c12e6f2 | 2016-07-23 14:42:42 +0530 | [diff] [blame] | 211 | #endif /* CONFIG_JUMP_LABEL */ |
Dave Kleikamp | 91b191c | 2011-07-04 18:38:03 +0000 | [diff] [blame] | 212 | |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 213 | extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup; |
| 214 | |
Benjamin Herrenschmidt | cd3db0c | 2010-07-06 15:39:02 -0700 | [diff] [blame] | 215 | #ifdef CONFIG_PPC64 |
| 216 | /* This is our real memory area size on ppc64 server, on embedded, we |
| 217 | * make it match the size our of bolted TLB area |
| 218 | */ |
| 219 | extern u64 ppc64_rma_size; |
Benjamin Herrenschmidt | fe036a0 | 2016-08-19 14:22:37 +0530 | [diff] [blame] | 220 | |
| 221 | /* Cleanup function used by kexec */ |
| 222 | extern void mmu_cleanup_all(void); |
| 223 | extern void radix__mmu_cleanup_all(void); |
Paul Mackerras | 9d66195 | 2016-11-21 16:00:58 +1100 | [diff] [blame] | 224 | |
| 225 | /* Functions for creating and updating partition table on POWER9 */ |
| 226 | extern void mmu_partition_table_init(void); |
| 227 | extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, |
| 228 | unsigned long dw1); |
Benjamin Herrenschmidt | cd3db0c | 2010-07-06 15:39:02 -0700 | [diff] [blame] | 229 | #endif /* CONFIG_PPC64 */ |
| 230 | |
Aneesh Kumar K.V | 78f1dbd | 2012-09-10 02:52:57 +0000 | [diff] [blame] | 231 | struct mm_struct; |
| 232 | #ifdef CONFIG_DEBUG_VM |
| 233 | extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr); |
| 234 | #else /* CONFIG_DEBUG_VM */ |
| 235 | static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr) |
| 236 | { |
| 237 | } |
| 238 | #endif /* !CONFIG_DEBUG_VM */ |
| 239 | |
Michael Ellerman | bab4c8d | 2016-07-27 13:37:58 +1000 | [diff] [blame] | 240 | #ifdef CONFIG_PPC_RADIX_MMU |
| 241 | static inline bool radix_enabled(void) |
| 242 | { |
| 243 | return mmu_has_feature(MMU_FTR_TYPE_RADIX); |
| 244 | } |
Michael Ellerman | a141cca | 2016-07-27 20:48:36 +1000 | [diff] [blame] | 245 | |
| 246 | static inline bool early_radix_enabled(void) |
| 247 | { |
| 248 | return early_mmu_has_feature(MMU_FTR_TYPE_RADIX); |
| 249 | } |
Michael Ellerman | bab4c8d | 2016-07-27 13:37:58 +1000 | [diff] [blame] | 250 | #else |
| 251 | static inline bool radix_enabled(void) |
| 252 | { |
| 253 | return false; |
| 254 | } |
Michael Ellerman | a141cca | 2016-07-27 20:48:36 +1000 | [diff] [blame] | 255 | |
| 256 | static inline bool early_radix_enabled(void) |
| 257 | { |
| 258 | return false; |
| 259 | } |
Michael Ellerman | bab4c8d | 2016-07-27 13:37:58 +1000 | [diff] [blame] | 260 | #endif |
| 261 | |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 262 | #endif /* !__ASSEMBLY__ */ |
| 263 | |
Benjamin Herrenschmidt | 57e2a99 | 2009-07-28 11:59:34 +1000 | [diff] [blame] | 264 | /* The kernel use the constants below to index in the page sizes array. |
| 265 | * The use of fixed constants for this purpose is better for performances |
| 266 | * of the low level hash refill handlers. |
| 267 | * |
| 268 | * A non supported page size has a "shift" field set to 0 |
| 269 | * |
| 270 | * Any new page size being implemented can get a new entry in here. Whether |
| 271 | * the kernel will use it or not is a different matter though. The actual page |
| 272 | * size used by hugetlbfs is not defined here and may be made variable |
| 273 | * |
| 274 | * Note: This array ended up being a false good idea as it's growing to the |
| 275 | * point where I wonder if we should replace it with something different, |
| 276 | * to think about, feedback welcome. --BenH. |
| 277 | */ |
| 278 | |
Scott Wood | a8b91e4 | 2012-06-14 13:40:55 +0000 | [diff] [blame] | 279 | /* These are #defines as they have to be used in assembly */ |
Benjamin Herrenschmidt | 57e2a99 | 2009-07-28 11:59:34 +1000 | [diff] [blame] | 280 | #define MMU_PAGE_4K 0 |
| 281 | #define MMU_PAGE_16K 1 |
| 282 | #define MMU_PAGE_64K 2 |
| 283 | #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */ |
| 284 | #define MMU_PAGE_256K 4 |
Christophe Leroy | 4b914286 | 2016-12-07 08:47:28 +0100 | [diff] [blame] | 285 | #define MMU_PAGE_512K 5 |
| 286 | #define MMU_PAGE_1M 6 |
| 287 | #define MMU_PAGE_2M 7 |
| 288 | #define MMU_PAGE_4M 8 |
| 289 | #define MMU_PAGE_8M 9 |
| 290 | #define MMU_PAGE_16M 10 |
| 291 | #define MMU_PAGE_64M 11 |
| 292 | #define MMU_PAGE_256M 12 |
| 293 | #define MMU_PAGE_1G 13 |
| 294 | #define MMU_PAGE_16G 14 |
| 295 | #define MMU_PAGE_64G 15 |
Benjamin Herrenschmidt | 57e2a99 | 2009-07-28 11:59:34 +1000 | [diff] [blame] | 296 | |
Aneesh Kumar K.V | e6f81a9 | 2017-03-29 17:21:53 +1100 | [diff] [blame] | 297 | /* |
| 298 | * N.B. we need to change the type of hpte_page_sizes if this gets to be > 16 |
| 299 | * Also we need to change he type of mm_context.low/high_slices_psize. |
| 300 | */ |
Christophe Leroy | 4b914286 | 2016-12-07 08:47:28 +0100 | [diff] [blame] | 301 | #define MMU_PAGE_COUNT 16 |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 302 | |
Aneesh Kumar K.V | 11a6f6a | 2016-04-29 23:25:41 +1000 | [diff] [blame] | 303 | #ifdef CONFIG_PPC_BOOK3S_64 |
| 304 | #include <asm/book3s/64/mmu.h> |
| 305 | #else /* CONFIG_PPC_BOOK3S_64 */ |
| 306 | |
Aneesh Kumar K.V | 756d08d | 2016-04-29 23:25:57 +1000 | [diff] [blame] | 307 | #ifndef __ASSEMBLY__ |
| 308 | /* MMU initialization */ |
| 309 | extern void early_init_mmu(void); |
| 310 | extern void early_init_mmu_secondary(void); |
| 311 | extern void setup_initial_memory_limit(phys_addr_t first_memblock_base, |
| 312 | phys_addr_t first_memblock_size); |
Michael Ellerman | 1a01dc8 | 2016-07-26 20:09:30 +1000 | [diff] [blame] | 313 | static inline void mmu_early_init_devtree(void) { } |
Aneesh Kumar K.V | 756d08d | 2016-04-29 23:25:57 +1000 | [diff] [blame] | 314 | #endif /* __ASSEMBLY__ */ |
Aneesh Kumar K.V | 11a6f6a | 2016-04-29 23:25:41 +1000 | [diff] [blame] | 315 | #endif |
| 316 | |
| 317 | #if defined(CONFIG_PPC_STD_MMU_32) |
David Gibson | 4db68bf | 2007-06-13 14:52:54 +1000 | [diff] [blame] | 318 | /* 32-bit classic hash table MMU */ |
Aneesh Kumar K.V | f64e808 | 2016-03-01 12:59:20 +0530 | [diff] [blame] | 319 | #include <asm/book3s/32/mmu-hash.h> |
Josh Boyer | 4d922c8 | 2007-08-20 07:28:48 -0500 | [diff] [blame] | 320 | #elif defined(CONFIG_40x) |
| 321 | /* 40x-style software loaded TLB */ |
| 322 | # include <asm/mmu-40x.h> |
David Gibson | 57d7909 | 2007-04-30 14:06:25 +1000 | [diff] [blame] | 323 | #elif defined(CONFIG_44x) |
| 324 | /* 44x-style software loaded TLB */ |
| 325 | # include <asm/mmu-44x.h> |
Kumar Gala | 70fe3af | 2009-02-12 16:12:40 -0600 | [diff] [blame] | 326 | #elif defined(CONFIG_PPC_BOOK3E_MMU) |
| 327 | /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ |
| 328 | # include <asm/mmu-book3e.h> |
David Gibson | 3120234 | 2007-06-22 14:58:55 +1000 | [diff] [blame] | 329 | #elif defined (CONFIG_PPC_8xx) |
| 330 | /* Motorola/Freescale 8xx software loaded TLB */ |
| 331 | # include <asm/mmu-8xx.h> |
David Gibson | 1f8d419 | 2005-05-05 16:15:13 -0700 | [diff] [blame] | 332 | #endif |
David Gibson | 1f8d419 | 2005-05-05 16:15:13 -0700 | [diff] [blame] | 333 | |
Arnd Bergmann | 88ced03 | 2005-12-16 22:43:46 +0100 | [diff] [blame] | 334 | #endif /* __KERNEL__ */ |
Paul Mackerras | 047ea78 | 2005-11-19 20:17:32 +1100 | [diff] [blame] | 335 | #endif /* _ASM_POWERPC_MMU_H_ */ |