Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 1 | /* |
| 2 | * SH7201 setup |
| 3 | * |
| 4 | * Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 5 | * Copyright (C) 2009 Paul Mundt |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 6 | * |
| 7 | * This file is subject to the terms and conditions of the GNU General Public |
| 8 | * License. See the file "COPYING" in the main directory of this archive |
| 9 | * for more details. |
| 10 | */ |
| 11 | #include <linux/platform_device.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/serial.h> |
| 14 | #include <linux/serial_sci.h> |
Paul Mundt | 46a12f7 | 2009-05-03 17:57:17 +0900 | [diff] [blame] | 15 | #include <linux/sh_timer.h> |
Magnus Damm | da107c6 | 2009-04-30 07:06:26 +0000 | [diff] [blame] | 16 | #include <linux/io.h> |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 17 | |
| 18 | enum { |
| 19 | UNUSED = 0, |
| 20 | |
| 21 | /* interrupt sources */ |
| 22 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, |
| 23 | PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 24 | |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 25 | ADC_ADI, |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 26 | |
| 27 | MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU, |
| 28 | MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V, |
| 29 | |
| 30 | RTC, WDT, |
| 31 | |
| 32 | IIC30, IIC31, IIC32, |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 33 | |
| 34 | DMAC0_DMINT0, DMAC1_DMINT1, |
| 35 | DMAC2_DMINT2, DMAC3_DMINT3, |
| 36 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 37 | SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7, |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 38 | |
| 39 | DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6, |
| 40 | DMAC7_DMINT7, |
| 41 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 42 | RCAN0, RCAN1, |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 43 | |
| 44 | SSI0_SSII, SSI1_SSII, |
| 45 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 46 | TMR0, TMR1, |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 47 | |
| 48 | /* interrupt groups */ |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 49 | PINT, |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 50 | }; |
| 51 | |
| 52 | static struct intc_vect vectors[] __initdata = { |
| 53 | INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), |
| 54 | INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), |
| 55 | INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), |
| 56 | INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 57 | |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 58 | INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), |
| 59 | INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), |
| 60 | INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), |
| 61 | INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), |
| 62 | |
| 63 | INTC_IRQ(ADC_ADI, 92), |
| 64 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 65 | INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109), |
| 66 | INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111), |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 67 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 68 | INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113), |
| 69 | INTC_IRQ(MTU20_VEF, 114), |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 70 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 71 | INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117), |
| 72 | INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121), |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 73 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 74 | INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125), |
| 75 | INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129), |
| 76 | |
| 77 | INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133), |
| 78 | INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135), |
| 79 | |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 80 | INTC_IRQ(MTU2_TCI3V, 136), |
| 81 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 82 | INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141), |
| 83 | INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143), |
| 84 | |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 85 | INTC_IRQ(MTU2_TCI4V, 144), |
| 86 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 87 | INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149), |
| 88 | INTC_IRQ(MTU25_UVW, 150), |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 89 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 90 | INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153), |
| 91 | INTC_IRQ(RTC, 154), |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 92 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 93 | INTC_IRQ(WDT, 156), |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 94 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 95 | INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158), |
| 96 | INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160), |
| 97 | INTC_IRQ(IIC30, 161), |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 98 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 99 | INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165), |
| 100 | INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167), |
| 101 | INTC_IRQ(IIC31, 168), |
| 102 | |
| 103 | INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171), |
| 104 | INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173), |
| 105 | INTC_IRQ(IIC32, 174), |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 106 | |
| 107 | INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177), |
| 108 | INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179), |
| 109 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 110 | INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181), |
| 111 | INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183), |
| 112 | INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185), |
| 113 | INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187), |
| 114 | INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189), |
| 115 | INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191), |
| 116 | INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193), |
| 117 | INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195), |
| 118 | INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197), |
| 119 | INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199), |
| 120 | INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201), |
| 121 | INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203), |
| 122 | INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205), |
| 123 | INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207), |
| 124 | INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209), |
| 125 | INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211), |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 126 | |
| 127 | INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216), |
| 128 | INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218), |
| 129 | INTC_IRQ(DMAC7_DMINT7, 219), |
| 130 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 131 | INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229), |
| 132 | INTC_IRQ(RCAN0, 230), |
| 133 | INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232), |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 134 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 135 | INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235), |
| 136 | INTC_IRQ(RCAN1, 236), |
| 137 | INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238), |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 138 | |
| 139 | INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245), |
| 140 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 141 | INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247), |
| 142 | INTC_IRQ(TMR0, 248), |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 143 | |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 144 | INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253), |
| 145 | INTC_IRQ(TMR1, 254), |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 146 | }; |
| 147 | |
| 148 | static struct intc_group groups[] __initdata = { |
| 149 | INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, |
| 150 | PINT4, PINT5, PINT6, PINT7), |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 151 | }; |
| 152 | |
| 153 | static struct intc_prio_reg prio_registers[] __initdata = { |
| 154 | { 0xfffe9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, |
| 155 | { 0xfffe941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, |
| 156 | { 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } }, |
| 157 | { 0xfffe9800, 0, 16, 4, /* IPR06 */ { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } }, |
| 158 | { 0xfffe9802, 0, 16, 4, /* IPR07 */ { MTU21_VU, MTU22_AB, MTU22_VU, MTU23_ABCD } }, |
| 159 | { 0xfffe9804, 0, 16, 4, /* IPR08 */ { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } }, |
| 160 | |
| 161 | { 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } }, |
| 162 | { 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } }, |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 163 | { 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } }, |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 164 | { 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } }, |
| 165 | { 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } }, |
| 166 | { 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } }, |
| 167 | { 0xfffe9812, 0, 16, 4, /* IPR15 */ { 0, RCAN0, RCAN1, 0 } }, |
| 168 | { 0xfffe9814, 0, 16, 4, /* IPR16 */ { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } }, |
| 169 | }; |
| 170 | |
| 171 | static struct intc_mask_reg mask_registers[] __initdata = { |
| 172 | { 0xfffe9408, 0, 16, /* PINTER */ |
| 173 | { 0, 0, 0, 0, 0, 0, 0, 0, |
| 174 | PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, |
| 175 | }; |
| 176 | |
| 177 | static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups, |
| 178 | mask_registers, prio_registers, NULL); |
| 179 | |
Magnus Damm | be091d2 | 2009-12-14 12:29:56 +0000 | [diff] [blame] | 180 | static struct plat_sci_port scif0_platform_data = { |
| 181 | .mapbase = 0xfffe8000, |
| 182 | .flags = UPF_BOOT_AUTOCONF, |
Paul Mundt | f43dc23 | 2011-01-13 15:06:28 +0900 | [diff] [blame] | 183 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 184 | .scbrr_algo_id = SCBRR_ALGO_2, |
Magnus Damm | be091d2 | 2009-12-14 12:29:56 +0000 | [diff] [blame] | 185 | .type = PORT_SCIF, |
| 186 | .irqs = { 180, 180, 180, 180 } |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 187 | }; |
| 188 | |
Magnus Damm | be091d2 | 2009-12-14 12:29:56 +0000 | [diff] [blame] | 189 | static struct platform_device scif0_device = { |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 190 | .name = "sh-sci", |
Magnus Damm | be091d2 | 2009-12-14 12:29:56 +0000 | [diff] [blame] | 191 | .id = 0, |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 192 | .dev = { |
Magnus Damm | be091d2 | 2009-12-14 12:29:56 +0000 | [diff] [blame] | 193 | .platform_data = &scif0_platform_data, |
| 194 | }, |
| 195 | }; |
| 196 | |
| 197 | static struct plat_sci_port scif1_platform_data = { |
| 198 | .mapbase = 0xfffe8800, |
| 199 | .flags = UPF_BOOT_AUTOCONF, |
Paul Mundt | f43dc23 | 2011-01-13 15:06:28 +0900 | [diff] [blame] | 200 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 201 | .scbrr_algo_id = SCBRR_ALGO_2, |
Magnus Damm | be091d2 | 2009-12-14 12:29:56 +0000 | [diff] [blame] | 202 | .type = PORT_SCIF, |
| 203 | .irqs = { 184, 184, 184, 184 } |
| 204 | }; |
| 205 | |
| 206 | static struct platform_device scif1_device = { |
| 207 | .name = "sh-sci", |
| 208 | .id = 1, |
| 209 | .dev = { |
| 210 | .platform_data = &scif1_platform_data, |
| 211 | }, |
| 212 | }; |
| 213 | |
| 214 | static struct plat_sci_port scif2_platform_data = { |
| 215 | .mapbase = 0xfffe9000, |
| 216 | .flags = UPF_BOOT_AUTOCONF, |
Paul Mundt | f43dc23 | 2011-01-13 15:06:28 +0900 | [diff] [blame] | 217 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 218 | .scbrr_algo_id = SCBRR_ALGO_2, |
Magnus Damm | be091d2 | 2009-12-14 12:29:56 +0000 | [diff] [blame] | 219 | .type = PORT_SCIF, |
| 220 | .irqs = { 188, 188, 188, 188 } |
| 221 | }; |
| 222 | |
| 223 | static struct platform_device scif2_device = { |
| 224 | .name = "sh-sci", |
| 225 | .id = 2, |
| 226 | .dev = { |
| 227 | .platform_data = &scif2_platform_data, |
| 228 | }, |
| 229 | }; |
| 230 | |
| 231 | static struct plat_sci_port scif3_platform_data = { |
| 232 | .mapbase = 0xfffe9800, |
| 233 | .flags = UPF_BOOT_AUTOCONF, |
Paul Mundt | f43dc23 | 2011-01-13 15:06:28 +0900 | [diff] [blame] | 234 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 235 | .scbrr_algo_id = SCBRR_ALGO_2, |
Magnus Damm | be091d2 | 2009-12-14 12:29:56 +0000 | [diff] [blame] | 236 | .type = PORT_SCIF, |
| 237 | .irqs = { 192, 192, 192, 192 } |
| 238 | }; |
| 239 | |
| 240 | static struct platform_device scif3_device = { |
| 241 | .name = "sh-sci", |
| 242 | .id = 3, |
| 243 | .dev = { |
| 244 | .platform_data = &scif3_platform_data, |
| 245 | }, |
| 246 | }; |
| 247 | |
| 248 | static struct plat_sci_port scif4_platform_data = { |
| 249 | .mapbase = 0xfffea000, |
| 250 | .flags = UPF_BOOT_AUTOCONF, |
Paul Mundt | f43dc23 | 2011-01-13 15:06:28 +0900 | [diff] [blame] | 251 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 252 | .scbrr_algo_id = SCBRR_ALGO_2, |
Magnus Damm | be091d2 | 2009-12-14 12:29:56 +0000 | [diff] [blame] | 253 | .type = PORT_SCIF, |
| 254 | .irqs = { 196, 196, 196, 196 } |
| 255 | }; |
| 256 | |
| 257 | static struct platform_device scif4_device = { |
| 258 | .name = "sh-sci", |
| 259 | .id = 4, |
| 260 | .dev = { |
| 261 | .platform_data = &scif4_platform_data, |
| 262 | }, |
| 263 | }; |
| 264 | |
| 265 | static struct plat_sci_port scif5_platform_data = { |
| 266 | .mapbase = 0xfffea800, |
| 267 | .flags = UPF_BOOT_AUTOCONF, |
Paul Mundt | f43dc23 | 2011-01-13 15:06:28 +0900 | [diff] [blame] | 268 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 269 | .scbrr_algo_id = SCBRR_ALGO_2, |
Magnus Damm | be091d2 | 2009-12-14 12:29:56 +0000 | [diff] [blame] | 270 | .type = PORT_SCIF, |
| 271 | .irqs = { 200, 200, 200, 200 } |
| 272 | }; |
| 273 | |
| 274 | static struct platform_device scif5_device = { |
| 275 | .name = "sh-sci", |
| 276 | .id = 5, |
| 277 | .dev = { |
| 278 | .platform_data = &scif5_platform_data, |
| 279 | }, |
| 280 | }; |
| 281 | |
| 282 | static struct plat_sci_port scif6_platform_data = { |
| 283 | .mapbase = 0xfffeb000, |
| 284 | .flags = UPF_BOOT_AUTOCONF, |
Paul Mundt | f43dc23 | 2011-01-13 15:06:28 +0900 | [diff] [blame] | 285 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 286 | .scbrr_algo_id = SCBRR_ALGO_2, |
Magnus Damm | be091d2 | 2009-12-14 12:29:56 +0000 | [diff] [blame] | 287 | .type = PORT_SCIF, |
| 288 | .irqs = { 204, 204, 204, 204 } |
| 289 | }; |
| 290 | |
| 291 | static struct platform_device scif6_device = { |
| 292 | .name = "sh-sci", |
| 293 | .id = 6, |
| 294 | .dev = { |
| 295 | .platform_data = &scif6_platform_data, |
| 296 | }, |
| 297 | }; |
| 298 | |
| 299 | static struct plat_sci_port scif7_platform_data = { |
| 300 | .mapbase = 0xfffeb800, |
| 301 | .flags = UPF_BOOT_AUTOCONF, |
Paul Mundt | f43dc23 | 2011-01-13 15:06:28 +0900 | [diff] [blame] | 302 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 303 | .scbrr_algo_id = SCBRR_ALGO_2, |
Magnus Damm | be091d2 | 2009-12-14 12:29:56 +0000 | [diff] [blame] | 304 | .type = PORT_SCIF, |
| 305 | .irqs = { 208, 208, 208, 208 } |
| 306 | }; |
| 307 | |
| 308 | static struct platform_device scif7_device = { |
| 309 | .name = "sh-sci", |
| 310 | .id = 7, |
| 311 | .dev = { |
| 312 | .platform_data = &scif7_platform_data, |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 313 | }, |
| 314 | }; |
| 315 | |
| 316 | static struct resource rtc_resources[] = { |
| 317 | [0] = { |
| 318 | .start = 0xffff0800, |
| 319 | .end = 0xffff2000 + 0x58 - 1, |
| 320 | .flags = IORESOURCE_IO, |
| 321 | }, |
| 322 | [1] = { |
Paul Mundt | d55eedd | 2009-03-06 18:21:38 +0900 | [diff] [blame] | 323 | /* Shared Period/Carry/Alarm IRQ */ |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 324 | .start = 152, |
| 325 | .flags = IORESOURCE_IRQ, |
| 326 | }, |
| 327 | }; |
| 328 | |
| 329 | static struct platform_device rtc_device = { |
| 330 | .name = "sh-rtc", |
| 331 | .id = -1, |
| 332 | .num_resources = ARRAY_SIZE(rtc_resources), |
| 333 | .resource = rtc_resources, |
| 334 | }; |
| 335 | |
Paul Mundt | 46a12f7 | 2009-05-03 17:57:17 +0900 | [diff] [blame] | 336 | static struct sh_timer_config mtu2_0_platform_data = { |
Magnus Damm | da107c6 | 2009-04-30 07:06:26 +0000 | [diff] [blame] | 337 | .channel_offset = -0x80, |
| 338 | .timer_bit = 0, |
Magnus Damm | da107c6 | 2009-04-30 07:06:26 +0000 | [diff] [blame] | 339 | .clockevent_rating = 200, |
| 340 | }; |
| 341 | |
| 342 | static struct resource mtu2_0_resources[] = { |
| 343 | [0] = { |
Magnus Damm | da107c6 | 2009-04-30 07:06:26 +0000 | [diff] [blame] | 344 | .start = 0xfffe4300, |
| 345 | .end = 0xfffe4326, |
| 346 | .flags = IORESOURCE_MEM, |
| 347 | }, |
| 348 | [1] = { |
| 349 | .start = 108, |
| 350 | .flags = IORESOURCE_IRQ, |
| 351 | }, |
| 352 | }; |
| 353 | |
| 354 | static struct platform_device mtu2_0_device = { |
| 355 | .name = "sh_mtu2", |
| 356 | .id = 0, |
| 357 | .dev = { |
| 358 | .platform_data = &mtu2_0_platform_data, |
| 359 | }, |
| 360 | .resource = mtu2_0_resources, |
| 361 | .num_resources = ARRAY_SIZE(mtu2_0_resources), |
| 362 | }; |
| 363 | |
Paul Mundt | 46a12f7 | 2009-05-03 17:57:17 +0900 | [diff] [blame] | 364 | static struct sh_timer_config mtu2_1_platform_data = { |
Magnus Damm | da107c6 | 2009-04-30 07:06:26 +0000 | [diff] [blame] | 365 | .channel_offset = -0x100, |
| 366 | .timer_bit = 1, |
Magnus Damm | da107c6 | 2009-04-30 07:06:26 +0000 | [diff] [blame] | 367 | .clockevent_rating = 200, |
| 368 | }; |
| 369 | |
| 370 | static struct resource mtu2_1_resources[] = { |
| 371 | [0] = { |
Magnus Damm | da107c6 | 2009-04-30 07:06:26 +0000 | [diff] [blame] | 372 | .start = 0xfffe4380, |
| 373 | .end = 0xfffe4390, |
| 374 | .flags = IORESOURCE_MEM, |
| 375 | }, |
| 376 | [1] = { |
| 377 | .start = 116, |
| 378 | .flags = IORESOURCE_IRQ, |
| 379 | }, |
| 380 | }; |
| 381 | |
| 382 | static struct platform_device mtu2_1_device = { |
| 383 | .name = "sh_mtu2", |
| 384 | .id = 1, |
| 385 | .dev = { |
| 386 | .platform_data = &mtu2_1_platform_data, |
| 387 | }, |
| 388 | .resource = mtu2_1_resources, |
| 389 | .num_resources = ARRAY_SIZE(mtu2_1_resources), |
| 390 | }; |
| 391 | |
Paul Mundt | 46a12f7 | 2009-05-03 17:57:17 +0900 | [diff] [blame] | 392 | static struct sh_timer_config mtu2_2_platform_data = { |
Magnus Damm | da107c6 | 2009-04-30 07:06:26 +0000 | [diff] [blame] | 393 | .channel_offset = 0x80, |
| 394 | .timer_bit = 2, |
Magnus Damm | da107c6 | 2009-04-30 07:06:26 +0000 | [diff] [blame] | 395 | .clockevent_rating = 200, |
| 396 | }; |
| 397 | |
| 398 | static struct resource mtu2_2_resources[] = { |
| 399 | [0] = { |
Magnus Damm | da107c6 | 2009-04-30 07:06:26 +0000 | [diff] [blame] | 400 | .start = 0xfffe4000, |
| 401 | .end = 0xfffe400a, |
| 402 | .flags = IORESOURCE_MEM, |
| 403 | }, |
| 404 | [1] = { |
| 405 | .start = 124, |
| 406 | .flags = IORESOURCE_IRQ, |
| 407 | }, |
| 408 | }; |
| 409 | |
| 410 | static struct platform_device mtu2_2_device = { |
| 411 | .name = "sh_mtu2", |
| 412 | .id = 2, |
| 413 | .dev = { |
| 414 | .platform_data = &mtu2_2_platform_data, |
| 415 | }, |
| 416 | .resource = mtu2_2_resources, |
| 417 | .num_resources = ARRAY_SIZE(mtu2_2_resources), |
| 418 | }; |
| 419 | |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 420 | static struct platform_device *sh7201_devices[] __initdata = { |
Magnus Damm | be091d2 | 2009-12-14 12:29:56 +0000 | [diff] [blame] | 421 | &scif0_device, |
| 422 | &scif1_device, |
| 423 | &scif2_device, |
| 424 | &scif3_device, |
| 425 | &scif4_device, |
| 426 | &scif5_device, |
| 427 | &scif6_device, |
| 428 | &scif7_device, |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 429 | &rtc_device, |
Magnus Damm | da107c6 | 2009-04-30 07:06:26 +0000 | [diff] [blame] | 430 | &mtu2_0_device, |
| 431 | &mtu2_1_device, |
| 432 | &mtu2_2_device, |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 433 | }; |
| 434 | |
| 435 | static int __init sh7201_devices_setup(void) |
| 436 | { |
| 437 | return platform_add_devices(sh7201_devices, |
| 438 | ARRAY_SIZE(sh7201_devices)); |
| 439 | } |
Magnus Damm | ba9a633 | 2009-07-22 15:14:29 +0000 | [diff] [blame] | 440 | arch_initcall(sh7201_devices_setup); |
Peter Griffin | 2825999 | 2008-11-28 22:48:20 +0900 | [diff] [blame] | 441 | |
| 442 | void __init plat_irq_setup(void) |
| 443 | { |
| 444 | register_intc_controller(&intc_desc); |
| 445 | } |
Magnus Damm | da107c6 | 2009-04-30 07:06:26 +0000 | [diff] [blame] | 446 | |
| 447 | static struct platform_device *sh7201_early_devices[] __initdata = { |
Magnus Damm | be091d2 | 2009-12-14 12:29:56 +0000 | [diff] [blame] | 448 | &scif0_device, |
| 449 | &scif1_device, |
| 450 | &scif2_device, |
| 451 | &scif3_device, |
| 452 | &scif4_device, |
| 453 | &scif5_device, |
| 454 | &scif6_device, |
| 455 | &scif7_device, |
Magnus Damm | da107c6 | 2009-04-30 07:06:26 +0000 | [diff] [blame] | 456 | &mtu2_0_device, |
| 457 | &mtu2_1_device, |
| 458 | &mtu2_2_device, |
| 459 | }; |
| 460 | |
| 461 | #define STBCR3 0xfffe0408 |
| 462 | |
| 463 | void __init plat_early_device_setup(void) |
| 464 | { |
| 465 | /* enable MTU2 clock */ |
| 466 | __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3); |
| 467 | |
| 468 | early_platform_add_devices(sh7201_early_devices, |
| 469 | ARRAY_SIZE(sh7201_early_devices)); |
| 470 | } |