blob: 8c13479b17cd9d418f7d7f496b01dbf7445ba202 [file] [log] [blame]
Sujithf1dc5602008-10-29 10:16:30 +05301/*
Sujithcee075a2009-03-13 09:07:23 +05302 * Copyright (c) 2008-2009 Atheros Communications Inc.
Sujithf1dc5602008-10-29 10:16:30 +05303 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
Luis R. Rodriguez990b70a2009-09-13 23:55:05 -070017#include "hw.h"
Luis R. Rodriguezac0bb762010-06-12 00:33:42 -040018#include "hw-ops.h"
Sujithf1dc5602008-10-29 10:16:30 +053019
Sujithcbe61d82009-02-09 13:27:12 +053020static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +053021 struct ath9k_tx_queue_info *qi)
22{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -070023 ath_print(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
24 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
25 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
26 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
27 ah->txurn_interrupt_mask);
Sujithf1dc5602008-10-29 10:16:30 +053028
Sujith7d0d0df2010-04-16 11:53:57 +053029 ENABLE_REGWRITE_BUFFER(ah);
30
Sujithf1dc5602008-10-29 10:16:30 +053031 REG_WRITE(ah, AR_IMR_S0,
Sujith2660b812009-02-09 13:27:26 +053032 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
33 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
Sujithf1dc5602008-10-29 10:16:30 +053034 REG_WRITE(ah, AR_IMR_S1,
Sujith2660b812009-02-09 13:27:26 +053035 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
36 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
Pavel Roskin74bad5c2010-02-23 18:15:27 -050037
38 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
39 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
40 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
Sujith7d0d0df2010-04-16 11:53:57 +053041
42 REGWRITE_BUFFER_FLUSH(ah);
Sujithf1dc5602008-10-29 10:16:30 +053043}
44
Sujithcbe61d82009-02-09 13:27:12 +053045u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
Sujithf1dc5602008-10-29 10:16:30 +053046{
47 return REG_READ(ah, AR_QTXDP(q));
48}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040049EXPORT_SYMBOL(ath9k_hw_gettxbuf);
Sujithf1dc5602008-10-29 10:16:30 +053050
Sujith54e4cec2009-08-07 09:45:09 +053051void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
Sujithf1dc5602008-10-29 10:16:30 +053052{
53 REG_WRITE(ah, AR_QTXDP(q), txdp);
Sujithf1dc5602008-10-29 10:16:30 +053054}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040055EXPORT_SYMBOL(ath9k_hw_puttxbuf);
Sujithf1dc5602008-10-29 10:16:30 +053056
Sujith54e4cec2009-08-07 09:45:09 +053057void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
Sujithf1dc5602008-10-29 10:16:30 +053058{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -070059 ath_print(ath9k_hw_common(ah), ATH_DBG_QUEUE,
60 "Enable TXE on queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +053061 REG_WRITE(ah, AR_Q_TXE, 1 << q);
Sujithf1dc5602008-10-29 10:16:30 +053062}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040063EXPORT_SYMBOL(ath9k_hw_txstart);
Sujithf1dc5602008-10-29 10:16:30 +053064
Vasanthakumar Thiagarajancc610ac02010-04-15 17:39:26 -040065void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
66{
67 struct ar5416_desc *ads = AR5416DESC(ds);
68
69 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
70 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
71 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
72 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
73 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
74}
75EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
76
Sujithcbe61d82009-02-09 13:27:12 +053077u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
Sujithf1dc5602008-10-29 10:16:30 +053078{
79 u32 npend;
80
81 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
82 if (npend == 0) {
83
84 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
85 npend = 1;
86 }
87
88 return npend;
89}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040090EXPORT_SYMBOL(ath9k_hw_numtxpending);
Sujithf1dc5602008-10-29 10:16:30 +053091
Luis R. Rodriguezf4709fd2009-11-24 21:37:57 -050092/**
93 * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
94 *
95 * @ah: atheros hardware struct
96 * @bIncTrigLevel: whether or not the frame trigger level should be updated
97 *
98 * The frame trigger level specifies the minimum number of bytes,
99 * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO
100 * before the PCU will initiate sending the frame on the air. This can
101 * mean we initiate transmit before a full frame is on the PCU TX FIFO.
102 * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs
103 * first)
104 *
105 * Caution must be taken to ensure to set the frame trigger level based
106 * on the DMA request size. For example if the DMA request size is set to
107 * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because
108 * there need to be enough space in the tx FIFO for the requested transfer
109 * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set
110 * the threshold to a value beyond 6, then the transmit will hang.
111 *
112 * Current dual stream devices have a PCU TX FIFO size of 8 KB.
113 * Current single stream devices have a PCU TX FIFO size of 4 KB, however,
114 * there is a hardware issue which forces us to use 2 KB instead so the
115 * frame trigger level must not exceed 2 KB for these chipsets.
116 */
Sujithcbe61d82009-02-09 13:27:12 +0530117bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
Sujithf1dc5602008-10-29 10:16:30 +0530118{
Sujithf1dc5602008-10-29 10:16:30 +0530119 u32 txcfg, curLevel, newLevel;
120 enum ath9k_int omask;
121
Luis R. Rodriguezf4709fd2009-11-24 21:37:57 -0500122 if (ah->tx_trig_level >= ah->config.max_txtrig_level)
Sujithf1dc5602008-10-29 10:16:30 +0530123 return false;
124
Pavel Roskin152d5302010-03-31 18:05:37 -0400125 omask = ath9k_hw_set_interrupts(ah, ah->imask & ~ATH9K_INT_GLOBAL);
Sujithf1dc5602008-10-29 10:16:30 +0530126
127 txcfg = REG_READ(ah, AR_TXCFG);
128 curLevel = MS(txcfg, AR_FTRIG);
129 newLevel = curLevel;
130 if (bIncTrigLevel) {
Luis R. Rodriguezf4709fd2009-11-24 21:37:57 -0500131 if (curLevel < ah->config.max_txtrig_level)
Sujithf1dc5602008-10-29 10:16:30 +0530132 newLevel++;
133 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
134 newLevel--;
135 if (newLevel != curLevel)
136 REG_WRITE(ah, AR_TXCFG,
137 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
138
139 ath9k_hw_set_interrupts(ah, omask);
140
Sujith2660b812009-02-09 13:27:26 +0530141 ah->tx_trig_level = newLevel;
Sujithf1dc5602008-10-29 10:16:30 +0530142
143 return newLevel != curLevel;
144}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400145EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
Sujithf1dc5602008-10-29 10:16:30 +0530146
Sujithcbe61d82009-02-09 13:27:12 +0530147bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
Sujithf1dc5602008-10-29 10:16:30 +0530148{
Sujith94ff91d2009-01-27 15:06:38 +0530149#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */
150#define ATH9K_TIME_QUANTUM 100 /* usec */
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700151 struct ath_common *common = ath9k_hw_common(ah);
Sujith2660b812009-02-09 13:27:26 +0530152 struct ath9k_hw_capabilities *pCap = &ah->caps;
Sujith94ff91d2009-01-27 15:06:38 +0530153 struct ath9k_tx_queue_info *qi;
Sujithf1dc5602008-10-29 10:16:30 +0530154 u32 tsfLow, j, wait;
Sujith94ff91d2009-01-27 15:06:38 +0530155 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
156
157 if (q >= pCap->total_queues) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700158 ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
159 "invalid queue: %u\n", q);
Sujith94ff91d2009-01-27 15:06:38 +0530160 return false;
161 }
162
Sujith2660b812009-02-09 13:27:26 +0530163 qi = &ah->txq[q];
Sujith94ff91d2009-01-27 15:06:38 +0530164 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700165 ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
166 "inactive queue: %u\n", q);
Sujith94ff91d2009-01-27 15:06:38 +0530167 return false;
168 }
Sujithf1dc5602008-10-29 10:16:30 +0530169
170 REG_WRITE(ah, AR_Q_TXD, 1 << q);
171
Sujith94ff91d2009-01-27 15:06:38 +0530172 for (wait = wait_time; wait != 0; wait--) {
Sujithf1dc5602008-10-29 10:16:30 +0530173 if (ath9k_hw_numtxpending(ah, q) == 0)
174 break;
Sujith94ff91d2009-01-27 15:06:38 +0530175 udelay(ATH9K_TIME_QUANTUM);
Sujithf1dc5602008-10-29 10:16:30 +0530176 }
177
178 if (ath9k_hw_numtxpending(ah, q)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700179 ath_print(common, ATH_DBG_QUEUE,
180 "%s: Num of pending TX Frames %d on Q %d\n",
181 __func__, ath9k_hw_numtxpending(ah, q), q);
Sujithf1dc5602008-10-29 10:16:30 +0530182
183 for (j = 0; j < 2; j++) {
184 tsfLow = REG_READ(ah, AR_TSF_L32);
185 REG_WRITE(ah, AR_QUIET2,
186 SM(10, AR_QUIET2_QUIET_DUR));
187 REG_WRITE(ah, AR_QUIET_PERIOD, 100);
188 REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
189 REG_SET_BIT(ah, AR_TIMER_MODE,
190 AR_QUIET_TIMER_EN);
191
192 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
193 break;
194
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700195 ath_print(common, ATH_DBG_QUEUE,
196 "TSF has moved while trying to set "
197 "quiet time TSF: 0x%08x\n", tsfLow);
Sujithf1dc5602008-10-29 10:16:30 +0530198 }
199
200 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
201
202 udelay(200);
203 REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
204
Sujith94ff91d2009-01-27 15:06:38 +0530205 wait = wait_time;
Sujithf1dc5602008-10-29 10:16:30 +0530206 while (ath9k_hw_numtxpending(ah, q)) {
207 if ((--wait) == 0) {
Sujithe8009e92009-12-14 14:57:08 +0530208 ath_print(common, ATH_DBG_FATAL,
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700209 "Failed to stop TX DMA in 100 "
210 "msec after killing last frame\n");
Sujithf1dc5602008-10-29 10:16:30 +0530211 break;
212 }
Sujith94ff91d2009-01-27 15:06:38 +0530213 udelay(ATH9K_TIME_QUANTUM);
Sujithf1dc5602008-10-29 10:16:30 +0530214 }
215
216 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
217 }
218
219 REG_WRITE(ah, AR_Q_TXD, 0);
Sujithf1dc5602008-10-29 10:16:30 +0530220 return wait != 0;
Sujith94ff91d2009-01-27 15:06:38 +0530221
222#undef ATH9K_TX_STOP_DMA_TIMEOUT
223#undef ATH9K_TIME_QUANTUM
Sujithf1dc5602008-10-29 10:16:30 +0530224}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400225EXPORT_SYMBOL(ath9k_hw_stoptxdma);
Sujithf1dc5602008-10-29 10:16:30 +0530226
Sujithcbe61d82009-02-09 13:27:12 +0530227void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
Sujithf1dc5602008-10-29 10:16:30 +0530228{
Sujith2660b812009-02-09 13:27:26 +0530229 *txqs &= ah->intr_txqs;
230 ah->intr_txqs &= ~(*txqs);
Sujithf1dc5602008-10-29 10:16:30 +0530231}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400232EXPORT_SYMBOL(ath9k_hw_gettxintrtxqs);
Sujithf1dc5602008-10-29 10:16:30 +0530233
Sujithcbe61d82009-02-09 13:27:12 +0530234bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
Sujithf1dc5602008-10-29 10:16:30 +0530235 const struct ath9k_tx_queue_info *qinfo)
236{
237 u32 cw;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700238 struct ath_common *common = ath9k_hw_common(ah);
Sujith2660b812009-02-09 13:27:26 +0530239 struct ath9k_hw_capabilities *pCap = &ah->caps;
Sujithf1dc5602008-10-29 10:16:30 +0530240 struct ath9k_tx_queue_info *qi;
241
242 if (q >= pCap->total_queues) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700243 ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
244 "invalid queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530245 return false;
246 }
247
Sujith2660b812009-02-09 13:27:26 +0530248 qi = &ah->txq[q];
Sujithf1dc5602008-10-29 10:16:30 +0530249 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700250 ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
251 "inactive queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530252 return false;
253 }
254
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700255 ath_print(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530256
257 qi->tqi_ver = qinfo->tqi_ver;
258 qi->tqi_subtype = qinfo->tqi_subtype;
259 qi->tqi_qflags = qinfo->tqi_qflags;
260 qi->tqi_priority = qinfo->tqi_priority;
261 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
262 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
263 else
264 qi->tqi_aifs = INIT_AIFS;
265 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
266 cw = min(qinfo->tqi_cwmin, 1024U);
267 qi->tqi_cwmin = 1;
268 while (qi->tqi_cwmin < cw)
269 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
270 } else
271 qi->tqi_cwmin = qinfo->tqi_cwmin;
272 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
273 cw = min(qinfo->tqi_cwmax, 1024U);
274 qi->tqi_cwmax = 1;
275 while (qi->tqi_cwmax < cw)
276 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
277 } else
278 qi->tqi_cwmax = INIT_CWMAX;
279
280 if (qinfo->tqi_shretry != 0)
281 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
282 else
283 qi->tqi_shretry = INIT_SH_RETRY;
284 if (qinfo->tqi_lgretry != 0)
285 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
286 else
287 qi->tqi_lgretry = INIT_LG_RETRY;
288 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
289 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
290 qi->tqi_burstTime = qinfo->tqi_burstTime;
291 qi->tqi_readyTime = qinfo->tqi_readyTime;
292
293 switch (qinfo->tqi_subtype) {
294 case ATH9K_WME_UPSD:
295 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
296 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
297 break;
298 default:
299 break;
300 }
301
302 return true;
303}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400304EXPORT_SYMBOL(ath9k_hw_set_txq_props);
Sujithf1dc5602008-10-29 10:16:30 +0530305
Sujithcbe61d82009-02-09 13:27:12 +0530306bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
Sujithf1dc5602008-10-29 10:16:30 +0530307 struct ath9k_tx_queue_info *qinfo)
308{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700309 struct ath_common *common = ath9k_hw_common(ah);
Sujith2660b812009-02-09 13:27:26 +0530310 struct ath9k_hw_capabilities *pCap = &ah->caps;
Sujithf1dc5602008-10-29 10:16:30 +0530311 struct ath9k_tx_queue_info *qi;
312
313 if (q >= pCap->total_queues) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700314 ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
315 "invalid queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530316 return false;
317 }
318
Sujith2660b812009-02-09 13:27:26 +0530319 qi = &ah->txq[q];
Sujithf1dc5602008-10-29 10:16:30 +0530320 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700321 ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
322 "inactive queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530323 return false;
324 }
325
326 qinfo->tqi_qflags = qi->tqi_qflags;
327 qinfo->tqi_ver = qi->tqi_ver;
328 qinfo->tqi_subtype = qi->tqi_subtype;
329 qinfo->tqi_qflags = qi->tqi_qflags;
330 qinfo->tqi_priority = qi->tqi_priority;
331 qinfo->tqi_aifs = qi->tqi_aifs;
332 qinfo->tqi_cwmin = qi->tqi_cwmin;
333 qinfo->tqi_cwmax = qi->tqi_cwmax;
334 qinfo->tqi_shretry = qi->tqi_shretry;
335 qinfo->tqi_lgretry = qi->tqi_lgretry;
336 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
337 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
338 qinfo->tqi_burstTime = qi->tqi_burstTime;
339 qinfo->tqi_readyTime = qi->tqi_readyTime;
340
341 return true;
342}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400343EXPORT_SYMBOL(ath9k_hw_get_txq_props);
Sujithf1dc5602008-10-29 10:16:30 +0530344
Sujithcbe61d82009-02-09 13:27:12 +0530345int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
Sujithf1dc5602008-10-29 10:16:30 +0530346 const struct ath9k_tx_queue_info *qinfo)
347{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700348 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530349 struct ath9k_tx_queue_info *qi;
Sujith2660b812009-02-09 13:27:26 +0530350 struct ath9k_hw_capabilities *pCap = &ah->caps;
Sujithf1dc5602008-10-29 10:16:30 +0530351 int q;
352
353 switch (type) {
354 case ATH9K_TX_QUEUE_BEACON:
355 q = pCap->total_queues - 1;
356 break;
357 case ATH9K_TX_QUEUE_CAB:
358 q = pCap->total_queues - 2;
359 break;
360 case ATH9K_TX_QUEUE_PSPOLL:
361 q = 1;
362 break;
363 case ATH9K_TX_QUEUE_UAPSD:
364 q = pCap->total_queues - 3;
365 break;
366 case ATH9K_TX_QUEUE_DATA:
367 for (q = 0; q < pCap->total_queues; q++)
Sujith2660b812009-02-09 13:27:26 +0530368 if (ah->txq[q].tqi_type ==
Sujithf1dc5602008-10-29 10:16:30 +0530369 ATH9K_TX_QUEUE_INACTIVE)
370 break;
371 if (q == pCap->total_queues) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700372 ath_print(common, ATH_DBG_FATAL,
373 "No available TX queue\n");
Sujithf1dc5602008-10-29 10:16:30 +0530374 return -1;
375 }
376 break;
377 default:
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700378 ath_print(common, ATH_DBG_FATAL,
379 "Invalid TX queue type: %u\n", type);
Sujithf1dc5602008-10-29 10:16:30 +0530380 return -1;
381 }
382
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700383 ath_print(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530384
Sujith2660b812009-02-09 13:27:26 +0530385 qi = &ah->txq[q];
Sujithf1dc5602008-10-29 10:16:30 +0530386 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700387 ath_print(common, ATH_DBG_FATAL,
388 "TX queue: %u already active\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530389 return -1;
390 }
391 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
392 qi->tqi_type = type;
393 if (qinfo == NULL) {
394 qi->tqi_qflags =
395 TXQ_FLAG_TXOKINT_ENABLE
396 | TXQ_FLAG_TXERRINT_ENABLE
397 | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
398 qi->tqi_aifs = INIT_AIFS;
399 qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
400 qi->tqi_cwmax = INIT_CWMAX;
401 qi->tqi_shretry = INIT_SH_RETRY;
402 qi->tqi_lgretry = INIT_LG_RETRY;
403 qi->tqi_physCompBuf = 0;
404 } else {
405 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
406 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
407 }
408
409 return q;
410}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400411EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
Sujithf1dc5602008-10-29 10:16:30 +0530412
Sujithcbe61d82009-02-09 13:27:12 +0530413bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
Sujithf1dc5602008-10-29 10:16:30 +0530414{
Sujith2660b812009-02-09 13:27:26 +0530415 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700416 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530417 struct ath9k_tx_queue_info *qi;
418
419 if (q >= pCap->total_queues) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700420 ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
421 "invalid queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530422 return false;
423 }
Sujith2660b812009-02-09 13:27:26 +0530424 qi = &ah->txq[q];
Sujithf1dc5602008-10-29 10:16:30 +0530425 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700426 ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
427 "inactive queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530428 return false;
429 }
430
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700431 ath_print(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530432
433 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
Sujith2660b812009-02-09 13:27:26 +0530434 ah->txok_interrupt_mask &= ~(1 << q);
435 ah->txerr_interrupt_mask &= ~(1 << q);
436 ah->txdesc_interrupt_mask &= ~(1 << q);
437 ah->txeol_interrupt_mask &= ~(1 << q);
438 ah->txurn_interrupt_mask &= ~(1 << q);
Sujithf1dc5602008-10-29 10:16:30 +0530439 ath9k_hw_set_txq_interrupts(ah, qi);
440
441 return true;
442}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400443EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
Sujithf1dc5602008-10-29 10:16:30 +0530444
Sujithcbe61d82009-02-09 13:27:12 +0530445bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
Sujithf1dc5602008-10-29 10:16:30 +0530446{
Sujith2660b812009-02-09 13:27:26 +0530447 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700448 struct ath_common *common = ath9k_hw_common(ah);
Sujith2660b812009-02-09 13:27:26 +0530449 struct ath9k_channel *chan = ah->curchan;
Sujithf1dc5602008-10-29 10:16:30 +0530450 struct ath9k_tx_queue_info *qi;
451 u32 cwMin, chanCwMin, value;
452
453 if (q >= pCap->total_queues) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700454 ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
455 "invalid queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530456 return false;
457 }
458
Sujith2660b812009-02-09 13:27:26 +0530459 qi = &ah->txq[q];
Sujithf1dc5602008-10-29 10:16:30 +0530460 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700461 ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
462 "inactive queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530463 return true;
464 }
465
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700466 ath_print(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530467
468 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
469 if (chan && IS_CHAN_B(chan))
470 chanCwMin = INIT_CWMIN_11B;
471 else
472 chanCwMin = INIT_CWMIN;
473
474 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
475 } else
476 cwMin = qi->tqi_cwmin;
477
Sujith7d0d0df2010-04-16 11:53:57 +0530478 ENABLE_REGWRITE_BUFFER(ah);
479
Sujithf1dc5602008-10-29 10:16:30 +0530480 REG_WRITE(ah, AR_DLCL_IFS(q),
481 SM(cwMin, AR_D_LCL_IFS_CWMIN) |
482 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
483 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
484
485 REG_WRITE(ah, AR_DRETRY_LIMIT(q),
486 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
487 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
488 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
489
490 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
491 REG_WRITE(ah, AR_DMISC(q),
492 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
493
494 if (qi->tqi_cbrPeriod) {
495 REG_WRITE(ah, AR_QCBRCFG(q),
496 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
497 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
498 REG_WRITE(ah, AR_QMISC(q),
499 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |
500 (qi->tqi_cbrOverflowLimit ?
501 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
502 }
503 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
504 REG_WRITE(ah, AR_QRDYTIMECFG(q),
505 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
506 AR_Q_RDYTIMECFG_EN);
507 }
508
509 REG_WRITE(ah, AR_DCHNTIME(q),
510 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
511 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
512
513 if (qi->tqi_burstTime
514 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
515 REG_WRITE(ah, AR_QMISC(q),
516 REG_READ(ah, AR_QMISC(q)) |
517 AR_Q_MISC_RDYTIME_EXP_POLICY);
518
519 }
520
521 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
522 REG_WRITE(ah, AR_DMISC(q),
523 REG_READ(ah, AR_DMISC(q)) |
524 AR_D_MISC_POST_FR_BKOFF_DIS);
525 }
Sujith7d0d0df2010-04-16 11:53:57 +0530526
527 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +0530528
Sujithf1dc5602008-10-29 10:16:30 +0530529 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
530 REG_WRITE(ah, AR_DMISC(q),
531 REG_READ(ah, AR_DMISC(q)) |
532 AR_D_MISC_FRAG_BKOFF_EN);
533 }
534 switch (qi->tqi_type) {
535 case ATH9K_TX_QUEUE_BEACON:
Sujith7d0d0df2010-04-16 11:53:57 +0530536 ENABLE_REGWRITE_BUFFER(ah);
537
Sujithf1dc5602008-10-29 10:16:30 +0530538 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
539 | AR_Q_MISC_FSP_DBA_GATED
540 | AR_Q_MISC_BEACON_USE
541 | AR_Q_MISC_CBR_INCR_DIS1);
542
543 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
544 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
545 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
546 | AR_D_MISC_BEACON_USE
547 | AR_D_MISC_POST_FR_BKOFF_DIS);
Sujith7d0d0df2010-04-16 11:53:57 +0530548
549 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +0530550
Luis R. Rodriguez9a2af882010-06-14 20:17:36 -0400551 /*
552 * cwmin and cwmax should be 0 for beacon queue
553 * but not for IBSS as we would create an imbalance
554 * on beaconing fairness for participating nodes.
555 */
556 if (AR_SREV_9300_20_OR_LATER(ah) &&
557 ah->opmode != NL80211_IFTYPE_ADHOC) {
Luis R. Rodriguez3deb4da2010-04-15 17:39:32 -0400558 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
559 | SM(0, AR_D_LCL_IFS_CWMAX)
560 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
561 }
Sujithf1dc5602008-10-29 10:16:30 +0530562 break;
563 case ATH9K_TX_QUEUE_CAB:
Sujith7d0d0df2010-04-16 11:53:57 +0530564 ENABLE_REGWRITE_BUFFER(ah);
565
Sujithf1dc5602008-10-29 10:16:30 +0530566 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
567 | AR_Q_MISC_FSP_DBA_GATED
568 | AR_Q_MISC_CBR_INCR_DIS1
569 | AR_Q_MISC_CBR_INCR_DIS0);
570 value = (qi->tqi_readyTime -
Sujith2660b812009-02-09 13:27:26 +0530571 (ah->config.sw_beacon_response_time -
572 ah->config.dma_beacon_response_time) -
573 ah->config.additional_swba_backoff) * 1024;
Sujithf1dc5602008-10-29 10:16:30 +0530574 REG_WRITE(ah, AR_QRDYTIMECFG(q),
575 value | AR_Q_RDYTIMECFG_EN);
576 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
577 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
578 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
Sujith7d0d0df2010-04-16 11:53:57 +0530579
580 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +0530581
Sujithf1dc5602008-10-29 10:16:30 +0530582 break;
583 case ATH9K_TX_QUEUE_PSPOLL:
584 REG_WRITE(ah, AR_QMISC(q),
585 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
586 break;
587 case ATH9K_TX_QUEUE_UAPSD:
588 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
589 AR_D_MISC_POST_FR_BKOFF_DIS);
590 break;
591 default:
592 break;
593 }
594
595 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
596 REG_WRITE(ah, AR_DMISC(q),
597 REG_READ(ah, AR_DMISC(q)) |
598 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
599 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
600 AR_D_MISC_POST_FR_BKOFF_DIS);
601 }
602
Luis R. Rodriguez79de2372010-04-15 17:39:31 -0400603 if (AR_SREV_9300_20_OR_LATER(ah))
604 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
605
Sujithf1dc5602008-10-29 10:16:30 +0530606 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
Sujith2660b812009-02-09 13:27:26 +0530607 ah->txok_interrupt_mask |= 1 << q;
Sujithf1dc5602008-10-29 10:16:30 +0530608 else
Sujith2660b812009-02-09 13:27:26 +0530609 ah->txok_interrupt_mask &= ~(1 << q);
Sujithf1dc5602008-10-29 10:16:30 +0530610 if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
Sujith2660b812009-02-09 13:27:26 +0530611 ah->txerr_interrupt_mask |= 1 << q;
Sujithf1dc5602008-10-29 10:16:30 +0530612 else
Sujith2660b812009-02-09 13:27:26 +0530613 ah->txerr_interrupt_mask &= ~(1 << q);
Sujithf1dc5602008-10-29 10:16:30 +0530614 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
Sujith2660b812009-02-09 13:27:26 +0530615 ah->txdesc_interrupt_mask |= 1 << q;
Sujithf1dc5602008-10-29 10:16:30 +0530616 else
Sujith2660b812009-02-09 13:27:26 +0530617 ah->txdesc_interrupt_mask &= ~(1 << q);
Sujithf1dc5602008-10-29 10:16:30 +0530618 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
Sujith2660b812009-02-09 13:27:26 +0530619 ah->txeol_interrupt_mask |= 1 << q;
Sujithf1dc5602008-10-29 10:16:30 +0530620 else
Sujith2660b812009-02-09 13:27:26 +0530621 ah->txeol_interrupt_mask &= ~(1 << q);
Sujithf1dc5602008-10-29 10:16:30 +0530622 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
Sujith2660b812009-02-09 13:27:26 +0530623 ah->txurn_interrupt_mask |= 1 << q;
Sujithf1dc5602008-10-29 10:16:30 +0530624 else
Sujith2660b812009-02-09 13:27:26 +0530625 ah->txurn_interrupt_mask &= ~(1 << q);
Sujithf1dc5602008-10-29 10:16:30 +0530626 ath9k_hw_set_txq_interrupts(ah, qi);
627
628 return true;
629}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400630EXPORT_SYMBOL(ath9k_hw_resettxqueue);
Sujithf1dc5602008-10-29 10:16:30 +0530631
Sujithcbe61d82009-02-09 13:27:12 +0530632int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700633 struct ath_rx_status *rs, u64 tsf)
Sujithf1dc5602008-10-29 10:16:30 +0530634{
635 struct ar5416_desc ads;
636 struct ar5416_desc *adsp = AR5416DESC(ds);
637 u32 phyerr;
638
639 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
640 return -EINPROGRESS;
641
642 ads.u.rx = adsp->u.rx;
643
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700644 rs->rs_status = 0;
645 rs->rs_flags = 0;
Sujithf1dc5602008-10-29 10:16:30 +0530646
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700647 rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
648 rs->rs_tstamp = ads.AR_RcvTimestamp;
Sujithf1dc5602008-10-29 10:16:30 +0530649
Senthil Balasubramaniandd8b15b2009-07-14 20:17:08 -0400650 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700651 rs->rs_rssi = ATH9K_RSSI_BAD;
652 rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
653 rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
654 rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
655 rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
656 rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
657 rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
Senthil Balasubramaniandd8b15b2009-07-14 20:17:08 -0400658 } else {
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700659 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
660 rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
Senthil Balasubramaniandd8b15b2009-07-14 20:17:08 -0400661 AR_RxRSSIAnt00);
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700662 rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
Senthil Balasubramaniandd8b15b2009-07-14 20:17:08 -0400663 AR_RxRSSIAnt01);
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700664 rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
Senthil Balasubramaniandd8b15b2009-07-14 20:17:08 -0400665 AR_RxRSSIAnt02);
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700666 rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
Senthil Balasubramaniandd8b15b2009-07-14 20:17:08 -0400667 AR_RxRSSIAnt10);
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700668 rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
Senthil Balasubramaniandd8b15b2009-07-14 20:17:08 -0400669 AR_RxRSSIAnt11);
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700670 rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
Senthil Balasubramaniandd8b15b2009-07-14 20:17:08 -0400671 AR_RxRSSIAnt12);
672 }
Sujithf1dc5602008-10-29 10:16:30 +0530673 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700674 rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
Sujithf1dc5602008-10-29 10:16:30 +0530675 else
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700676 rs->rs_keyix = ATH9K_RXKEYIX_INVALID;
Sujithf1dc5602008-10-29 10:16:30 +0530677
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700678 rs->rs_rate = RXSTATUS_RATE(ah, (&ads));
679 rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
Sujithf1dc5602008-10-29 10:16:30 +0530680
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700681 rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
682 rs->rs_moreaggr =
Sujithf1dc5602008-10-29 10:16:30 +0530683 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700684 rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
685 rs->rs_flags =
Sujithf1dc5602008-10-29 10:16:30 +0530686 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700687 rs->rs_flags |=
Sujithf1dc5602008-10-29 10:16:30 +0530688 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
689
690 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700691 rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
Sujithf1dc5602008-10-29 10:16:30 +0530692 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700693 rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
Sujithf1dc5602008-10-29 10:16:30 +0530694 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700695 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
Sujithf1dc5602008-10-29 10:16:30 +0530696
697 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
698 if (ads.ds_rxstatus8 & AR_CRCErr)
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700699 rs->rs_status |= ATH9K_RXERR_CRC;
Sujithf1dc5602008-10-29 10:16:30 +0530700 else if (ads.ds_rxstatus8 & AR_PHYErr) {
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700701 rs->rs_status |= ATH9K_RXERR_PHY;
Sujithf1dc5602008-10-29 10:16:30 +0530702 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700703 rs->rs_phyerr = phyerr;
Sujithf1dc5602008-10-29 10:16:30 +0530704 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700705 rs->rs_status |= ATH9K_RXERR_DECRYPT;
Felix Fietkau56363dd2010-08-28 18:21:21 +0200706 else if ((ads.ds_rxstatus8 & AR_MichaelErr) &&
707 rs->rs_keyix != ATH9K_RXKEYIX_INVALID)
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700708 rs->rs_status |= ATH9K_RXERR_MIC;
Felix Fietkau3ae74c32010-09-14 18:38:26 +0200709 else if (ads.ds_rxstatus8 & AR_KeyMiss)
710 rs->rs_status |= ATH9K_RXERR_DECRYPT;
Sujithf1dc5602008-10-29 10:16:30 +0530711 }
712
713 return 0;
714}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400715EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
Sujithf1dc5602008-10-29 10:16:30 +0530716
Luis R. Rodrigueze7824a52009-11-24 02:53:25 -0500717/*
718 * This can stop or re-enables RX.
719 *
720 * If bool is set this will kill any frame which is currently being
721 * transferred between the MAC and baseband and also prevent any new
722 * frames from getting started.
723 */
Sujithcbe61d82009-02-09 13:27:12 +0530724bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
Sujithf1dc5602008-10-29 10:16:30 +0530725{
726 u32 reg;
727
728 if (set) {
729 REG_SET_BIT(ah, AR_DIAG_SW,
730 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
731
Sujith0caa7b12009-02-16 13:23:20 +0530732 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
733 0, AH_WAIT_TIMEOUT)) {
Sujithf1dc5602008-10-29 10:16:30 +0530734 REG_CLR_BIT(ah, AR_DIAG_SW,
735 (AR_DIAG_RX_DIS |
736 AR_DIAG_RX_ABORT));
737
738 reg = REG_READ(ah, AR_OBS_BUS_1);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700739 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
740 "RX failed to go idle in 10 ms RXSM=0x%x\n",
741 reg);
Sujithf1dc5602008-10-29 10:16:30 +0530742
743 return false;
744 }
745 } else {
746 REG_CLR_BIT(ah, AR_DIAG_SW,
747 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
748 }
749
750 return true;
751}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400752EXPORT_SYMBOL(ath9k_hw_setrxabort);
Sujithf1dc5602008-10-29 10:16:30 +0530753
Sujithcbe61d82009-02-09 13:27:12 +0530754void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
Sujithf1dc5602008-10-29 10:16:30 +0530755{
756 REG_WRITE(ah, AR_RXDP, rxdp);
757}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400758EXPORT_SYMBOL(ath9k_hw_putrxbuf);
Sujithf1dc5602008-10-29 10:16:30 +0530759
Luis R. Rodriguez40346b62010-06-12 00:33:44 -0400760void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
Sujithf1dc5602008-10-29 10:16:30 +0530761{
Sujithf1dc5602008-10-29 10:16:30 +0530762 ath9k_enable_mib_counters(ah);
763
Luis R. Rodriguez40346b62010-06-12 00:33:44 -0400764 ath9k_ani_reset(ah, is_scanning);
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530765
Senthil Balasubramanian8aa15e12008-12-08 19:43:50 +0530766 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
Sujithf1dc5602008-10-29 10:16:30 +0530767}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400768EXPORT_SYMBOL(ath9k_hw_startpcureceive);
Sujithf1dc5602008-10-29 10:16:30 +0530769
Sujithcbe61d82009-02-09 13:27:12 +0530770void ath9k_hw_stoppcurecv(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530771{
772 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
773
774 ath9k_hw_disable_mib_counters(ah);
775}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400776EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
Sujithf1dc5602008-10-29 10:16:30 +0530777
Vasanthakumar Thiagarajan9b9cc612010-04-15 17:39:41 -0400778void ath9k_hw_abortpcurecv(struct ath_hw *ah)
779{
780 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
781
782 ath9k_hw_disable_mib_counters(ah);
783}
784EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
785
Sujithcbe61d82009-02-09 13:27:12 +0530786bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530787{
Sujith0caa7b12009-02-16 13:23:20 +0530788#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
789#define AH_RX_TIME_QUANTUM 100 /* usec */
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700790 struct ath_common *common = ath9k_hw_common(ah);
Sujith0caa7b12009-02-16 13:23:20 +0530791 int i;
792
Sujithf1dc5602008-10-29 10:16:30 +0530793 REG_WRITE(ah, AR_CR, AR_CR_RXD);
794
Sujith0caa7b12009-02-16 13:23:20 +0530795 /* Wait for rx enable bit to go low */
796 for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
797 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
798 break;
799 udelay(AH_TIME_QUANTUM);
800 }
801
802 if (i == 0) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700803 ath_print(common, ATH_DBG_FATAL,
804 "DMA failed to stop in %d ms "
805 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
806 AH_RX_STOP_DMA_TIMEOUT / 1000,
807 REG_READ(ah, AR_CR),
808 REG_READ(ah, AR_DIAG_SW));
Sujithf1dc5602008-10-29 10:16:30 +0530809 return false;
810 } else {
811 return true;
812 }
Sujith0caa7b12009-02-16 13:23:20 +0530813
814#undef AH_RX_TIME_QUANTUM
815#undef AH_RX_STOP_DMA_TIMEOUT
Sujithf1dc5602008-10-29 10:16:30 +0530816}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400817EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
Luis R. Rodriguez536b3a72009-10-06 21:19:11 -0400818
819int ath9k_hw_beaconq_setup(struct ath_hw *ah)
820{
821 struct ath9k_tx_queue_info qi;
822
823 memset(&qi, 0, sizeof(qi));
824 qi.tqi_aifs = 1;
825 qi.tqi_cwmin = 0;
826 qi.tqi_cwmax = 0;
827 /* NB: don't enable any interrupts */
828 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
829}
830EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -0400831
832bool ath9k_hw_intrpend(struct ath_hw *ah)
833{
834 u32 host_isr;
835
836 if (AR_SREV_9100(ah))
837 return true;
838
839 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
840 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
841 return true;
842
843 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
844 if ((host_isr & AR_INTR_SYNC_DEFAULT)
845 && (host_isr != AR_INTR_SPURIOUS))
846 return true;
847
848 return false;
849}
850EXPORT_SYMBOL(ath9k_hw_intrpend);
851
852enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
853 enum ath9k_int ints)
854{
855 enum ath9k_int omask = ah->imask;
856 u32 mask, mask2;
857 struct ath9k_hw_capabilities *pCap = &ah->caps;
858 struct ath_common *common = ath9k_hw_common(ah);
859
860 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
861
862 if (omask & ATH9K_INT_GLOBAL) {
863 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
864 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
865 (void) REG_READ(ah, AR_IER);
866 if (!AR_SREV_9100(ah)) {
867 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
868 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
869
870 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
871 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
872 }
873 }
874
875 /* TODO: global int Ref count */
876 mask = ints & ATH9K_INT_COMMON;
877 mask2 = 0;
878
879 if (ints & ATH9K_INT_TX) {
880 if (ah->config.tx_intr_mitigation)
881 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
Luis R. Rodriguez5bea4002010-04-26 15:04:41 -0400882 else {
883 if (ah->txok_interrupt_mask)
884 mask |= AR_IMR_TXOK;
885 if (ah->txdesc_interrupt_mask)
886 mask |= AR_IMR_TXDESC;
887 }
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -0400888 if (ah->txerr_interrupt_mask)
889 mask |= AR_IMR_TXERR;
890 if (ah->txeol_interrupt_mask)
891 mask |= AR_IMR_TXEOL;
892 }
893 if (ints & ATH9K_INT_RX) {
894 if (AR_SREV_9300_20_OR_LATER(ah)) {
895 mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
896 if (ah->config.rx_intr_mitigation) {
897 mask &= ~AR_IMR_RXOK_LP;
898 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
899 } else {
900 mask |= AR_IMR_RXOK_LP;
901 }
902 } else {
903 if (ah->config.rx_intr_mitigation)
904 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
905 else
906 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
907 }
908 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
909 mask |= AR_IMR_GENTMR;
910 }
911
912 if (ints & (ATH9K_INT_BMISC)) {
913 mask |= AR_IMR_BCNMISC;
914 if (ints & ATH9K_INT_TIM)
915 mask2 |= AR_IMR_S2_TIM;
916 if (ints & ATH9K_INT_DTIM)
917 mask2 |= AR_IMR_S2_DTIM;
918 if (ints & ATH9K_INT_DTIMSYNC)
919 mask2 |= AR_IMR_S2_DTIMSYNC;
920 if (ints & ATH9K_INT_CABEND)
921 mask2 |= AR_IMR_S2_CABEND;
922 if (ints & ATH9K_INT_TSFOOR)
923 mask2 |= AR_IMR_S2_TSFOOR;
924 }
925
926 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
927 mask |= AR_IMR_BCNMISC;
928 if (ints & ATH9K_INT_GTT)
929 mask2 |= AR_IMR_S2_GTT;
930 if (ints & ATH9K_INT_CST)
931 mask2 |= AR_IMR_S2_CST;
932 }
933
934 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
935 REG_WRITE(ah, AR_IMR, mask);
936 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
937 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
938 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
939 ah->imrs2_reg |= mask2;
940 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
941
942 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
943 if (ints & ATH9K_INT_TIM_TIMER)
944 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
945 else
946 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
947 }
948
949 if (ints & ATH9K_INT_GLOBAL) {
950 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
951 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
952 if (!AR_SREV_9100(ah)) {
953 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
954 AR_INTR_MAC_IRQ);
955 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
956
957
958 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
959 AR_INTR_SYNC_DEFAULT);
960 REG_WRITE(ah, AR_INTR_SYNC_MASK,
961 AR_INTR_SYNC_DEFAULT);
962 }
963 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
964 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
965 }
966
967 return omask;
968}
969EXPORT_SYMBOL(ath9k_hw_set_interrupts);