Adrian Bunk | 88278ca | 2008-05-19 16:53:02 -0700 | [diff] [blame] | 1 | /* |
Sam Ravnborg | e54f854 | 2011-01-28 22:08:21 +0000 | [diff] [blame] | 2 | * SS1000/SC2000 interrupt handling. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) |
| 5 | * Heavily based on arch/sparc/kernel/irq.c. |
| 6 | */ |
| 7 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | #include <linux/kernel_stat.h> |
David Howells | 0d01ff2 | 2013-04-11 23:51:01 +0100 | [diff] [blame] | 9 | #include <linux/slab.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | #include <linux/seq_file.h> |
| 11 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | #include <asm/timer.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | #include <asm/traps.h> |
| 14 | #include <asm/irq.h> |
| 15 | #include <asm/io.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | #include <asm/sbi.h> |
| 17 | #include <asm/cacheflush.h> |
Daniel Hellstrom | 5fcafb7 | 2011-04-21 04:20:23 +0000 | [diff] [blame] | 18 | #include <asm/setup.h> |
David S. Miller | 5d83d66 | 2012-05-13 20:49:31 -0700 | [diff] [blame] | 19 | #include <asm/oplib.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | |
Sam Ravnborg | 81265fd | 2008-12-08 01:08:24 -0800 | [diff] [blame] | 21 | #include "kernel.h" |
Al Viro | 32231a6 | 2007-07-21 19:18:57 -0700 | [diff] [blame] | 22 | #include "irq.h" |
| 23 | |
Sam Ravnborg | e54f854 | 2011-01-28 22:08:21 +0000 | [diff] [blame] | 24 | /* Sun4d interrupts fall roughly into two categories. SBUS and |
| 25 | * cpu local. CPU local interrupts cover the timer interrupts |
| 26 | * and whatnot, and we encode those as normal PILs between |
| 27 | * 0 and 15. |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 28 | * SBUS interrupts are encodes as a combination of board, level and slot. |
Sam Ravnborg | e54f854 | 2011-01-28 22:08:21 +0000 | [diff] [blame] | 29 | */ |
| 30 | |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 31 | struct sun4d_handler_data { |
| 32 | unsigned int cpuid; /* target cpu */ |
| 33 | unsigned int real_irq; /* interrupt level */ |
| 34 | }; |
| 35 | |
| 36 | |
| 37 | static unsigned int sun4d_encode_irq(int board, int lvl, int slot) |
| 38 | { |
| 39 | return (board + 1) << 5 | (lvl << 2) | slot; |
| 40 | } |
| 41 | |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 42 | struct sun4d_timer_regs { |
| 43 | u32 l10_timer_limit; |
| 44 | u32 l10_cur_countx; |
| 45 | u32 l10_limit_noclear; |
| 46 | u32 ctrl; |
| 47 | u32 l10_cur_count; |
| 48 | }; |
| 49 | |
| 50 | static struct sun4d_timer_regs __iomem *sun4d_timers; |
| 51 | |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 52 | #define SUN4D_TIMER_IRQ 10 |
Sam Ravnborg | db1cdd1 | 2011-04-18 11:25:42 +0000 | [diff] [blame] | 53 | |
| 54 | /* Specify which cpu handle interrupts from which board. |
| 55 | * Index is board - value is cpu. |
| 56 | */ |
| 57 | static unsigned char board_to_cpu[32]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | static int pil_to_sbus[] = { |
Sam Ravnborg | e54f854 | 2011-01-28 22:08:21 +0000 | [diff] [blame] | 60 | 0, |
| 61 | 0, |
| 62 | 1, |
| 63 | 2, |
| 64 | 0, |
| 65 | 3, |
| 66 | 0, |
| 67 | 4, |
| 68 | 0, |
| 69 | 5, |
| 70 | 0, |
| 71 | 6, |
| 72 | 0, |
| 73 | 7, |
| 74 | 0, |
| 75 | 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 76 | }; |
| 77 | |
David S. Miller | f8376e9 | 2008-09-13 22:05:25 -0700 | [diff] [blame] | 78 | /* Exported for sun4d_smp.c */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 79 | DEFINE_SPINLOCK(sun4d_imsk_lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 80 | |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 81 | /* SBUS interrupts are encoded integers including the board number |
| 82 | * (plus one), the SBUS level, and the SBUS slot number. Sun4D |
| 83 | * IRQ dispatch is done by: |
| 84 | * |
| 85 | * 1) Reading the BW local interrupt table in order to get the bus |
| 86 | * interrupt mask. |
| 87 | * |
| 88 | * This table is indexed by SBUS interrupt level which can be |
| 89 | * derived from the PIL we got interrupted on. |
| 90 | * |
| 91 | * 2) For each bus showing interrupt pending from #1, read the |
| 92 | * SBI interrupt state register. This will indicate which slots |
| 93 | * have interrupts pending for that SBUS interrupt level. |
| 94 | * |
| 95 | * 3) Call the genreric IRQ support. |
| 96 | */ |
| 97 | static void sun4d_sbus_handler_irq(int sbusl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | { |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 99 | unsigned int bus_mask; |
| 100 | unsigned int sbino, slot; |
| 101 | unsigned int sbil; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 102 | |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 103 | bus_mask = bw_get_intr_mask(sbusl) & 0x3ffff; |
| 104 | bw_clear_intr_mask(sbusl, bus_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 105 | |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 106 | sbil = (sbusl << 2); |
| 107 | /* Loop for each pending SBI */ |
oftedal | ea16058 | 2011-06-01 11:04:20 +0000 | [diff] [blame] | 108 | for (sbino = 0; bus_mask; sbino++, bus_mask >>= 1) { |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 109 | unsigned int idx, mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 111 | if (!(bus_mask & 1)) |
| 112 | continue; |
| 113 | /* XXX This seems to ACK the irq twice. acquire_sbi() |
| 114 | * XXX uses swap, therefore this writes 0xf << sbil, |
| 115 | * XXX then later release_sbi() will write the individual |
| 116 | * XXX bits which were set again. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 117 | */ |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 118 | mask = acquire_sbi(SBI2DEVID(sbino), 0xf << sbil); |
| 119 | mask &= (0xf << sbil); |
| 120 | |
| 121 | /* Loop for each pending SBI slot */ |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 122 | slot = (1 << sbil); |
oftedal | ea16058 | 2011-06-01 11:04:20 +0000 | [diff] [blame] | 123 | for (idx = 0; mask != 0; idx++, slot <<= 1) { |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 124 | unsigned int pil; |
| 125 | struct irq_bucket *p; |
| 126 | |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 127 | if (!(mask & slot)) |
| 128 | continue; |
| 129 | |
| 130 | mask &= ~slot; |
oftedal | ea16058 | 2011-06-01 11:04:20 +0000 | [diff] [blame] | 131 | pil = sun4d_encode_irq(sbino, sbusl, idx); |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 132 | |
| 133 | p = irq_map[pil]; |
| 134 | while (p) { |
| 135 | struct irq_bucket *next; |
| 136 | |
| 137 | next = p->next; |
| 138 | generic_handle_irq(p->irq); |
| 139 | p = next; |
| 140 | } |
| 141 | release_sbi(SBI2DEVID(sbino), slot); |
| 142 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 144 | } |
| 145 | |
Sam Ravnborg | 5ac7568 | 2014-04-21 21:39:23 +0200 | [diff] [blame] | 146 | void sun4d_handler_irq(unsigned int pil, struct pt_regs *regs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | { |
Al Viro | 0d84438 | 2006-10-08 14:30:44 +0100 | [diff] [blame] | 148 | struct pt_regs *old_regs; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 149 | /* SBUS IRQ level (1 - 7) */ |
Sam Ravnborg | d4d1ec4 | 2011-01-22 11:32:15 +0000 | [diff] [blame] | 150 | int sbusl = pil_to_sbus[pil]; |
Sam Ravnborg | e54f854 | 2011-01-28 22:08:21 +0000 | [diff] [blame] | 151 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 152 | /* FIXME: Is this necessary?? */ |
| 153 | cc_get_ipen(); |
Sam Ravnborg | e54f854 | 2011-01-28 22:08:21 +0000 | [diff] [blame] | 154 | |
Sam Ravnborg | d4d1ec4 | 2011-01-22 11:32:15 +0000 | [diff] [blame] | 155 | cc_set_iclr(1 << pil); |
Sam Ravnborg | e54f854 | 2011-01-28 22:08:21 +0000 | [diff] [blame] | 156 | |
Daniel Hellstrom | 55dd23e | 2011-05-02 00:08:54 +0000 | [diff] [blame] | 157 | #ifdef CONFIG_SMP |
| 158 | /* |
| 159 | * Check IPI data structures after IRQ has been cleared. Hard and Soft |
| 160 | * IRQ can happen at the same time, so both cases are always handled. |
| 161 | */ |
| 162 | if (pil == SUN4D_IPI_IRQ) |
| 163 | sun4d_ipi_interrupt(); |
| 164 | #endif |
| 165 | |
Al Viro | 0d84438 | 2006-10-08 14:30:44 +0100 | [diff] [blame] | 166 | old_regs = set_irq_regs(regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 167 | irq_enter(); |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 168 | if (sbusl == 0) { |
| 169 | /* cpu interrupt */ |
| 170 | struct irq_bucket *p; |
| 171 | |
| 172 | p = irq_map[pil]; |
| 173 | while (p) { |
| 174 | struct irq_bucket *next; |
| 175 | |
| 176 | next = p->next; |
| 177 | generic_handle_irq(p->irq); |
| 178 | p = next; |
| 179 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 180 | } else { |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 181 | /* SBUS interrupt */ |
| 182 | sun4d_sbus_handler_irq(sbusl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 183 | } |
| 184 | irq_exit(); |
Al Viro | 0d84438 | 2006-10-08 14:30:44 +0100 | [diff] [blame] | 185 | set_irq_regs(old_regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 186 | } |
| 187 | |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 188 | |
| 189 | static void sun4d_mask_irq(struct irq_data *data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 190 | { |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 191 | struct sun4d_handler_data *handler_data = data->handler_data; |
| 192 | unsigned int real_irq; |
| 193 | #ifdef CONFIG_SMP |
| 194 | int cpuid = handler_data->cpuid; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 195 | unsigned long flags; |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 196 | #endif |
| 197 | real_irq = handler_data->real_irq; |
| 198 | #ifdef CONFIG_SMP |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | spin_lock_irqsave(&sun4d_imsk_lock, flags); |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 200 | cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) | (1 << real_irq)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 201 | spin_unlock_irqrestore(&sun4d_imsk_lock, flags); |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 202 | #else |
| 203 | cc_set_imsk(cc_get_imsk() | (1 << real_irq)); |
| 204 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 205 | } |
| 206 | |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 207 | static void sun4d_unmask_irq(struct irq_data *data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 208 | { |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 209 | struct sun4d_handler_data *handler_data = data->handler_data; |
| 210 | unsigned int real_irq; |
| 211 | #ifdef CONFIG_SMP |
| 212 | int cpuid = handler_data->cpuid; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 213 | unsigned long flags; |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 214 | #endif |
| 215 | real_irq = handler_data->real_irq; |
Sam Ravnborg | e54f854 | 2011-01-28 22:08:21 +0000 | [diff] [blame] | 216 | |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 217 | #ifdef CONFIG_SMP |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | spin_lock_irqsave(&sun4d_imsk_lock, flags); |
oftedal | ea16058 | 2011-06-01 11:04:20 +0000 | [diff] [blame] | 219 | cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) & ~(1 << real_irq)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 220 | spin_unlock_irqrestore(&sun4d_imsk_lock, flags); |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 221 | #else |
oftedal | ea16058 | 2011-06-01 11:04:20 +0000 | [diff] [blame] | 222 | cc_set_imsk(cc_get_imsk() & ~(1 << real_irq)); |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 223 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 224 | } |
| 225 | |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 226 | static unsigned int sun4d_startup_irq(struct irq_data *data) |
| 227 | { |
| 228 | irq_link(data->irq); |
| 229 | sun4d_unmask_irq(data); |
| 230 | return 0; |
| 231 | } |
| 232 | |
| 233 | static void sun4d_shutdown_irq(struct irq_data *data) |
| 234 | { |
| 235 | sun4d_mask_irq(data); |
| 236 | irq_unlink(data->irq); |
| 237 | } |
| 238 | |
Sam Ravnborg | 5ac7568 | 2014-04-21 21:39:23 +0200 | [diff] [blame] | 239 | static struct irq_chip sun4d_irq = { |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 240 | .name = "sun4d", |
| 241 | .irq_startup = sun4d_startup_irq, |
| 242 | .irq_shutdown = sun4d_shutdown_irq, |
| 243 | .irq_unmask = sun4d_unmask_irq, |
| 244 | .irq_mask = sun4d_mask_irq, |
| 245 | }; |
| 246 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 247 | #ifdef CONFIG_SMP |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 248 | /* Setup IRQ distribution scheme. */ |
| 249 | void __init sun4d_distribute_irqs(void) |
| 250 | { |
David S. Miller | 71d3721 | 2008-08-27 02:50:57 -0700 | [diff] [blame] | 251 | struct device_node *dp; |
| 252 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 253 | int cpuid = cpu_logical_map(1); |
| 254 | |
| 255 | if (cpuid == -1) |
| 256 | cpuid = cpu_logical_map(0); |
David S. Miller | 71d3721 | 2008-08-27 02:50:57 -0700 | [diff] [blame] | 257 | for_each_node_by_name(dp, "sbi") { |
| 258 | int devid = of_getintprop_default(dp, "device-id", 0); |
| 259 | int board = of_getintprop_default(dp, "board#", 0); |
Sam Ravnborg | db1cdd1 | 2011-04-18 11:25:42 +0000 | [diff] [blame] | 260 | board_to_cpu[board] = cpuid; |
David S. Miller | 71d3721 | 2008-08-27 02:50:57 -0700 | [diff] [blame] | 261 | set_sbi_tid(devid, cpuid << 3); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 262 | } |
Sam Ravnborg | e54f854 | 2011-01-28 22:08:21 +0000 | [diff] [blame] | 263 | printk(KERN_ERR "All sbus IRQs directed to CPU%d\n", cpuid); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 264 | } |
| 265 | #endif |
Sam Ravnborg | e54f854 | 2011-01-28 22:08:21 +0000 | [diff] [blame] | 266 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 267 | static void sun4d_clear_clock_irq(void) |
| 268 | { |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 269 | sbus_readl(&sun4d_timers->l10_timer_limit); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 270 | } |
| 271 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | static void sun4d_load_profile_irq(int cpu, unsigned int limit) |
| 273 | { |
Tkhai Kirill | 62f0828 | 2012-04-04 21:49:26 +0200 | [diff] [blame] | 274 | unsigned int value = limit ? timer_value(limit) : 0; |
| 275 | bw_set_prof_limit(cpu, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 276 | } |
| 277 | |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 278 | static void __init sun4d_load_profile_irqs(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 279 | { |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 280 | int cpu = 0, mid; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 281 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 282 | while (!cpu_find_by_instance(cpu, NULL, &mid)) { |
| 283 | sun4d_load_profile_irq(mid >> 3, 0); |
| 284 | cpu++; |
| 285 | } |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 286 | } |
| 287 | |
Sam Ravnborg | 5ac7568 | 2014-04-21 21:39:23 +0200 | [diff] [blame] | 288 | static unsigned int _sun4d_build_device_irq(unsigned int real_irq, |
| 289 | unsigned int pil, |
| 290 | unsigned int board) |
oftedal | 5fba170 | 2011-06-01 10:43:50 +0000 | [diff] [blame] | 291 | { |
| 292 | struct sun4d_handler_data *handler_data; |
| 293 | unsigned int irq; |
| 294 | |
| 295 | irq = irq_alloc(real_irq, pil); |
| 296 | if (irq == 0) { |
| 297 | prom_printf("IRQ: allocate for %d %d %d failed\n", |
| 298 | real_irq, pil, board); |
| 299 | goto err_out; |
| 300 | } |
| 301 | |
| 302 | handler_data = irq_get_handler_data(irq); |
| 303 | if (unlikely(handler_data)) |
| 304 | goto err_out; |
| 305 | |
| 306 | handler_data = kzalloc(sizeof(struct sun4d_handler_data), GFP_ATOMIC); |
| 307 | if (unlikely(!handler_data)) { |
| 308 | prom_printf("IRQ: kzalloc(sun4d_handler_data) failed.\n"); |
| 309 | prom_halt(); |
| 310 | } |
| 311 | handler_data->cpuid = board_to_cpu[board]; |
| 312 | handler_data->real_irq = real_irq; |
| 313 | irq_set_chip_and_handler_name(irq, &sun4d_irq, |
| 314 | handle_level_irq, "level"); |
| 315 | irq_set_handler_data(irq, handler_data); |
| 316 | |
| 317 | err_out: |
| 318 | return irq; |
| 319 | } |
| 320 | |
| 321 | |
| 322 | |
Sam Ravnborg | 5ac7568 | 2014-04-21 21:39:23 +0200 | [diff] [blame] | 323 | static unsigned int sun4d_build_device_irq(struct platform_device *op, |
| 324 | unsigned int real_irq) |
Sam Ravnborg | 1d05995 | 2011-02-25 23:01:19 -0800 | [diff] [blame] | 325 | { |
Sam Ravnborg | 1d05995 | 2011-02-25 23:01:19 -0800 | [diff] [blame] | 326 | struct device_node *dp = op->dev.of_node; |
oftedal | 9eeb089 | 2011-06-01 11:11:41 +0000 | [diff] [blame] | 327 | struct device_node *board_parent, *bus = dp->parent; |
| 328 | char *bus_connection; |
Sam Ravnborg | 1d05995 | 2011-02-25 23:01:19 -0800 | [diff] [blame] | 329 | const struct linux_prom_registers *regs; |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 330 | unsigned int pil; |
| 331 | unsigned int irq; |
Sam Ravnborg | 1d05995 | 2011-02-25 23:01:19 -0800 | [diff] [blame] | 332 | int board, slot; |
| 333 | int sbusl; |
| 334 | |
oftedal | 5fba170 | 2011-06-01 10:43:50 +0000 | [diff] [blame] | 335 | irq = real_irq; |
oftedal | 9eeb089 | 2011-06-01 11:11:41 +0000 | [diff] [blame] | 336 | while (bus) { |
| 337 | if (!strcmp(bus->name, "sbi")) { |
| 338 | bus_connection = "io-unit"; |
Sam Ravnborg | 1d05995 | 2011-02-25 23:01:19 -0800 | [diff] [blame] | 339 | break; |
oftedal | 9eeb089 | 2011-06-01 11:11:41 +0000 | [diff] [blame] | 340 | } |
Sam Ravnborg | 1d05995 | 2011-02-25 23:01:19 -0800 | [diff] [blame] | 341 | |
oftedal | 9eeb089 | 2011-06-01 11:11:41 +0000 | [diff] [blame] | 342 | if (!strcmp(bus->name, "bootbus")) { |
| 343 | bus_connection = "cpu-unit"; |
| 344 | break; |
| 345 | } |
| 346 | |
| 347 | bus = bus->parent; |
Sam Ravnborg | 1d05995 | 2011-02-25 23:01:19 -0800 | [diff] [blame] | 348 | } |
oftedal | 9eeb089 | 2011-06-01 11:11:41 +0000 | [diff] [blame] | 349 | if (!bus) |
Sam Ravnborg | 1d05995 | 2011-02-25 23:01:19 -0800 | [diff] [blame] | 350 | goto err_out; |
| 351 | |
| 352 | regs = of_get_property(dp, "reg", NULL); |
| 353 | if (!regs) |
| 354 | goto err_out; |
| 355 | |
| 356 | slot = regs->which_io; |
| 357 | |
| 358 | /* |
oftedal | 9eeb089 | 2011-06-01 11:11:41 +0000 | [diff] [blame] | 359 | * If Bus nodes parent is not io-unit/cpu-unit or the io-unit/cpu-unit |
| 360 | * lacks a "board#" property, something is very wrong. |
Sam Ravnborg | 1d05995 | 2011-02-25 23:01:19 -0800 | [diff] [blame] | 361 | */ |
oftedal | 9eeb089 | 2011-06-01 11:11:41 +0000 | [diff] [blame] | 362 | if (!bus->parent || strcmp(bus->parent->name, bus_connection)) { |
| 363 | printk(KERN_ERR "%s: Error, parent is not %s.\n", |
| 364 | bus->full_name, bus_connection); |
Sam Ravnborg | 1d05995 | 2011-02-25 23:01:19 -0800 | [diff] [blame] | 365 | goto err_out; |
| 366 | } |
oftedal | 9eeb089 | 2011-06-01 11:11:41 +0000 | [diff] [blame] | 367 | board_parent = bus->parent; |
| 368 | board = of_getintprop_default(board_parent, "board#", -1); |
Sam Ravnborg | 1d05995 | 2011-02-25 23:01:19 -0800 | [diff] [blame] | 369 | if (board == -1) { |
oftedal | 9eeb089 | 2011-06-01 11:11:41 +0000 | [diff] [blame] | 370 | printk(KERN_ERR "%s: Error, lacks board# property.\n", |
| 371 | board_parent->full_name); |
Sam Ravnborg | 1d05995 | 2011-02-25 23:01:19 -0800 | [diff] [blame] | 372 | goto err_out; |
| 373 | } |
| 374 | |
| 375 | sbusl = pil_to_sbus[real_irq]; |
| 376 | if (sbusl) |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 377 | pil = sun4d_encode_irq(board, sbusl, slot); |
| 378 | else |
| 379 | pil = real_irq; |
| 380 | |
oftedal | 5fba170 | 2011-06-01 10:43:50 +0000 | [diff] [blame] | 381 | irq = _sun4d_build_device_irq(real_irq, pil, board); |
Sam Ravnborg | 1d05995 | 2011-02-25 23:01:19 -0800 | [diff] [blame] | 382 | err_out: |
oftedal | 5fba170 | 2011-06-01 10:43:50 +0000 | [diff] [blame] | 383 | return irq; |
Sam Ravnborg | 1d05995 | 2011-02-25 23:01:19 -0800 | [diff] [blame] | 384 | } |
| 385 | |
Sam Ravnborg | 5ac7568 | 2014-04-21 21:39:23 +0200 | [diff] [blame] | 386 | static unsigned int sun4d_build_timer_irq(unsigned int board, |
| 387 | unsigned int real_irq) |
oftedal | 5fba170 | 2011-06-01 10:43:50 +0000 | [diff] [blame] | 388 | { |
| 389 | return _sun4d_build_device_irq(real_irq, real_irq, board); |
| 390 | } |
| 391 | |
| 392 | |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 393 | static void __init sun4d_fixup_trap_table(void) |
| 394 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | #ifdef CONFIG_SMP |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 396 | unsigned long flags; |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 397 | struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 398 | |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 399 | /* Adjust so that we jump directly to smp4d_ticker */ |
| 400 | lvl14_save[2] += smp4d_ticker - real_irq_entry; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 401 | |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 402 | /* For SMP we use the level 14 ticker, however the bootup code |
| 403 | * has copied the firmware's level 14 vector into the boot cpu's |
| 404 | * trap table, we must fix this now or we get squashed. |
| 405 | */ |
| 406 | local_irq_save(flags); |
| 407 | patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */ |
| 408 | trap_table->inst_one = lvl14_save[0]; |
| 409 | trap_table->inst_two = lvl14_save[1]; |
| 410 | trap_table->inst_three = lvl14_save[2]; |
| 411 | trap_table->inst_four = lvl14_save[3]; |
David S. Miller | 5d83d66 | 2012-05-13 20:49:31 -0700 | [diff] [blame] | 412 | local_ops->cache_all(); |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 413 | local_irq_restore(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 414 | #endif |
| 415 | } |
| 416 | |
Tkhai Kirill | 62f0828 | 2012-04-04 21:49:26 +0200 | [diff] [blame] | 417 | static void __init sun4d_init_timers(void) |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 418 | { |
| 419 | struct device_node *dp; |
| 420 | struct resource res; |
Sam Ravnborg | 6baa9b2 | 2011-04-18 11:25:44 +0000 | [diff] [blame] | 421 | unsigned int irq; |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 422 | const u32 *reg; |
| 423 | int err; |
oftedal | 5fba170 | 2011-06-01 10:43:50 +0000 | [diff] [blame] | 424 | int board; |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 425 | |
| 426 | dp = of_find_node_by_name(NULL, "cpu-unit"); |
| 427 | if (!dp) { |
| 428 | prom_printf("sun4d_init_timers: Unable to find cpu-unit\n"); |
| 429 | prom_halt(); |
| 430 | } |
| 431 | |
| 432 | /* Which cpu-unit we use is arbitrary, we can view the bootbus timer |
| 433 | * registers via any cpu's mapping. The first 'reg' property is the |
| 434 | * bootbus. |
| 435 | */ |
| 436 | reg = of_get_property(dp, "reg", NULL); |
| 437 | if (!reg) { |
| 438 | prom_printf("sun4d_init_timers: No reg property\n"); |
| 439 | prom_halt(); |
| 440 | } |
| 441 | |
oftedal | 5fba170 | 2011-06-01 10:43:50 +0000 | [diff] [blame] | 442 | board = of_getintprop_default(dp, "board#", -1); |
| 443 | if (board == -1) { |
| 444 | prom_printf("sun4d_init_timers: No board# property on cpu-unit\n"); |
| 445 | prom_halt(); |
| 446 | } |
| 447 | |
| 448 | of_node_put(dp); |
| 449 | |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 450 | res.start = reg[1]; |
| 451 | res.end = reg[2] - 1; |
| 452 | res.flags = reg[0] & 0xff; |
| 453 | sun4d_timers = of_ioremap(&res, BW_TIMER_LIMIT, |
| 454 | sizeof(struct sun4d_timer_regs), "user timer"); |
| 455 | if (!sun4d_timers) { |
| 456 | prom_printf("sun4d_init_timers: Can't map timer regs\n"); |
| 457 | prom_halt(); |
| 458 | } |
| 459 | |
Tkhai Kirill | 62f0828 | 2012-04-04 21:49:26 +0200 | [diff] [blame] | 460 | #ifdef CONFIG_SMP |
| 461 | sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */ |
| 462 | #else |
| 463 | sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */ |
| 464 | sparc_config.features |= FEAT_L10_CLOCKEVENT; |
| 465 | #endif |
| 466 | sparc_config.features |= FEAT_L10_CLOCKSOURCE; |
| 467 | sbus_writel(timer_value(sparc_config.cs_period), |
| 468 | &sun4d_timers->l10_timer_limit); |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 469 | |
| 470 | master_l10_counter = &sun4d_timers->l10_cur_count; |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 471 | |
oftedal | 5fba170 | 2011-06-01 10:43:50 +0000 | [diff] [blame] | 472 | irq = sun4d_build_timer_irq(board, SUN4D_TIMER_IRQ); |
Tkhai Kirill | 62f0828 | 2012-04-04 21:49:26 +0200 | [diff] [blame] | 473 | err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL); |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 474 | if (err) { |
Sam Ravnborg | e54f854 | 2011-01-28 22:08:21 +0000 | [diff] [blame] | 475 | prom_printf("sun4d_init_timers: request_irq() failed with %d\n", |
| 476 | err); |
David S. Miller | f5f1085 | 2008-09-13 22:04:55 -0700 | [diff] [blame] | 477 | prom_halt(); |
| 478 | } |
| 479 | sun4d_load_profile_irqs(); |
| 480 | sun4d_fixup_trap_table(); |
| 481 | } |
| 482 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 483 | void __init sun4d_init_sbi_irq(void) |
| 484 | { |
David S. Miller | 71d3721 | 2008-08-27 02:50:57 -0700 | [diff] [blame] | 485 | struct device_node *dp; |
Daniel Hellstrom | 5fcafb7 | 2011-04-21 04:20:23 +0000 | [diff] [blame] | 486 | int target_cpu; |
David S. Miller | f8376e9 | 2008-09-13 22:05:25 -0700 | [diff] [blame] | 487 | |
David S. Miller | f8376e9 | 2008-09-13 22:05:25 -0700 | [diff] [blame] | 488 | target_cpu = boot_cpu_id; |
David S. Miller | 71d3721 | 2008-08-27 02:50:57 -0700 | [diff] [blame] | 489 | for_each_node_by_name(dp, "sbi") { |
| 490 | int devid = of_getintprop_default(dp, "device-id", 0); |
| 491 | int board = of_getintprop_default(dp, "board#", 0); |
| 492 | unsigned int mask; |
| 493 | |
David S. Miller | f8376e9 | 2008-09-13 22:05:25 -0700 | [diff] [blame] | 494 | set_sbi_tid(devid, target_cpu << 3); |
Sam Ravnborg | db1cdd1 | 2011-04-18 11:25:42 +0000 | [diff] [blame] | 495 | board_to_cpu[board] = target_cpu; |
David S. Miller | f8376e9 | 2008-09-13 22:05:25 -0700 | [diff] [blame] | 496 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 497 | /* Get rid of pending irqs from PROM */ |
David S. Miller | 71d3721 | 2008-08-27 02:50:57 -0700 | [diff] [blame] | 498 | mask = acquire_sbi(devid, 0xffffffff); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 499 | if (mask) { |
Sam Ravnborg | e54f854 | 2011-01-28 22:08:21 +0000 | [diff] [blame] | 500 | printk(KERN_ERR "Clearing pending IRQs %08x on SBI %d\n", |
| 501 | mask, board); |
David S. Miller | 71d3721 | 2008-08-27 02:50:57 -0700 | [diff] [blame] | 502 | release_sbi(devid, mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 503 | } |
| 504 | } |
| 505 | } |
| 506 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 507 | void __init sun4d_init_IRQ(void) |
| 508 | { |
| 509 | local_irq_disable(); |
| 510 | |
Sam Ravnborg | 472bc4f | 2012-04-04 13:21:13 +0200 | [diff] [blame] | 511 | sparc_config.init_timers = sun4d_init_timers; |
| 512 | sparc_config.build_device_irq = sun4d_build_device_irq; |
Tkhai Kirill | 62f0828 | 2012-04-04 21:49:26 +0200 | [diff] [blame] | 513 | sparc_config.clock_rate = SBUS_CLOCK_RATE; |
Sam Ravnborg | 08c9388 | 2012-05-14 17:30:35 +0200 | [diff] [blame] | 514 | sparc_config.clear_clock_irq = sun4d_clear_clock_irq; |
| 515 | sparc_config.load_profile_irq = sun4d_load_profile_irq; |
Sam Ravnborg | bbdc266 | 2011-02-25 23:00:19 -0800 | [diff] [blame] | 516 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 517 | /* Cannot enable interrupts until OBP ticker is disabled. */ |
| 518 | } |