blob: 461499b43cff4efc29ea5996f6dafa200aaba872 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
David Gibsonf7f6f4f2005-10-19 14:53:32 +10002 * arch/powerpc/kernel/pmc.c
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Copyright (C) 2004 David Gibson, IBM Corporation.
David Gibsonf7f6f4f2005-10-19 14:53:32 +10005 * Includes code formerly from arch/ppc/kernel/perfmon.c:
6 * Author: Andy Fleming
7 * Copyright (c) 2004 Freescale Semiconductor, Inc
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <linux/errno.h>
16#include <linux/spinlock.h>
17#include <linux/module.h>
18
19#include <asm/processor.h>
Olof Johansson6529c132007-01-28 21:25:57 -060020#include <asm/cputable.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <asm/pmc.h>
22
Anton Blanchard177e9ea2007-05-20 03:13:43 +100023#ifndef MMCR0_PMAO
24#define MMCR0_PMAO 0
Olof Johansson1bd2e5a2007-01-28 21:23:54 -060025#endif
26
27static void dummy_perf(struct pt_regs *regs)
28{
Andy Fleming39aef682008-02-04 18:27:55 -060029#if defined(CONFIG_FSL_EMB_PERFMON)
Olof Johansson1bd2e5a2007-01-28 21:23:54 -060030 mtpmr(PMRN_PMGC0, mfpmr(PMRN_PMGC0) & ~PMGC0_PMIE);
David Gibsonf7f6f4f2005-10-19 14:53:32 +100031#elif defined(CONFIG_PPC64) || defined(CONFIG_6xx)
Olof Johansson6529c132007-01-28 21:25:57 -060032 if (cur_cpu_spec->pmc_type == PPC_PMC_IBM)
Anton Blanchard177e9ea2007-05-20 03:13:43 +100033 mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~(MMCR0_PMXE|MMCR0_PMAO));
David Gibsonf7f6f4f2005-10-19 14:53:32 +100034#else
Olof Johansson1bd2e5a2007-01-28 21:23:54 -060035 mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~MMCR0_PMXE);
David Gibsonf7f6f4f2005-10-19 14:53:32 +100036#endif
Olof Johansson1bd2e5a2007-01-28 21:23:54 -060037}
38
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
Thomas Gleixner071c06c2010-02-18 02:22:27 +000040static DEFINE_RAW_SPINLOCK(pmc_owner_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070041static void *pmc_owner_caller; /* mostly for debugging */
42perf_irq_t perf_irq = dummy_perf;
43
44int reserve_pmc_hardware(perf_irq_t new_perf_irq)
45{
46 int err = 0;
47
Thomas Gleixner071c06c2010-02-18 02:22:27 +000048 raw_spin_lock(&pmc_owner_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070049
50 if (pmc_owner_caller) {
51 printk(KERN_WARNING "reserve_pmc_hardware: "
52 "PMC hardware busy (reserved by caller %p)\n",
53 pmc_owner_caller);
54 err = -EBUSY;
55 goto out;
56 }
57
58 pmc_owner_caller = __builtin_return_address(0);
Andy Flemingdd6c89f2006-10-27 15:06:32 -050059 perf_irq = new_perf_irq ? new_perf_irq : dummy_perf;
Linus Torvalds1da177e2005-04-16 15:20:36 -070060
61 out:
Thomas Gleixner071c06c2010-02-18 02:22:27 +000062 raw_spin_unlock(&pmc_owner_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070063 return err;
64}
65EXPORT_SYMBOL_GPL(reserve_pmc_hardware);
66
67void release_pmc_hardware(void)
68{
Thomas Gleixner071c06c2010-02-18 02:22:27 +000069 raw_spin_lock(&pmc_owner_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070070
71 WARN_ON(! pmc_owner_caller);
72
73 pmc_owner_caller = NULL;
74 perf_irq = dummy_perf;
75
Thomas Gleixner071c06c2010-02-18 02:22:27 +000076 raw_spin_unlock(&pmc_owner_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070077}
78EXPORT_SYMBOL_GPL(release_pmc_hardware);
Michael Ellerman180a3362005-08-09 11:13:36 +100079
David Gibsonf7f6f4f2005-10-19 14:53:32 +100080#ifdef CONFIG_PPC64
Michael Ellerman180a3362005-08-09 11:13:36 +100081void power4_enable_pmcs(void)
82{
83 unsigned long hid0;
84
Paul Mackerrasb5bbeb22005-10-10 14:01:07 +100085 hid0 = mfspr(SPRN_HID0);
Michael Ellerman180a3362005-08-09 11:13:36 +100086 hid0 |= 1UL << (63 - 20);
87
88 /* POWER4 requires the following sequence */
89 asm volatile(
90 "sync\n"
91 "mtspr %1, %0\n"
92 "mfspr %0, %1\n"
93 "mfspr %0, %1\n"
94 "mfspr %0, %1\n"
95 "mfspr %0, %1\n"
96 "mfspr %0, %1\n"
97 "mfspr %0, %1\n"
Paul Mackerrasb5bbeb22005-10-10 14:01:07 +100098 "isync" : "=&r" (hid0) : "i" (SPRN_HID0), "0" (hid0):
Michael Ellerman180a3362005-08-09 11:13:36 +100099 "memory");
100}
David Gibsonf7f6f4f2005-10-19 14:53:32 +1000101#endif /* CONFIG_PPC64 */