blob: a5900f64e38c112e7fb195ea2cdca7281cc64af7 [file] [log] [blame]
Nicolas Pitre0100def2009-01-30 22:44:20 -05001/*
2 * arch/arm/mach-kirkwood/mpp.c
3 *
4 * MPP functions for Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h>
15#include <asm/gpio.h>
16#include <mach/hardware.h>
17#include "common.h"
18#include "mpp.h"
19
20static unsigned int __init kirkwood_variant(void)
21{
22 u32 dev, rev;
23
24 kirkwood_pcie_id(&dev, &rev);
25
26 if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0)
27 return MPP_F6281_MASK;
28 if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
29 return MPP_F6192_MASK;
30 if (dev == MV88F6180_DEV_ID)
31 return MPP_F6180_MASK;
32
33 printk(KERN_ERR "MPP setup: unknown kirkwood variant "
34 "(dev %#x rev %#x)\n", dev, rev);
35 return 0;
36}
37
38#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4)
39#define MPP_NR_REGS (1 + MPP_MAX/8)
40
41void __init kirkwood_mpp_conf(unsigned int *mpp_list)
42{
43 u32 mpp_ctrl[MPP_NR_REGS];
44 unsigned int variant_mask;
45 int i;
46
47 variant_mask = kirkwood_variant();
48 if (!variant_mask)
49 return;
50
Erik Benadaa8865652009-05-28 17:08:55 -070051 /* Initialize gpiolib. */
52 orion_gpio_init();
53
Nicolas Pitre0100def2009-01-30 22:44:20 -050054 printk(KERN_DEBUG "initial MPP regs:");
55 for (i = 0; i < MPP_NR_REGS; i++) {
56 mpp_ctrl[i] = readl(MPP_CTRL(i));
57 printk(" %08x", mpp_ctrl[i]);
58 }
59 printk("\n");
60
61 while (*mpp_list) {
62 unsigned int num = MPP_NUM(*mpp_list);
63 unsigned int sel = MPP_SEL(*mpp_list);
64 int shift, gpio_mode;
65
66 if (num > MPP_MAX) {
67 printk(KERN_ERR "kirkwood_mpp_conf: invalid MPP "
68 "number (%u)\n", num);
69 continue;
70 }
71 if (!(*mpp_list & variant_mask)) {
72 printk(KERN_WARNING
73 "kirkwood_mpp_conf: requested MPP%u config "
74 "unavailable on this hardware\n", num);
75 continue;
76 }
77
78 shift = (num & 7) << 2;
79 mpp_ctrl[num / 8] &= ~(0xf << shift);
80 mpp_ctrl[num / 8] |= sel << shift;
81
82 gpio_mode = 0;
83 if (*mpp_list & MPP_INPUT_MASK)
84 gpio_mode |= GPIO_INPUT_OK;
85 if (*mpp_list & MPP_OUTPUT_MASK)
86 gpio_mode |= GPIO_OUTPUT_OK;
87 if (sel != 0)
88 gpio_mode = 0;
89 orion_gpio_set_valid(num, gpio_mode);
90
91 mpp_list++;
92 }
93
94 printk(KERN_DEBUG " final MPP regs:");
95 for (i = 0; i < MPP_NR_REGS; i++) {
96 writel(mpp_ctrl[i], MPP_CTRL(i));
97 printk(" %08x", mpp_ctrl[i]);
98 }
99 printk("\n");
100}