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Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +01001#include <linux/bitops.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07002#include <linux/kernel.h>
Ingo Molnaredc05e62008-02-18 03:30:47 +01003
Borislav Petkovcd4d09e2016-01-26 22:12:04 +01004#include <asm/cpufeature.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07005#include <asm/e820.h>
Jesper Juhl52f4a912006-03-23 02:59:50 -08006#include <asm/mtrr.h>
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +01007#include <asm/msr.h>
Ingo Molnaredc05e62008-02-18 03:30:47 +01008
Linus Torvalds1da177e2005-04-16 15:20:36 -07009#include "cpu.h"
10
Linus Torvalds1da177e2005-04-16 15:20:36 -070011#define ACE_PRESENT (1 << 6)
12#define ACE_ENABLED (1 << 7)
13#define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
14
15#define RNG_PRESENT (1 << 2)
16#define RNG_ENABLED (1 << 3)
17#define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */
18
Paul Gortmaker148f9bb2013-06-18 18:23:59 -040019static void init_c3(struct cpuinfo_x86 *c)
Linus Torvalds1da177e2005-04-16 15:20:36 -070020{
21 u32 lo, hi;
22
23 /* Test for Centaur Extended Feature Flags presence */
24 if (cpuid_eax(0xC0000000) >= 0xC0000001) {
25 u32 tmp = cpuid_edx(0xC0000001);
26
27 /* enable ACE unit, if present and disabled */
28 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +010029 rdmsr(MSR_VIA_FCR, lo, hi);
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 lo |= ACE_FCR; /* enable ACE unit */
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +010031 wrmsr(MSR_VIA_FCR, lo, hi);
Chen Yucong1b74dde2016-02-02 11:45:02 +080032 pr_info("CPU: Enabled ACE h/w crypto\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070033 }
34
35 /* enable RNG unit, if present and disabled */
36 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +010037 rdmsr(MSR_VIA_RNG, lo, hi);
Linus Torvalds1da177e2005-04-16 15:20:36 -070038 lo |= RNG_ENABLE; /* enable RNG unit */
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +010039 wrmsr(MSR_VIA_RNG, lo, hi);
Chen Yucong1b74dde2016-02-02 11:45:02 +080040 pr_info("CPU: Enabled h/w RNG\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070041 }
42
43 /* store Centaur Extended Feature Flags as
44 * word 5 of the CPU capability bit array
45 */
Borislav Petkov39c06df2015-12-07 10:39:40 +010046 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
Linus Torvalds1da177e2005-04-16 15:20:36 -070047 }
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +010048#ifdef CONFIG_X86_32
Simon Arlott27b46d72007-10-20 01:13:56 +020049 /* Cyrix III family needs CX8 & PGE explicitly enabled. */
Timo Teräscb3f7182011-12-15 17:11:28 +020050 if (c->x86_model >= 6 && c->x86_model <= 13) {
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +010051 rdmsr(MSR_VIA_FCR, lo, hi);
Linus Torvalds1da177e2005-04-16 15:20:36 -070052 lo |= (1<<1 | 1<<7);
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +010053 wrmsr(MSR_VIA_FCR, lo, hi);
Ingo Molnare1a94a92008-02-26 08:51:22 +010054 set_cpu_cap(c, X86_FEATURE_CX8);
Linus Torvalds1da177e2005-04-16 15:20:36 -070055 }
56
57 /* Before Nehemiah, the C3's had 3dNOW! */
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +010058 if (c->x86_model >= 6 && c->x86_model < 9)
Ingo Molnare1a94a92008-02-26 08:51:22 +010059 set_cpu_cap(c, X86_FEATURE_3DNOW);
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +010060#endif
61 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
62 c->x86_cache_alignment = c->x86_clflush_size * 2;
63 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
64 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070065
Borislav Petkov27c13ec2009-11-21 14:01:45 +010066 cpu_detect_cache_sizes(c);
Linus Torvalds1da177e2005-04-16 15:20:36 -070067}
68
Ingo Molnaredc05e62008-02-18 03:30:47 +010069enum {
70 ECX8 = 1<<1,
71 EIERRINT = 1<<2,
72 DPM = 1<<3,
73 DMCE = 1<<4,
74 DSTPCLK = 1<<5,
75 ELINEAR = 1<<6,
76 DSMC = 1<<7,
77 DTLOCK = 1<<8,
78 EDCTLB = 1<<8,
79 EMMX = 1<<9,
80 DPDC = 1<<11,
81 EBRPRED = 1<<12,
82 DIC = 1<<13,
83 DDC = 1<<14,
84 DNA = 1<<15,
85 ERETSTK = 1<<16,
86 E2MMX = 1<<19,
87 EAMD3D = 1<<20,
88};
89
Paul Gortmaker148f9bb2013-06-18 18:23:59 -040090static void early_init_centaur(struct cpuinfo_x86 *c)
Yinghai Lu5fef55f2008-09-04 21:09:43 +020091{
92 switch (c->x86) {
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +010093#ifdef CONFIG_X86_32
Yinghai Lu5fef55f2008-09-04 21:09:43 +020094 case 5:
95 /* Emulate MTRRs using Centaur's MCR. */
96 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
97 break;
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +010098#endif
99 case 6:
100 if (c->x86_model >= 0xf)
101 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
102 break;
Yinghai Lu5fef55f2008-09-04 21:09:43 +0200103 }
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100104#ifdef CONFIG_X86_64
105 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
106#endif
Yinghai Lu5fef55f2008-09-04 21:09:43 +0200107}
108
Paul Gortmaker148f9bb2013-06-18 18:23:59 -0400109static void init_centaur(struct cpuinfo_x86 *c)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110{
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100111#ifdef CONFIG_X86_32
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112 char *name;
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100113 u32 fcr_set = 0;
114 u32 fcr_clr = 0;
115 u32 lo, hi, newlo;
116 u32 aa, bb, cc, dd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117
Ingo Molnaredc05e62008-02-18 03:30:47 +0100118 /*
119 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
120 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
121 */
Ingo Molnare1a94a92008-02-26 08:51:22 +0100122 clear_cpu_cap(c, 0*32+31);
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100123#endif
124 early_init_centaur(c);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125 switch (c->x86) {
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100126#ifdef CONFIG_X86_32
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100127 case 5:
Ingo Molnaredc05e62008-02-18 03:30:47 +0100128 switch (c->x86_model) {
129 case 4:
130 name = "C6";
131 fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
132 fcr_clr = DPDC;
Chen Yucong1b74dde2016-02-02 11:45:02 +0800133 pr_notice("Disabling bugged TSC.\n");
Ingo Molnare1a94a92008-02-26 08:51:22 +0100134 clear_cpu_cap(c, X86_FEATURE_TSC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135 break;
Ingo Molnaredc05e62008-02-18 03:30:47 +0100136 case 8:
137 switch (c->x86_mask) {
138 default:
139 name = "2";
140 break;
141 case 7 ... 9:
142 name = "2A";
143 break;
144 case 10 ... 15:
145 name = "2B";
146 break;
147 }
148 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
149 E2MMX|EAMD3D;
150 fcr_clr = DPDC;
Ingo Molnaredc05e62008-02-18 03:30:47 +0100151 break;
152 case 9:
153 name = "3";
154 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
155 E2MMX|EAMD3D;
156 fcr_clr = DPDC;
Ingo Molnaredc05e62008-02-18 03:30:47 +0100157 break;
158 default:
159 name = "??";
160 }
161
162 rdmsr(MSR_IDT_FCR1, lo, hi);
163 newlo = (lo|fcr_set) & (~fcr_clr);
164
165 if (newlo != lo) {
Chen Yucong1b74dde2016-02-02 11:45:02 +0800166 pr_info("Centaur FCR was 0x%X now 0x%X\n",
Ingo Molnaredc05e62008-02-18 03:30:47 +0100167 lo, newlo);
168 wrmsr(MSR_IDT_FCR1, newlo, hi);
169 } else {
Chen Yucong1b74dde2016-02-02 11:45:02 +0800170 pr_info("Centaur FCR is 0x%X\n", lo);
Ingo Molnaredc05e62008-02-18 03:30:47 +0100171 }
172 /* Emulate MTRRs using Centaur's MCR. */
Ingo Molnare1a94a92008-02-26 08:51:22 +0100173 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
Ingo Molnaredc05e62008-02-18 03:30:47 +0100174 /* Report CX8 */
Ingo Molnare1a94a92008-02-26 08:51:22 +0100175 set_cpu_cap(c, X86_FEATURE_CX8);
Ingo Molnaredc05e62008-02-18 03:30:47 +0100176 /* Set 3DNow! on Winchip 2 and above. */
177 if (c->x86_model >= 8)
Ingo Molnare1a94a92008-02-26 08:51:22 +0100178 set_cpu_cap(c, X86_FEATURE_3DNOW);
Ingo Molnaredc05e62008-02-18 03:30:47 +0100179 /* See if we can find out some more. */
180 if (cpuid_eax(0x80000000) >= 0x80000005) {
181 /* Yes, we can. */
182 cpuid(0x80000005, &aa, &bb, &cc, &dd);
183 /* Add L1 data and code cache sizes. */
184 c->x86_cache_size = (cc>>24)+(dd>>24);
185 }
186 sprintf(c->x86_model_id, "WinChip %s", name);
187 break;
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100188#endif
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100189 case 6:
Ingo Molnaredc05e62008-02-18 03:30:47 +0100190 init_c3(c);
191 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192 }
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100193#ifdef CONFIG_X86_64
194 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
195#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196}
197
Jan Beulich09dc68d2013-10-21 09:35:20 +0100198#ifdef CONFIG_X86_32
Paul Gortmaker148f9bb2013-06-18 18:23:59 -0400199static unsigned int
Ingo Molnaredc05e62008-02-18 03:30:47 +0100200centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201{
202 /* VIA C3 CPUs (670-68F) need further shifting. */
203 if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
204 size >>= 8;
205
Ingo Molnaredc05e62008-02-18 03:30:47 +0100206 /*
207 * There's also an erratum in Nehemiah stepping 1, which
208 * returns '65KB' instead of '64KB'
209 * - Note, it seems this may only be in engineering samples.
210 */
211 if ((c->x86 == 6) && (c->x86_model == 9) &&
212 (c->x86_mask == 1) && (size == 65))
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100213 size -= 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214 return size;
215}
Jan Beulich09dc68d2013-10-21 09:35:20 +0100216#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217
Paul Gortmaker148f9bb2013-06-18 18:23:59 -0400218static const struct cpu_dev centaur_cpu_dev = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219 .c_vendor = "Centaur",
220 .c_ident = { "CentaurHauls" },
Yinghai Lu5fef55f2008-09-04 21:09:43 +0200221 .c_early_init = early_init_centaur,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222 .c_init = init_centaur,
Jan Beulich09dc68d2013-10-21 09:35:20 +0100223#ifdef CONFIG_X86_32
224 .legacy_cache_size = centaur_size_cache,
225#endif
Yinghai Lu10a434f2008-09-04 21:09:45 +0200226 .c_x86_vendor = X86_VENDOR_CENTAUR,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227};
228
Yinghai Lu10a434f2008-09-04 21:09:45 +0200229cpu_dev_register(centaur_cpu_dev);