Sebastian Andrzej Siewior | 48f4c48 | 2009-03-14 12:24:02 +0100 | [diff] [blame] | 1 | #include <linux/bitops.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | #include <linux/kernel.h> |
Ingo Molnar | edc05e6 | 2008-02-18 03:30:47 +0100 | [diff] [blame] | 3 | |
Borislav Petkov | cd4d09e | 2016-01-26 22:12:04 +0100 | [diff] [blame] | 4 | #include <asm/cpufeature.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | #include <asm/e820.h> |
Jesper Juhl | 52f4a91 | 2006-03-23 02:59:50 -0800 | [diff] [blame] | 6 | #include <asm/mtrr.h> |
Sebastian Andrzej Siewior | 48f4c48 | 2009-03-14 12:24:02 +0100 | [diff] [blame] | 7 | #include <asm/msr.h> |
Ingo Molnar | edc05e6 | 2008-02-18 03:30:47 +0100 | [diff] [blame] | 8 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | #include "cpu.h" |
| 10 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | #define ACE_PRESENT (1 << 6) |
| 12 | #define ACE_ENABLED (1 << 7) |
| 13 | #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */ |
| 14 | |
| 15 | #define RNG_PRESENT (1 << 2) |
| 16 | #define RNG_ENABLED (1 << 3) |
| 17 | #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */ |
| 18 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 19 | static void init_c3(struct cpuinfo_x86 *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | { |
| 21 | u32 lo, hi; |
| 22 | |
| 23 | /* Test for Centaur Extended Feature Flags presence */ |
| 24 | if (cpuid_eax(0xC0000000) >= 0xC0000001) { |
| 25 | u32 tmp = cpuid_edx(0xC0000001); |
| 26 | |
| 27 | /* enable ACE unit, if present and disabled */ |
| 28 | if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) { |
Paolo Ciarrocchi | 29a9994 | 2008-02-17 23:30:23 +0100 | [diff] [blame] | 29 | rdmsr(MSR_VIA_FCR, lo, hi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | lo |= ACE_FCR; /* enable ACE unit */ |
Paolo Ciarrocchi | 29a9994 | 2008-02-17 23:30:23 +0100 | [diff] [blame] | 31 | wrmsr(MSR_VIA_FCR, lo, hi); |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 32 | pr_info("CPU: Enabled ACE h/w crypto\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | } |
| 34 | |
| 35 | /* enable RNG unit, if present and disabled */ |
| 36 | if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) { |
Paolo Ciarrocchi | 29a9994 | 2008-02-17 23:30:23 +0100 | [diff] [blame] | 37 | rdmsr(MSR_VIA_RNG, lo, hi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | lo |= RNG_ENABLE; /* enable RNG unit */ |
Paolo Ciarrocchi | 29a9994 | 2008-02-17 23:30:23 +0100 | [diff] [blame] | 39 | wrmsr(MSR_VIA_RNG, lo, hi); |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 40 | pr_info("CPU: Enabled h/w RNG\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | } |
| 42 | |
| 43 | /* store Centaur Extended Feature Flags as |
| 44 | * word 5 of the CPU capability bit array |
| 45 | */ |
Borislav Petkov | 39c06df | 2015-12-07 10:39:40 +0100 | [diff] [blame] | 46 | c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | } |
Sebastian Andrzej Siewior | 48f4c48 | 2009-03-14 12:24:02 +0100 | [diff] [blame] | 48 | #ifdef CONFIG_X86_32 |
Simon Arlott | 27b46d7 | 2007-10-20 01:13:56 +0200 | [diff] [blame] | 49 | /* Cyrix III family needs CX8 & PGE explicitly enabled. */ |
Timo Teräs | cb3f718 | 2011-12-15 17:11:28 +0200 | [diff] [blame] | 50 | if (c->x86_model >= 6 && c->x86_model <= 13) { |
Paolo Ciarrocchi | 29a9994 | 2008-02-17 23:30:23 +0100 | [diff] [blame] | 51 | rdmsr(MSR_VIA_FCR, lo, hi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | lo |= (1<<1 | 1<<7); |
Paolo Ciarrocchi | 29a9994 | 2008-02-17 23:30:23 +0100 | [diff] [blame] | 53 | wrmsr(MSR_VIA_FCR, lo, hi); |
Ingo Molnar | e1a94a9 | 2008-02-26 08:51:22 +0100 | [diff] [blame] | 54 | set_cpu_cap(c, X86_FEATURE_CX8); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | } |
| 56 | |
| 57 | /* Before Nehemiah, the C3's had 3dNOW! */ |
Paolo Ciarrocchi | 29a9994 | 2008-02-17 23:30:23 +0100 | [diff] [blame] | 58 | if (c->x86_model >= 6 && c->x86_model < 9) |
Ingo Molnar | e1a94a9 | 2008-02-26 08:51:22 +0100 | [diff] [blame] | 59 | set_cpu_cap(c, X86_FEATURE_3DNOW); |
Sebastian Andrzej Siewior | 48f4c48 | 2009-03-14 12:24:02 +0100 | [diff] [blame] | 60 | #endif |
| 61 | if (c->x86 == 0x6 && c->x86_model >= 0xf) { |
| 62 | c->x86_cache_alignment = c->x86_clflush_size * 2; |
| 63 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
| 64 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 65 | |
Borislav Petkov | 27c13ec | 2009-11-21 14:01:45 +0100 | [diff] [blame] | 66 | cpu_detect_cache_sizes(c); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 67 | } |
| 68 | |
Ingo Molnar | edc05e6 | 2008-02-18 03:30:47 +0100 | [diff] [blame] | 69 | enum { |
| 70 | ECX8 = 1<<1, |
| 71 | EIERRINT = 1<<2, |
| 72 | DPM = 1<<3, |
| 73 | DMCE = 1<<4, |
| 74 | DSTPCLK = 1<<5, |
| 75 | ELINEAR = 1<<6, |
| 76 | DSMC = 1<<7, |
| 77 | DTLOCK = 1<<8, |
| 78 | EDCTLB = 1<<8, |
| 79 | EMMX = 1<<9, |
| 80 | DPDC = 1<<11, |
| 81 | EBRPRED = 1<<12, |
| 82 | DIC = 1<<13, |
| 83 | DDC = 1<<14, |
| 84 | DNA = 1<<15, |
| 85 | ERETSTK = 1<<16, |
| 86 | E2MMX = 1<<19, |
| 87 | EAMD3D = 1<<20, |
| 88 | }; |
| 89 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 90 | static void early_init_centaur(struct cpuinfo_x86 *c) |
Yinghai Lu | 5fef55f | 2008-09-04 21:09:43 +0200 | [diff] [blame] | 91 | { |
| 92 | switch (c->x86) { |
Sebastian Andrzej Siewior | 48f4c48 | 2009-03-14 12:24:02 +0100 | [diff] [blame] | 93 | #ifdef CONFIG_X86_32 |
Yinghai Lu | 5fef55f | 2008-09-04 21:09:43 +0200 | [diff] [blame] | 94 | case 5: |
| 95 | /* Emulate MTRRs using Centaur's MCR. */ |
| 96 | set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); |
| 97 | break; |
Sebastian Andrzej Siewior | 48f4c48 | 2009-03-14 12:24:02 +0100 | [diff] [blame] | 98 | #endif |
| 99 | case 6: |
| 100 | if (c->x86_model >= 0xf) |
| 101 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
| 102 | break; |
Yinghai Lu | 5fef55f | 2008-09-04 21:09:43 +0200 | [diff] [blame] | 103 | } |
Sebastian Andrzej Siewior | 48f4c48 | 2009-03-14 12:24:02 +0100 | [diff] [blame] | 104 | #ifdef CONFIG_X86_64 |
| 105 | set_cpu_cap(c, X86_FEATURE_SYSENTER32); |
| 106 | #endif |
Yinghai Lu | 5fef55f | 2008-09-04 21:09:43 +0200 | [diff] [blame] | 107 | } |
| 108 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 109 | static void init_centaur(struct cpuinfo_x86 *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | { |
Sebastian Andrzej Siewior | 48f4c48 | 2009-03-14 12:24:02 +0100 | [diff] [blame] | 111 | #ifdef CONFIG_X86_32 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 112 | char *name; |
Paolo Ciarrocchi | 29a9994 | 2008-02-17 23:30:23 +0100 | [diff] [blame] | 113 | u32 fcr_set = 0; |
| 114 | u32 fcr_clr = 0; |
| 115 | u32 lo, hi, newlo; |
| 116 | u32 aa, bb, cc, dd; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 117 | |
Ingo Molnar | edc05e6 | 2008-02-18 03:30:47 +0100 | [diff] [blame] | 118 | /* |
| 119 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; |
| 120 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway |
| 121 | */ |
Ingo Molnar | e1a94a9 | 2008-02-26 08:51:22 +0100 | [diff] [blame] | 122 | clear_cpu_cap(c, 0*32+31); |
Sebastian Andrzej Siewior | 48f4c48 | 2009-03-14 12:24:02 +0100 | [diff] [blame] | 123 | #endif |
| 124 | early_init_centaur(c); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 125 | switch (c->x86) { |
Sebastian Andrzej Siewior | 48f4c48 | 2009-03-14 12:24:02 +0100 | [diff] [blame] | 126 | #ifdef CONFIG_X86_32 |
Paolo Ciarrocchi | 29a9994 | 2008-02-17 23:30:23 +0100 | [diff] [blame] | 127 | case 5: |
Ingo Molnar | edc05e6 | 2008-02-18 03:30:47 +0100 | [diff] [blame] | 128 | switch (c->x86_model) { |
| 129 | case 4: |
| 130 | name = "C6"; |
| 131 | fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK; |
| 132 | fcr_clr = DPDC; |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 133 | pr_notice("Disabling bugged TSC.\n"); |
Ingo Molnar | e1a94a9 | 2008-02-26 08:51:22 +0100 | [diff] [blame] | 134 | clear_cpu_cap(c, X86_FEATURE_TSC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 135 | break; |
Ingo Molnar | edc05e6 | 2008-02-18 03:30:47 +0100 | [diff] [blame] | 136 | case 8: |
| 137 | switch (c->x86_mask) { |
| 138 | default: |
| 139 | name = "2"; |
| 140 | break; |
| 141 | case 7 ... 9: |
| 142 | name = "2A"; |
| 143 | break; |
| 144 | case 10 ... 15: |
| 145 | name = "2B"; |
| 146 | break; |
| 147 | } |
| 148 | fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| |
| 149 | E2MMX|EAMD3D; |
| 150 | fcr_clr = DPDC; |
Ingo Molnar | edc05e6 | 2008-02-18 03:30:47 +0100 | [diff] [blame] | 151 | break; |
| 152 | case 9: |
| 153 | name = "3"; |
| 154 | fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| |
| 155 | E2MMX|EAMD3D; |
| 156 | fcr_clr = DPDC; |
Ingo Molnar | edc05e6 | 2008-02-18 03:30:47 +0100 | [diff] [blame] | 157 | break; |
| 158 | default: |
| 159 | name = "??"; |
| 160 | } |
| 161 | |
| 162 | rdmsr(MSR_IDT_FCR1, lo, hi); |
| 163 | newlo = (lo|fcr_set) & (~fcr_clr); |
| 164 | |
| 165 | if (newlo != lo) { |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 166 | pr_info("Centaur FCR was 0x%X now 0x%X\n", |
Ingo Molnar | edc05e6 | 2008-02-18 03:30:47 +0100 | [diff] [blame] | 167 | lo, newlo); |
| 168 | wrmsr(MSR_IDT_FCR1, newlo, hi); |
| 169 | } else { |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 170 | pr_info("Centaur FCR is 0x%X\n", lo); |
Ingo Molnar | edc05e6 | 2008-02-18 03:30:47 +0100 | [diff] [blame] | 171 | } |
| 172 | /* Emulate MTRRs using Centaur's MCR. */ |
Ingo Molnar | e1a94a9 | 2008-02-26 08:51:22 +0100 | [diff] [blame] | 173 | set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); |
Ingo Molnar | edc05e6 | 2008-02-18 03:30:47 +0100 | [diff] [blame] | 174 | /* Report CX8 */ |
Ingo Molnar | e1a94a9 | 2008-02-26 08:51:22 +0100 | [diff] [blame] | 175 | set_cpu_cap(c, X86_FEATURE_CX8); |
Ingo Molnar | edc05e6 | 2008-02-18 03:30:47 +0100 | [diff] [blame] | 176 | /* Set 3DNow! on Winchip 2 and above. */ |
| 177 | if (c->x86_model >= 8) |
Ingo Molnar | e1a94a9 | 2008-02-26 08:51:22 +0100 | [diff] [blame] | 178 | set_cpu_cap(c, X86_FEATURE_3DNOW); |
Ingo Molnar | edc05e6 | 2008-02-18 03:30:47 +0100 | [diff] [blame] | 179 | /* See if we can find out some more. */ |
| 180 | if (cpuid_eax(0x80000000) >= 0x80000005) { |
| 181 | /* Yes, we can. */ |
| 182 | cpuid(0x80000005, &aa, &bb, &cc, &dd); |
| 183 | /* Add L1 data and code cache sizes. */ |
| 184 | c->x86_cache_size = (cc>>24)+(dd>>24); |
| 185 | } |
| 186 | sprintf(c->x86_model_id, "WinChip %s", name); |
| 187 | break; |
Sebastian Andrzej Siewior | 48f4c48 | 2009-03-14 12:24:02 +0100 | [diff] [blame] | 188 | #endif |
Paolo Ciarrocchi | 29a9994 | 2008-02-17 23:30:23 +0100 | [diff] [blame] | 189 | case 6: |
Ingo Molnar | edc05e6 | 2008-02-18 03:30:47 +0100 | [diff] [blame] | 190 | init_c3(c); |
| 191 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 192 | } |
Sebastian Andrzej Siewior | 48f4c48 | 2009-03-14 12:24:02 +0100 | [diff] [blame] | 193 | #ifdef CONFIG_X86_64 |
| 194 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); |
| 195 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 196 | } |
| 197 | |
Jan Beulich | 09dc68d | 2013-10-21 09:35:20 +0100 | [diff] [blame] | 198 | #ifdef CONFIG_X86_32 |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 199 | static unsigned int |
Ingo Molnar | edc05e6 | 2008-02-18 03:30:47 +0100 | [diff] [blame] | 200 | centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 201 | { |
| 202 | /* VIA C3 CPUs (670-68F) need further shifting. */ |
| 203 | if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8))) |
| 204 | size >>= 8; |
| 205 | |
Ingo Molnar | edc05e6 | 2008-02-18 03:30:47 +0100 | [diff] [blame] | 206 | /* |
| 207 | * There's also an erratum in Nehemiah stepping 1, which |
| 208 | * returns '65KB' instead of '64KB' |
| 209 | * - Note, it seems this may only be in engineering samples. |
| 210 | */ |
| 211 | if ((c->x86 == 6) && (c->x86_model == 9) && |
| 212 | (c->x86_mask == 1) && (size == 65)) |
Paolo Ciarrocchi | 29a9994 | 2008-02-17 23:30:23 +0100 | [diff] [blame] | 213 | size -= 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 214 | return size; |
| 215 | } |
Jan Beulich | 09dc68d | 2013-10-21 09:35:20 +0100 | [diff] [blame] | 216 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 217 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 218 | static const struct cpu_dev centaur_cpu_dev = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 219 | .c_vendor = "Centaur", |
| 220 | .c_ident = { "CentaurHauls" }, |
Yinghai Lu | 5fef55f | 2008-09-04 21:09:43 +0200 | [diff] [blame] | 221 | .c_early_init = early_init_centaur, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 222 | .c_init = init_centaur, |
Jan Beulich | 09dc68d | 2013-10-21 09:35:20 +0100 | [diff] [blame] | 223 | #ifdef CONFIG_X86_32 |
| 224 | .legacy_cache_size = centaur_size_cache, |
| 225 | #endif |
Yinghai Lu | 10a434f | 2008-09-04 21:09:45 +0200 | [diff] [blame] | 226 | .c_x86_vendor = X86_VENDOR_CENTAUR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 227 | }; |
| 228 | |
Yinghai Lu | 10a434f | 2008-09-04 21:09:45 +0200 | [diff] [blame] | 229 | cpu_dev_register(centaur_cpu_dev); |