Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1 | /* |
| 2 | * PowerPC version |
| 3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
| 4 | * |
| 5 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP |
| 6 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> |
| 7 | * Adapted for Power Macintosh by Paul Mackerras. |
| 8 | * Low-level exception handlers and MMU support |
| 9 | * rewritten by Paul Mackerras. |
| 10 | * Copyright (C) 1996 Paul Mackerras. |
| 11 | * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). |
| 12 | * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). |
| 13 | * |
| 14 | * This file contains the low-level support and setup for the |
| 15 | * PowerPC platform, including trap and interrupt dispatch. |
| 16 | * (The PPC 8xx embedded CPUs use head_8xx.S instead.) |
| 17 | * |
| 18 | * This program is free software; you can redistribute it and/or |
| 19 | * modify it under the terms of the GNU General Public License |
| 20 | * as published by the Free Software Foundation; either version |
| 21 | * 2 of the License, or (at your option) any later version. |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #include <linux/config.h> |
Paul Mackerras | b3b8dc6 | 2005-10-10 22:20:10 +1000 | [diff] [blame] | 26 | #include <asm/reg.h> |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 27 | #include <asm/page.h> |
| 28 | #include <asm/mmu.h> |
| 29 | #include <asm/pgtable.h> |
| 30 | #include <asm/cputable.h> |
| 31 | #include <asm/cache.h> |
| 32 | #include <asm/thread_info.h> |
| 33 | #include <asm/ppc_asm.h> |
| 34 | #include <asm/asm-offsets.h> |
| 35 | |
| 36 | #ifdef CONFIG_APUS |
| 37 | #include <asm/amigappc.h> |
| 38 | #endif |
| 39 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 40 | /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */ |
| 41 | #define LOAD_BAT(n, reg, RA, RB) \ |
| 42 | /* see the comment for clear_bats() -- Cort */ \ |
| 43 | li RA,0; \ |
| 44 | mtspr SPRN_IBAT##n##U,RA; \ |
| 45 | mtspr SPRN_DBAT##n##U,RA; \ |
| 46 | lwz RA,(n*16)+0(reg); \ |
| 47 | lwz RB,(n*16)+4(reg); \ |
| 48 | mtspr SPRN_IBAT##n##U,RA; \ |
| 49 | mtspr SPRN_IBAT##n##L,RB; \ |
| 50 | beq 1f; \ |
| 51 | lwz RA,(n*16)+8(reg); \ |
| 52 | lwz RB,(n*16)+12(reg); \ |
| 53 | mtspr SPRN_DBAT##n##U,RA; \ |
| 54 | mtspr SPRN_DBAT##n##L,RB; \ |
| 55 | 1: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 56 | |
| 57 | .text |
Paul Mackerras | b3b8dc6 | 2005-10-10 22:20:10 +1000 | [diff] [blame] | 58 | .stabs "arch/powerpc/kernel/",N_SO,0,0,0f |
| 59 | .stabs "head_32.S",N_SO,0,0,0f |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 60 | 0: |
| 61 | .globl _stext |
| 62 | _stext: |
| 63 | |
| 64 | /* |
| 65 | * _start is defined this way because the XCOFF loader in the OpenFirmware |
| 66 | * on the powermac expects the entry point to be a procedure descriptor. |
| 67 | */ |
| 68 | .text |
| 69 | .globl _start |
| 70 | _start: |
| 71 | /* |
| 72 | * These are here for legacy reasons, the kernel used to |
| 73 | * need to look like a coff function entry for the pmac |
| 74 | * but we're always started by some kind of bootloader now. |
| 75 | * -- Cort |
| 76 | */ |
| 77 | nop /* used by __secondary_hold on prep (mtx) and chrp smp */ |
| 78 | nop /* used by __secondary_hold on prep (mtx) and chrp smp */ |
| 79 | nop |
| 80 | |
| 81 | /* PMAC |
| 82 | * Enter here with the kernel text, data and bss loaded starting at |
| 83 | * 0, running with virtual == physical mapping. |
| 84 | * r5 points to the prom entry point (the client interface handler |
| 85 | * address). Address translation is turned on, with the prom |
| 86 | * managing the hash table. Interrupts are disabled. The stack |
| 87 | * pointer (r1) points to just below the end of the half-meg region |
| 88 | * from 0x380000 - 0x400000, which is mapped in already. |
| 89 | * |
| 90 | * If we are booted from MacOS via BootX, we enter with the kernel |
| 91 | * image loaded somewhere, and the following values in registers: |
| 92 | * r3: 'BooX' (0x426f6f58) |
| 93 | * r4: virtual address of boot_infos_t |
| 94 | * r5: 0 |
| 95 | * |
| 96 | * APUS |
| 97 | * r3: 'APUS' |
| 98 | * r4: physical address of memory base |
| 99 | * Linux/m68k style BootInfo structure at &_end. |
| 100 | * |
| 101 | * PREP |
| 102 | * This is jumped to on prep systems right after the kernel is relocated |
| 103 | * to its proper place in memory by the boot loader. The expected layout |
| 104 | * of the regs is: |
| 105 | * r3: ptr to residual data |
| 106 | * r4: initrd_start or if no initrd then 0 |
| 107 | * r5: initrd_end - unused if r4 is 0 |
| 108 | * r6: Start of command line string |
| 109 | * r7: End of command line string |
| 110 | * |
| 111 | * This just gets a minimal mmu environment setup so we can call |
| 112 | * start_here() to do the real work. |
| 113 | * -- Cort |
| 114 | */ |
| 115 | |
| 116 | .globl __start |
| 117 | __start: |
| 118 | /* |
| 119 | * We have to do any OF calls before we map ourselves to KERNELBASE, |
| 120 | * because OF may have I/O devices mapped into that area |
| 121 | * (particularly on CHRP). |
| 122 | */ |
Paul Mackerras | 9b6b563 | 2005-10-06 12:06:20 +1000 | [diff] [blame] | 123 | cmpwi 0,r5,0 |
| 124 | beq 1f |
| 125 | bl prom_init |
| 126 | trap |
| 127 | |
| 128 | 1: mr r31,r3 /* save parameters */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 129 | mr r30,r4 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 130 | li r24,0 /* cpu # */ |
| 131 | |
| 132 | /* |
| 133 | * early_init() does the early machine identification and does |
| 134 | * the necessary low-level setup and clears the BSS |
| 135 | * -- Cort <cort@fsmlabs.com> |
| 136 | */ |
| 137 | bl early_init |
| 138 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 139 | #ifdef CONFIG_APUS |
| 140 | /* On APUS the __va/__pa constants need to be set to the correct |
| 141 | * values before continuing. |
| 142 | */ |
| 143 | mr r4,r30 |
| 144 | bl fix_mem_constants |
| 145 | #endif /* CONFIG_APUS */ |
| 146 | |
| 147 | /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains |
| 148 | * the physical address we are running at, returned by early_init() |
| 149 | */ |
| 150 | bl mmu_off |
| 151 | __after_mmu_off: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 152 | bl clear_bats |
| 153 | bl flush_tlbs |
| 154 | |
| 155 | bl initial_bats |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 156 | |
| 157 | /* |
| 158 | * Call setup_cpu for CPU 0 and initialize 6xx Idle |
| 159 | */ |
| 160 | bl reloc_offset |
| 161 | li r24,0 /* cpu# */ |
| 162 | bl call_setup_cpu /* Call setup_cpu for this CPU */ |
| 163 | #ifdef CONFIG_6xx |
| 164 | bl reloc_offset |
| 165 | bl init_idle_6xx |
| 166 | #endif /* CONFIG_6xx */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 167 | |
| 168 | |
| 169 | #ifndef CONFIG_APUS |
| 170 | /* |
| 171 | * We need to run with _start at physical address 0. |
| 172 | * On CHRP, we are loaded at 0x10000 since OF on CHRP uses |
| 173 | * the exception vectors at 0 (and therefore this copy |
| 174 | * overwrites OF's exception vectors with our own). |
Paul Mackerras | 9b6b563 | 2005-10-06 12:06:20 +1000 | [diff] [blame] | 175 | * The MMU is off at this point. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 176 | */ |
| 177 | bl reloc_offset |
| 178 | mr r26,r3 |
| 179 | addis r4,r3,KERNELBASE@h /* current address of _start */ |
| 180 | cmpwi 0,r4,0 /* are we already running at 0? */ |
| 181 | bne relocate_kernel |
| 182 | #endif /* CONFIG_APUS */ |
| 183 | /* |
| 184 | * we now have the 1st 16M of ram mapped with the bats. |
| 185 | * prep needs the mmu to be turned on here, but pmac already has it on. |
| 186 | * this shouldn't bother the pmac since it just gets turned on again |
| 187 | * as we jump to our code at KERNELBASE. -- Cort |
| 188 | * Actually no, pmac doesn't have it on any more. BootX enters with MMU |
| 189 | * off, and in other cases, we now turn it off before changing BATs above. |
| 190 | */ |
| 191 | turn_on_mmu: |
| 192 | mfmsr r0 |
| 193 | ori r0,r0,MSR_DR|MSR_IR |
| 194 | mtspr SPRN_SRR1,r0 |
| 195 | lis r0,start_here@h |
| 196 | ori r0,r0,start_here@l |
| 197 | mtspr SPRN_SRR0,r0 |
| 198 | SYNC |
| 199 | RFI /* enables MMU */ |
| 200 | |
| 201 | /* |
| 202 | * We need __secondary_hold as a place to hold the other cpus on |
| 203 | * an SMP machine, even when we are running a UP kernel. |
| 204 | */ |
| 205 | . = 0xc0 /* for prep bootloader */ |
| 206 | li r3,1 /* MTX only has 1 cpu */ |
| 207 | .globl __secondary_hold |
| 208 | __secondary_hold: |
| 209 | /* tell the master we're here */ |
Paul Mackerras | bbd0abd | 2005-10-26 21:45:56 +1000 | [diff] [blame] | 210 | stw r3,__secondary_hold_acknowledge@l(0) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 211 | #ifdef CONFIG_SMP |
| 212 | 100: lwz r4,0(0) |
| 213 | /* wait until we're told to start */ |
| 214 | cmpw 0,r4,r3 |
| 215 | bne 100b |
| 216 | /* our cpu # was at addr 0 - go */ |
| 217 | mr r24,r3 /* cpu # */ |
| 218 | b __secondary_start |
| 219 | #else |
| 220 | b . |
| 221 | #endif /* CONFIG_SMP */ |
| 222 | |
Paul Mackerras | bbd0abd | 2005-10-26 21:45:56 +1000 | [diff] [blame] | 223 | .globl __secondary_hold_spinloop |
| 224 | __secondary_hold_spinloop: |
| 225 | .long 0 |
| 226 | .globl __secondary_hold_acknowledge |
| 227 | __secondary_hold_acknowledge: |
| 228 | .long -1 |
| 229 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 230 | /* |
| 231 | * Exception entry code. This code runs with address translation |
| 232 | * turned off, i.e. using physical addresses. |
| 233 | * We assume sprg3 has the physical address of the current |
| 234 | * task's thread_struct. |
| 235 | */ |
| 236 | #define EXCEPTION_PROLOG \ |
| 237 | mtspr SPRN_SPRG0,r10; \ |
| 238 | mtspr SPRN_SPRG1,r11; \ |
| 239 | mfcr r10; \ |
| 240 | EXCEPTION_PROLOG_1; \ |
| 241 | EXCEPTION_PROLOG_2 |
| 242 | |
| 243 | #define EXCEPTION_PROLOG_1 \ |
| 244 | mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ |
| 245 | andi. r11,r11,MSR_PR; \ |
| 246 | tophys(r11,r1); /* use tophys(r1) if kernel */ \ |
| 247 | beq 1f; \ |
| 248 | mfspr r11,SPRN_SPRG3; \ |
| 249 | lwz r11,THREAD_INFO-THREAD(r11); \ |
| 250 | addi r11,r11,THREAD_SIZE; \ |
| 251 | tophys(r11,r11); \ |
| 252 | 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ |
| 253 | |
| 254 | |
| 255 | #define EXCEPTION_PROLOG_2 \ |
| 256 | CLR_TOP32(r11); \ |
| 257 | stw r10,_CCR(r11); /* save registers */ \ |
| 258 | stw r12,GPR12(r11); \ |
| 259 | stw r9,GPR9(r11); \ |
| 260 | mfspr r10,SPRN_SPRG0; \ |
| 261 | stw r10,GPR10(r11); \ |
| 262 | mfspr r12,SPRN_SPRG1; \ |
| 263 | stw r12,GPR11(r11); \ |
| 264 | mflr r10; \ |
| 265 | stw r10,_LINK(r11); \ |
| 266 | mfspr r12,SPRN_SRR0; \ |
| 267 | mfspr r9,SPRN_SRR1; \ |
| 268 | stw r1,GPR1(r11); \ |
| 269 | stw r1,0(r11); \ |
| 270 | tovirt(r1,r11); /* set new kernel sp */ \ |
| 271 | li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ |
| 272 | MTMSRD(r10); /* (except for mach check in rtas) */ \ |
| 273 | stw r0,GPR0(r11); \ |
Paul Mackerras | f78541d | 2005-10-28 22:53:37 +1000 | [diff] [blame] | 274 | lis r10,0x7265; /* put exception frame marker */ \ |
| 275 | addi r10,r10,0x6773; \ |
| 276 | stw r10,8(r11); \ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 277 | SAVE_4GPRS(3, r11); \ |
| 278 | SAVE_2GPRS(7, r11) |
| 279 | |
| 280 | /* |
| 281 | * Note: code which follows this uses cr0.eq (set if from kernel), |
| 282 | * r11, r12 (SRR0), and r9 (SRR1). |
| 283 | * |
| 284 | * Note2: once we have set r1 we are in a position to take exceptions |
| 285 | * again, and we could thus set MSR:RI at that point. |
| 286 | */ |
| 287 | |
| 288 | /* |
| 289 | * Exception vectors. |
| 290 | */ |
| 291 | #define EXCEPTION(n, label, hdlr, xfer) \ |
| 292 | . = n; \ |
| 293 | label: \ |
| 294 | EXCEPTION_PROLOG; \ |
| 295 | addi r3,r1,STACK_FRAME_OVERHEAD; \ |
| 296 | xfer(n, hdlr) |
| 297 | |
| 298 | #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ |
| 299 | li r10,trap; \ |
Paul Mackerras | d73e0c9 | 2005-10-28 22:45:25 +1000 | [diff] [blame] | 300 | stw r10,_TRAP(r11); \ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 301 | li r10,MSR_KERNEL; \ |
| 302 | copyee(r10, r9); \ |
| 303 | bl tfer; \ |
| 304 | i##n: \ |
| 305 | .long hdlr; \ |
| 306 | .long ret |
| 307 | |
| 308 | #define COPY_EE(d, s) rlwimi d,s,0,16,16 |
| 309 | #define NOCOPY(d, s) |
| 310 | |
| 311 | #define EXC_XFER_STD(n, hdlr) \ |
| 312 | EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ |
| 313 | ret_from_except_full) |
| 314 | |
| 315 | #define EXC_XFER_LITE(n, hdlr) \ |
| 316 | EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ |
| 317 | ret_from_except) |
| 318 | |
| 319 | #define EXC_XFER_EE(n, hdlr) \ |
| 320 | EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ |
| 321 | ret_from_except_full) |
| 322 | |
| 323 | #define EXC_XFER_EE_LITE(n, hdlr) \ |
| 324 | EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ |
| 325 | ret_from_except) |
| 326 | |
| 327 | /* System reset */ |
| 328 | /* core99 pmac starts the seconary here by changing the vector, and |
Stephen Rothwell | dc1c1ca | 2005-10-01 18:43:42 +1000 | [diff] [blame] | 329 | putting it back to what it was (unknown_exception) when done. */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 330 | #if defined(CONFIG_GEMINI) && defined(CONFIG_SMP) |
| 331 | . = 0x100 |
| 332 | b __secondary_start_gemini |
| 333 | #else |
Stephen Rothwell | dc1c1ca | 2005-10-01 18:43:42 +1000 | [diff] [blame] | 334 | EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 335 | #endif |
| 336 | |
| 337 | /* Machine check */ |
| 338 | /* |
| 339 | * On CHRP, this is complicated by the fact that we could get a |
| 340 | * machine check inside RTAS, and we have no guarantee that certain |
| 341 | * critical registers will have the values we expect. The set of |
| 342 | * registers that might have bad values includes all the GPRs |
| 343 | * and all the BATs. We indicate that we are in RTAS by putting |
| 344 | * a non-zero value, the address of the exception frame to use, |
| 345 | * in SPRG2. The machine check handler checks SPRG2 and uses its |
| 346 | * value if it is non-zero. If we ever needed to free up SPRG2, |
| 347 | * we could use a field in the thread_info or thread_struct instead. |
| 348 | * (Other exception handlers assume that r1 is a valid kernel stack |
| 349 | * pointer when we take an exception from supervisor mode.) |
| 350 | * -- paulus. |
| 351 | */ |
| 352 | . = 0x200 |
| 353 | mtspr SPRN_SPRG0,r10 |
| 354 | mtspr SPRN_SPRG1,r11 |
| 355 | mfcr r10 |
| 356 | #ifdef CONFIG_PPC_CHRP |
| 357 | mfspr r11,SPRN_SPRG2 |
| 358 | cmpwi 0,r11,0 |
| 359 | bne 7f |
| 360 | #endif /* CONFIG_PPC_CHRP */ |
| 361 | EXCEPTION_PROLOG_1 |
| 362 | 7: EXCEPTION_PROLOG_2 |
| 363 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 364 | #ifdef CONFIG_PPC_CHRP |
| 365 | mfspr r4,SPRN_SPRG2 |
| 366 | cmpwi cr1,r4,0 |
| 367 | bne cr1,1f |
| 368 | #endif |
Stephen Rothwell | dc1c1ca | 2005-10-01 18:43:42 +1000 | [diff] [blame] | 369 | EXC_XFER_STD(0x200, machine_check_exception) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 370 | #ifdef CONFIG_PPC_CHRP |
| 371 | 1: b machine_check_in_rtas |
| 372 | #endif |
| 373 | |
| 374 | /* Data access exception. */ |
| 375 | . = 0x300 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 376 | DataAccess: |
| 377 | EXCEPTION_PROLOG |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 378 | mfspr r10,SPRN_DSISR |
| 379 | andis. r0,r10,0xa470 /* weird error? */ |
| 380 | bne 1f /* if not, try to put a PTE */ |
| 381 | mfspr r4,SPRN_DAR /* into the hash table */ |
| 382 | rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */ |
| 383 | bl hash_page |
| 384 | 1: stw r10,_DSISR(r11) |
| 385 | mr r5,r10 |
| 386 | mfspr r4,SPRN_DAR |
| 387 | EXC_XFER_EE_LITE(0x300, handle_page_fault) |
| 388 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 389 | |
| 390 | /* Instruction access exception. */ |
| 391 | . = 0x400 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 392 | InstructionAccess: |
| 393 | EXCEPTION_PROLOG |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 394 | andis. r0,r9,0x4000 /* no pte found? */ |
| 395 | beq 1f /* if so, try to put a PTE */ |
| 396 | li r3,0 /* into the hash table */ |
| 397 | mr r4,r12 /* SRR0 is fault address */ |
| 398 | bl hash_page |
| 399 | 1: mr r4,r12 |
| 400 | mr r5,r9 |
| 401 | EXC_XFER_EE_LITE(0x400, handle_page_fault) |
| 402 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 403 | /* External interrupt */ |
| 404 | EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) |
| 405 | |
| 406 | /* Alignment exception */ |
| 407 | . = 0x600 |
| 408 | Alignment: |
| 409 | EXCEPTION_PROLOG |
| 410 | mfspr r4,SPRN_DAR |
| 411 | stw r4,_DAR(r11) |
| 412 | mfspr r5,SPRN_DSISR |
| 413 | stw r5,_DSISR(r11) |
| 414 | addi r3,r1,STACK_FRAME_OVERHEAD |
Stephen Rothwell | dc1c1ca | 2005-10-01 18:43:42 +1000 | [diff] [blame] | 415 | EXC_XFER_EE(0x600, alignment_exception) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 416 | |
| 417 | /* Program check exception */ |
Stephen Rothwell | dc1c1ca | 2005-10-01 18:43:42 +1000 | [diff] [blame] | 418 | EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 419 | |
| 420 | /* Floating-point unavailable */ |
| 421 | . = 0x800 |
| 422 | FPUnavailable: |
| 423 | EXCEPTION_PROLOG |
| 424 | bne load_up_fpu /* if from user, just load it up */ |
| 425 | addi r3,r1,STACK_FRAME_OVERHEAD |
Paul Mackerras | 8dad3f9 | 2005-10-06 13:27:05 +1000 | [diff] [blame] | 426 | EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 427 | |
| 428 | /* Decrementer */ |
| 429 | EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) |
| 430 | |
Stephen Rothwell | dc1c1ca | 2005-10-01 18:43:42 +1000 | [diff] [blame] | 431 | EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) |
| 432 | EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 433 | |
| 434 | /* System call */ |
| 435 | . = 0xc00 |
| 436 | SystemCall: |
| 437 | EXCEPTION_PROLOG |
| 438 | EXC_XFER_EE_LITE(0xc00, DoSyscall) |
| 439 | |
| 440 | /* Single step - not used on 601 */ |
Stephen Rothwell | dc1c1ca | 2005-10-01 18:43:42 +1000 | [diff] [blame] | 441 | EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) |
| 442 | EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 443 | |
| 444 | /* |
| 445 | * The Altivec unavailable trap is at 0x0f20. Foo. |
| 446 | * We effectively remap it to 0x3000. |
| 447 | * We include an altivec unavailable exception vector even if |
| 448 | * not configured for Altivec, so that you can't panic a |
| 449 | * non-altivec kernel running on a machine with altivec just |
| 450 | * by executing an altivec instruction. |
| 451 | */ |
| 452 | . = 0xf00 |
| 453 | b Trap_0f |
| 454 | |
| 455 | . = 0xf20 |
| 456 | b AltiVecUnavailable |
| 457 | |
| 458 | Trap_0f: |
| 459 | EXCEPTION_PROLOG |
| 460 | addi r3,r1,STACK_FRAME_OVERHEAD |
Stephen Rothwell | dc1c1ca | 2005-10-01 18:43:42 +1000 | [diff] [blame] | 461 | EXC_XFER_EE(0xf00, unknown_exception) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 462 | |
| 463 | /* |
| 464 | * Handle TLB miss for instruction on 603/603e. |
| 465 | * Note: we get an alternate set of r0 - r3 to use automatically. |
| 466 | */ |
| 467 | . = 0x1000 |
| 468 | InstructionTLBMiss: |
| 469 | /* |
| 470 | * r0: stored ctr |
| 471 | * r1: linux style pte ( later becomes ppc hardware pte ) |
| 472 | * r2: ptr to linux-style pte |
| 473 | * r3: scratch |
| 474 | */ |
| 475 | mfctr r0 |
| 476 | /* Get PTE (linux-style) and check access */ |
| 477 | mfspr r3,SPRN_IMISS |
| 478 | lis r1,KERNELBASE@h /* check if kernel address */ |
| 479 | cmplw 0,r3,r1 |
| 480 | mfspr r2,SPRN_SPRG3 |
| 481 | li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */ |
| 482 | lwz r2,PGDIR(r2) |
| 483 | blt+ 112f |
| 484 | lis r2,swapper_pg_dir@ha /* if kernel address, use */ |
| 485 | addi r2,r2,swapper_pg_dir@l /* kernel page table */ |
| 486 | mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ |
| 487 | rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ |
| 488 | 112: tophys(r2,r2) |
| 489 | rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ |
| 490 | lwz r2,0(r2) /* get pmd entry */ |
| 491 | rlwinm. r2,r2,0,0,19 /* extract address of pte page */ |
| 492 | beq- InstructionAddressInvalid /* return if no mapping */ |
| 493 | rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ |
| 494 | lwz r3,0(r2) /* get linux-style pte */ |
| 495 | andc. r1,r1,r3 /* check access & ~permission */ |
| 496 | bne- InstructionAddressInvalid /* return if access not permitted */ |
| 497 | ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */ |
| 498 | /* |
| 499 | * NOTE! We are assuming this is not an SMP system, otherwise |
| 500 | * we would need to update the pte atomically with lwarx/stwcx. |
| 501 | */ |
| 502 | stw r3,0(r2) /* update PTE (accessed bit) */ |
| 503 | /* Convert linux-style PTE to low word of PPC-style PTE */ |
| 504 | rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */ |
| 505 | rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ |
| 506 | and r1,r1,r2 /* writable if _RW and _DIRTY */ |
| 507 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ |
| 508 | rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ |
| 509 | ori r1,r1,0xe14 /* clear out reserved bits and M */ |
| 510 | andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ |
| 511 | mtspr SPRN_RPA,r1 |
| 512 | mfspr r3,SPRN_IMISS |
| 513 | tlbli r3 |
| 514 | mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ |
| 515 | mtcrf 0x80,r3 |
| 516 | rfi |
| 517 | InstructionAddressInvalid: |
| 518 | mfspr r3,SPRN_SRR1 |
| 519 | rlwinm r1,r3,9,6,6 /* Get load/store bit */ |
| 520 | |
| 521 | addis r1,r1,0x2000 |
| 522 | mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */ |
| 523 | mtctr r0 /* Restore CTR */ |
| 524 | andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */ |
| 525 | or r2,r2,r1 |
| 526 | mtspr SPRN_SRR1,r2 |
| 527 | mfspr r1,SPRN_IMISS /* Get failing address */ |
| 528 | rlwinm. r2,r2,0,31,31 /* Check for little endian access */ |
| 529 | rlwimi r2,r2,1,30,30 /* change 1 -> 3 */ |
| 530 | xor r1,r1,r2 |
| 531 | mtspr SPRN_DAR,r1 /* Set fault address */ |
| 532 | mfmsr r0 /* Restore "normal" registers */ |
| 533 | xoris r0,r0,MSR_TGPR>>16 |
| 534 | mtcrf 0x80,r3 /* Restore CR0 */ |
| 535 | mtmsr r0 |
| 536 | b InstructionAccess |
| 537 | |
| 538 | /* |
| 539 | * Handle TLB miss for DATA Load operation on 603/603e |
| 540 | */ |
| 541 | . = 0x1100 |
| 542 | DataLoadTLBMiss: |
| 543 | /* |
| 544 | * r0: stored ctr |
| 545 | * r1: linux style pte ( later becomes ppc hardware pte ) |
| 546 | * r2: ptr to linux-style pte |
| 547 | * r3: scratch |
| 548 | */ |
| 549 | mfctr r0 |
| 550 | /* Get PTE (linux-style) and check access */ |
| 551 | mfspr r3,SPRN_DMISS |
| 552 | lis r1,KERNELBASE@h /* check if kernel address */ |
| 553 | cmplw 0,r3,r1 |
| 554 | mfspr r2,SPRN_SPRG3 |
| 555 | li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */ |
| 556 | lwz r2,PGDIR(r2) |
| 557 | blt+ 112f |
| 558 | lis r2,swapper_pg_dir@ha /* if kernel address, use */ |
| 559 | addi r2,r2,swapper_pg_dir@l /* kernel page table */ |
| 560 | mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ |
| 561 | rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ |
| 562 | 112: tophys(r2,r2) |
| 563 | rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ |
| 564 | lwz r2,0(r2) /* get pmd entry */ |
| 565 | rlwinm. r2,r2,0,0,19 /* extract address of pte page */ |
| 566 | beq- DataAddressInvalid /* return if no mapping */ |
| 567 | rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ |
| 568 | lwz r3,0(r2) /* get linux-style pte */ |
| 569 | andc. r1,r1,r3 /* check access & ~permission */ |
| 570 | bne- DataAddressInvalid /* return if access not permitted */ |
| 571 | ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */ |
| 572 | /* |
| 573 | * NOTE! We are assuming this is not an SMP system, otherwise |
| 574 | * we would need to update the pte atomically with lwarx/stwcx. |
| 575 | */ |
| 576 | stw r3,0(r2) /* update PTE (accessed bit) */ |
| 577 | /* Convert linux-style PTE to low word of PPC-style PTE */ |
| 578 | rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */ |
| 579 | rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ |
| 580 | and r1,r1,r2 /* writable if _RW and _DIRTY */ |
| 581 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ |
| 582 | rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ |
| 583 | ori r1,r1,0xe14 /* clear out reserved bits and M */ |
| 584 | andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ |
| 585 | mtspr SPRN_RPA,r1 |
| 586 | mfspr r3,SPRN_DMISS |
| 587 | tlbld r3 |
| 588 | mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ |
| 589 | mtcrf 0x80,r3 |
| 590 | rfi |
| 591 | DataAddressInvalid: |
| 592 | mfspr r3,SPRN_SRR1 |
| 593 | rlwinm r1,r3,9,6,6 /* Get load/store bit */ |
| 594 | addis r1,r1,0x2000 |
| 595 | mtspr SPRN_DSISR,r1 |
| 596 | mtctr r0 /* Restore CTR */ |
| 597 | andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */ |
| 598 | mtspr SPRN_SRR1,r2 |
| 599 | mfspr r1,SPRN_DMISS /* Get failing address */ |
| 600 | rlwinm. r2,r2,0,31,31 /* Check for little endian access */ |
| 601 | beq 20f /* Jump if big endian */ |
| 602 | xori r1,r1,3 |
| 603 | 20: mtspr SPRN_DAR,r1 /* Set fault address */ |
| 604 | mfmsr r0 /* Restore "normal" registers */ |
| 605 | xoris r0,r0,MSR_TGPR>>16 |
| 606 | mtcrf 0x80,r3 /* Restore CR0 */ |
| 607 | mtmsr r0 |
| 608 | b DataAccess |
| 609 | |
| 610 | /* |
| 611 | * Handle TLB miss for DATA Store on 603/603e |
| 612 | */ |
| 613 | . = 0x1200 |
| 614 | DataStoreTLBMiss: |
| 615 | /* |
| 616 | * r0: stored ctr |
| 617 | * r1: linux style pte ( later becomes ppc hardware pte ) |
| 618 | * r2: ptr to linux-style pte |
| 619 | * r3: scratch |
| 620 | */ |
| 621 | mfctr r0 |
| 622 | /* Get PTE (linux-style) and check access */ |
| 623 | mfspr r3,SPRN_DMISS |
| 624 | lis r1,KERNELBASE@h /* check if kernel address */ |
| 625 | cmplw 0,r3,r1 |
| 626 | mfspr r2,SPRN_SPRG3 |
| 627 | li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */ |
| 628 | lwz r2,PGDIR(r2) |
| 629 | blt+ 112f |
| 630 | lis r2,swapper_pg_dir@ha /* if kernel address, use */ |
| 631 | addi r2,r2,swapper_pg_dir@l /* kernel page table */ |
| 632 | mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ |
| 633 | rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ |
| 634 | 112: tophys(r2,r2) |
| 635 | rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ |
| 636 | lwz r2,0(r2) /* get pmd entry */ |
| 637 | rlwinm. r2,r2,0,0,19 /* extract address of pte page */ |
| 638 | beq- DataAddressInvalid /* return if no mapping */ |
| 639 | rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ |
| 640 | lwz r3,0(r2) /* get linux-style pte */ |
| 641 | andc. r1,r1,r3 /* check access & ~permission */ |
| 642 | bne- DataAddressInvalid /* return if access not permitted */ |
| 643 | ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY |
| 644 | /* |
| 645 | * NOTE! We are assuming this is not an SMP system, otherwise |
| 646 | * we would need to update the pte atomically with lwarx/stwcx. |
| 647 | */ |
| 648 | stw r3,0(r2) /* update PTE (accessed/dirty bits) */ |
| 649 | /* Convert linux-style PTE to low word of PPC-style PTE */ |
| 650 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ |
| 651 | li r1,0xe15 /* clear out reserved bits and M */ |
| 652 | andc r1,r3,r1 /* PP = user? 2: 0 */ |
| 653 | mtspr SPRN_RPA,r1 |
| 654 | mfspr r3,SPRN_DMISS |
| 655 | tlbld r3 |
| 656 | mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ |
| 657 | mtcrf 0x80,r3 |
| 658 | rfi |
| 659 | |
| 660 | #ifndef CONFIG_ALTIVEC |
Stephen Rothwell | dc1c1ca | 2005-10-01 18:43:42 +1000 | [diff] [blame] | 661 | #define altivec_assist_exception unknown_exception |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 662 | #endif |
| 663 | |
Stephen Rothwell | dc1c1ca | 2005-10-01 18:43:42 +1000 | [diff] [blame] | 664 | EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 665 | EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE) |
Stephen Rothwell | dc1c1ca | 2005-10-01 18:43:42 +1000 | [diff] [blame] | 666 | EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) |
Stephen Rothwell | dc1c1ca | 2005-10-01 18:43:42 +1000 | [diff] [blame] | 667 | EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 668 | EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD) |
Stephen Rothwell | dc1c1ca | 2005-10-01 18:43:42 +1000 | [diff] [blame] | 669 | EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) |
Stephen Rothwell | dc1c1ca | 2005-10-01 18:43:42 +1000 | [diff] [blame] | 670 | EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) |
| 671 | EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) |
| 672 | EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) |
| 673 | EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) |
| 674 | EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) |
| 675 | EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) |
| 676 | EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 677 | EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE) |
Stephen Rothwell | dc1c1ca | 2005-10-01 18:43:42 +1000 | [diff] [blame] | 678 | EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE) |
| 679 | EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE) |
| 680 | EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE) |
| 681 | EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE) |
| 682 | EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE) |
| 683 | EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE) |
| 684 | EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE) |
| 685 | EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE) |
| 686 | EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE) |
| 687 | EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE) |
| 688 | EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE) |
| 689 | EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE) |
| 690 | EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE) |
| 691 | EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE) |
| 692 | EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 693 | |
| 694 | .globl mol_trampoline |
| 695 | .set mol_trampoline, i0x2f00 |
| 696 | |
| 697 | . = 0x3000 |
| 698 | |
| 699 | AltiVecUnavailable: |
| 700 | EXCEPTION_PROLOG |
| 701 | #ifdef CONFIG_ALTIVEC |
| 702 | bne load_up_altivec /* if from user, just load it up */ |
| 703 | #endif /* CONFIG_ALTIVEC */ |
Stephen Rothwell | dc1c1ca | 2005-10-01 18:43:42 +1000 | [diff] [blame] | 704 | EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 705 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 706 | #ifdef CONFIG_ALTIVEC |
| 707 | /* Note that the AltiVec support is closely modeled after the FP |
| 708 | * support. Changes to one are likely to be applicable to the |
| 709 | * other! */ |
| 710 | load_up_altivec: |
| 711 | /* |
| 712 | * Disable AltiVec for the task which had AltiVec previously, |
| 713 | * and save its AltiVec registers in its thread_struct. |
| 714 | * Enables AltiVec for use in the kernel on return. |
| 715 | * On SMP we know the AltiVec units are free, since we give it up every |
| 716 | * switch. -- Kumar |
| 717 | */ |
| 718 | mfmsr r5 |
| 719 | oris r5,r5,MSR_VEC@h |
| 720 | MTMSRD(r5) /* enable use of AltiVec now */ |
| 721 | isync |
| 722 | /* |
| 723 | * For SMP, we don't do lazy AltiVec switching because it just gets too |
| 724 | * horrendously complex, especially when a task switches from one CPU |
| 725 | * to another. Instead we call giveup_altivec in switch_to. |
| 726 | */ |
| 727 | #ifndef CONFIG_SMP |
| 728 | tophys(r6,0) |
| 729 | addis r3,r6,last_task_used_altivec@ha |
| 730 | lwz r4,last_task_used_altivec@l(r3) |
| 731 | cmpwi 0,r4,0 |
| 732 | beq 1f |
| 733 | add r4,r4,r6 |
| 734 | addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */ |
| 735 | SAVE_32VRS(0,r10,r4) |
| 736 | mfvscr vr0 |
| 737 | li r10,THREAD_VSCR |
| 738 | stvx vr0,r10,r4 |
| 739 | lwz r5,PT_REGS(r4) |
| 740 | add r5,r5,r6 |
| 741 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) |
| 742 | lis r10,MSR_VEC@h |
| 743 | andc r4,r4,r10 /* disable altivec for previous task */ |
| 744 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) |
| 745 | 1: |
| 746 | #endif /* CONFIG_SMP */ |
| 747 | /* enable use of AltiVec after return */ |
| 748 | oris r9,r9,MSR_VEC@h |
| 749 | mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ |
| 750 | li r4,1 |
| 751 | li r10,THREAD_VSCR |
| 752 | stw r4,THREAD_USED_VR(r5) |
| 753 | lvx vr0,r10,r5 |
| 754 | mtvscr vr0 |
| 755 | REST_32VRS(0,r10,r5) |
| 756 | #ifndef CONFIG_SMP |
| 757 | subi r4,r5,THREAD |
| 758 | sub r4,r4,r6 |
| 759 | stw r4,last_task_used_altivec@l(r3) |
| 760 | #endif /* CONFIG_SMP */ |
| 761 | /* restore registers and return */ |
| 762 | /* we haven't used ctr or xer or lr */ |
| 763 | b fast_exception_return |
| 764 | |
| 765 | /* |
| 766 | * AltiVec unavailable trap from kernel - print a message, but let |
| 767 | * the task use AltiVec in the kernel until it returns to user mode. |
| 768 | */ |
| 769 | KernelAltiVec: |
| 770 | lwz r3,_MSR(r1) |
| 771 | oris r3,r3,MSR_VEC@h |
| 772 | stw r3,_MSR(r1) /* enable use of AltiVec after return */ |
| 773 | lis r3,87f@h |
| 774 | ori r3,r3,87f@l |
| 775 | mr r4,r2 /* current */ |
| 776 | lwz r5,_NIP(r1) |
| 777 | bl printk |
| 778 | b ret_from_except |
| 779 | 87: .string "AltiVec used in kernel (task=%p, pc=%x) \n" |
| 780 | .align 4,0 |
| 781 | |
| 782 | /* |
| 783 | * giveup_altivec(tsk) |
| 784 | * Disable AltiVec for the task given as the argument, |
| 785 | * and save the AltiVec registers in its thread_struct. |
| 786 | * Enables AltiVec for use in the kernel on return. |
| 787 | */ |
| 788 | |
| 789 | .globl giveup_altivec |
| 790 | giveup_altivec: |
| 791 | mfmsr r5 |
| 792 | oris r5,r5,MSR_VEC@h |
| 793 | SYNC |
| 794 | MTMSRD(r5) /* enable use of AltiVec now */ |
| 795 | isync |
| 796 | cmpwi 0,r3,0 |
| 797 | beqlr- /* if no previous owner, done */ |
| 798 | addi r3,r3,THREAD /* want THREAD of task */ |
| 799 | lwz r5,PT_REGS(r3) |
| 800 | cmpwi 0,r5,0 |
| 801 | SAVE_32VRS(0, r4, r3) |
| 802 | mfvscr vr0 |
| 803 | li r4,THREAD_VSCR |
| 804 | stvx vr0,r4,r3 |
| 805 | beq 1f |
| 806 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) |
| 807 | lis r3,MSR_VEC@h |
| 808 | andc r4,r4,r3 /* disable AltiVec for previous task */ |
| 809 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) |
| 810 | 1: |
| 811 | #ifndef CONFIG_SMP |
| 812 | li r5,0 |
| 813 | lis r4,last_task_used_altivec@ha |
| 814 | stw r5,last_task_used_altivec@l(r4) |
| 815 | #endif /* CONFIG_SMP */ |
| 816 | blr |
| 817 | #endif /* CONFIG_ALTIVEC */ |
| 818 | |
| 819 | /* |
| 820 | * This code is jumped to from the startup code to copy |
| 821 | * the kernel image to physical address 0. |
| 822 | */ |
| 823 | relocate_kernel: |
| 824 | addis r9,r26,klimit@ha /* fetch klimit */ |
| 825 | lwz r25,klimit@l(r9) |
| 826 | addis r25,r25,-KERNELBASE@h |
| 827 | li r3,0 /* Destination base address */ |
| 828 | li r6,0 /* Destination offset */ |
| 829 | li r5,0x4000 /* # bytes of memory to copy */ |
| 830 | bl copy_and_flush /* copy the first 0x4000 bytes */ |
| 831 | addi r0,r3,4f@l /* jump to the address of 4f */ |
| 832 | mtctr r0 /* in copy and do the rest. */ |
| 833 | bctr /* jump to the copy */ |
| 834 | 4: mr r5,r25 |
| 835 | bl copy_and_flush /* copy the rest */ |
| 836 | b turn_on_mmu |
| 837 | |
| 838 | /* |
| 839 | * Copy routine used to copy the kernel to start at physical address 0 |
| 840 | * and flush and invalidate the caches as needed. |
| 841 | * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset |
| 842 | * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. |
| 843 | */ |
Paul Mackerras | 77f543c | 2005-10-18 14:19:41 +1000 | [diff] [blame] | 844 | _GLOBAL(copy_and_flush) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 845 | addi r5,r5,-4 |
| 846 | addi r6,r6,-4 |
Stephen Rothwell | 7dffb72 | 2005-10-17 11:50:32 +1000 | [diff] [blame] | 847 | 4: li r0,L1_CACHE_BYTES/4 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 848 | mtctr r0 |
| 849 | 3: addi r6,r6,4 /* copy a cache line */ |
| 850 | lwzx r0,r6,r4 |
| 851 | stwx r0,r6,r3 |
| 852 | bdnz 3b |
| 853 | dcbst r6,r3 /* write it to memory */ |
| 854 | sync |
| 855 | icbi r6,r3 /* flush the icache line */ |
| 856 | cmplw 0,r6,r5 |
| 857 | blt 4b |
| 858 | sync /* additional sync needed on g4 */ |
| 859 | isync |
| 860 | addi r5,r5,4 |
| 861 | addi r6,r6,4 |
| 862 | blr |
| 863 | |
| 864 | #ifdef CONFIG_APUS |
| 865 | /* |
| 866 | * On APUS the physical base address of the kernel is not known at compile |
| 867 | * time, which means the __pa/__va constants used are incorrect. In the |
| 868 | * __init section is recorded the virtual addresses of instructions using |
| 869 | * these constants, so all that has to be done is fix these before |
| 870 | * continuing the kernel boot. |
| 871 | * |
| 872 | * r4 = The physical address of the kernel base. |
| 873 | */ |
| 874 | fix_mem_constants: |
| 875 | mr r10,r4 |
| 876 | addis r10,r10,-KERNELBASE@h /* virt_to_phys constant */ |
| 877 | neg r11,r10 /* phys_to_virt constant */ |
| 878 | |
| 879 | lis r12,__vtop_table_begin@h |
| 880 | ori r12,r12,__vtop_table_begin@l |
| 881 | add r12,r12,r10 /* table begin phys address */ |
| 882 | lis r13,__vtop_table_end@h |
| 883 | ori r13,r13,__vtop_table_end@l |
| 884 | add r13,r13,r10 /* table end phys address */ |
| 885 | subi r12,r12,4 |
| 886 | subi r13,r13,4 |
| 887 | 1: lwzu r14,4(r12) /* virt address of instruction */ |
| 888 | add r14,r14,r10 /* phys address of instruction */ |
| 889 | lwz r15,0(r14) /* instruction, now insert top */ |
| 890 | rlwimi r15,r10,16,16,31 /* half of vp const in low half */ |
| 891 | stw r15,0(r14) /* of instruction and restore. */ |
| 892 | dcbst r0,r14 /* write it to memory */ |
| 893 | sync |
| 894 | icbi r0,r14 /* flush the icache line */ |
| 895 | cmpw r12,r13 |
| 896 | bne 1b |
| 897 | sync /* additional sync needed on g4 */ |
| 898 | isync |
| 899 | |
| 900 | /* |
| 901 | * Map the memory where the exception handlers will |
| 902 | * be copied to when hash constants have been patched. |
| 903 | */ |
| 904 | #ifdef CONFIG_APUS_FAST_EXCEPT |
| 905 | lis r8,0xfff0 |
| 906 | #else |
| 907 | lis r8,0 |
| 908 | #endif |
| 909 | ori r8,r8,0x2 /* 128KB, supervisor */ |
| 910 | mtspr SPRN_DBAT3U,r8 |
| 911 | mtspr SPRN_DBAT3L,r8 |
| 912 | |
| 913 | lis r12,__ptov_table_begin@h |
| 914 | ori r12,r12,__ptov_table_begin@l |
| 915 | add r12,r12,r10 /* table begin phys address */ |
| 916 | lis r13,__ptov_table_end@h |
| 917 | ori r13,r13,__ptov_table_end@l |
| 918 | add r13,r13,r10 /* table end phys address */ |
| 919 | subi r12,r12,4 |
| 920 | subi r13,r13,4 |
| 921 | 1: lwzu r14,4(r12) /* virt address of instruction */ |
| 922 | add r14,r14,r10 /* phys address of instruction */ |
| 923 | lwz r15,0(r14) /* instruction, now insert top */ |
| 924 | rlwimi r15,r11,16,16,31 /* half of pv const in low half*/ |
| 925 | stw r15,0(r14) /* of instruction and restore. */ |
| 926 | dcbst r0,r14 /* write it to memory */ |
| 927 | sync |
| 928 | icbi r0,r14 /* flush the icache line */ |
| 929 | cmpw r12,r13 |
| 930 | bne 1b |
| 931 | |
| 932 | sync /* additional sync needed on g4 */ |
| 933 | isync /* No speculative loading until now */ |
| 934 | blr |
| 935 | |
| 936 | /*********************************************************************** |
| 937 | * Please note that on APUS the exception handlers are located at the |
| 938 | * physical address 0xfff0000. For this reason, the exception handlers |
| 939 | * cannot use relative branches to access the code below. |
| 940 | ***********************************************************************/ |
| 941 | #endif /* CONFIG_APUS */ |
| 942 | |
| 943 | #ifdef CONFIG_SMP |
| 944 | #ifdef CONFIG_GEMINI |
| 945 | .globl __secondary_start_gemini |
| 946 | __secondary_start_gemini: |
| 947 | mfspr r4,SPRN_HID0 |
| 948 | ori r4,r4,HID0_ICFI |
| 949 | li r3,0 |
| 950 | ori r3,r3,HID0_ICE |
| 951 | andc r4,r4,r3 |
| 952 | mtspr SPRN_HID0,r4 |
| 953 | sync |
| 954 | b __secondary_start |
| 955 | #endif /* CONFIG_GEMINI */ |
| 956 | |
| 957 | .globl __secondary_start_pmac_0 |
| 958 | __secondary_start_pmac_0: |
| 959 | /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ |
| 960 | li r24,0 |
| 961 | b 1f |
| 962 | li r24,1 |
| 963 | b 1f |
| 964 | li r24,2 |
| 965 | b 1f |
| 966 | li r24,3 |
| 967 | 1: |
| 968 | /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0 |
| 969 | set to map the 0xf0000000 - 0xffffffff region */ |
| 970 | mfmsr r0 |
| 971 | rlwinm r0,r0,0,28,26 /* clear DR (0x10) */ |
| 972 | SYNC |
| 973 | mtmsr r0 |
| 974 | isync |
| 975 | |
| 976 | .globl __secondary_start |
| 977 | __secondary_start: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 978 | /* Copy some CPU settings from CPU 0 */ |
| 979 | bl __restore_cpu_setup |
| 980 | |
| 981 | lis r3,-KERNELBASE@h |
| 982 | mr r4,r24 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 983 | bl call_setup_cpu /* Call setup_cpu for this CPU */ |
| 984 | #ifdef CONFIG_6xx |
| 985 | lis r3,-KERNELBASE@h |
| 986 | bl init_idle_6xx |
| 987 | #endif /* CONFIG_6xx */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 988 | |
| 989 | /* get current_thread_info and current */ |
| 990 | lis r1,secondary_ti@ha |
| 991 | tophys(r1,r1) |
| 992 | lwz r1,secondary_ti@l(r1) |
| 993 | tophys(r2,r1) |
| 994 | lwz r2,TI_TASK(r2) |
| 995 | |
| 996 | /* stack */ |
| 997 | addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD |
| 998 | li r0,0 |
| 999 | tophys(r3,r1) |
| 1000 | stw r0,0(r3) |
| 1001 | |
| 1002 | /* load up the MMU */ |
| 1003 | bl load_up_mmu |
| 1004 | |
| 1005 | /* ptr to phys current thread */ |
| 1006 | tophys(r4,r2) |
| 1007 | addi r4,r4,THREAD /* phys address of our thread_struct */ |
| 1008 | CLR_TOP32(r4) |
| 1009 | mtspr SPRN_SPRG3,r4 |
| 1010 | li r3,0 |
| 1011 | mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */ |
| 1012 | |
| 1013 | /* enable MMU and jump to start_secondary */ |
| 1014 | li r4,MSR_KERNEL |
| 1015 | FIX_SRR1(r4,r5) |
| 1016 | lis r3,start_secondary@h |
| 1017 | ori r3,r3,start_secondary@l |
| 1018 | mtspr SPRN_SRR0,r3 |
| 1019 | mtspr SPRN_SRR1,r4 |
| 1020 | SYNC |
| 1021 | RFI |
| 1022 | #endif /* CONFIG_SMP */ |
| 1023 | |
| 1024 | /* |
| 1025 | * Those generic dummy functions are kept for CPUs not |
| 1026 | * included in CONFIG_6xx |
| 1027 | */ |
Paul Mackerras | 187a006 | 2005-10-06 12:49:05 +1000 | [diff] [blame] | 1028 | #if !defined(CONFIG_6xx) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1029 | _GLOBAL(__save_cpu_setup) |
| 1030 | blr |
| 1031 | _GLOBAL(__restore_cpu_setup) |
| 1032 | blr |
Paul Mackerras | 187a006 | 2005-10-06 12:49:05 +1000 | [diff] [blame] | 1033 | #endif /* !defined(CONFIG_6xx) */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1034 | |
| 1035 | |
| 1036 | /* |
| 1037 | * Load stuff into the MMU. Intended to be called with |
| 1038 | * IR=0 and DR=0. |
| 1039 | */ |
| 1040 | load_up_mmu: |
| 1041 | sync /* Force all PTE updates to finish */ |
| 1042 | isync |
| 1043 | tlbia /* Clear all TLB entries */ |
| 1044 | sync /* wait for tlbia/tlbie to finish */ |
| 1045 | TLBSYNC /* ... on all CPUs */ |
| 1046 | /* Load the SDR1 register (hash table base & size) */ |
| 1047 | lis r6,_SDR1@ha |
| 1048 | tophys(r6,r6) |
| 1049 | lwz r6,_SDR1@l(r6) |
| 1050 | mtspr SPRN_SDR1,r6 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1051 | li r0,16 /* load up segment register values */ |
| 1052 | mtctr r0 /* for context 0 */ |
| 1053 | lis r3,0x2000 /* Ku = 1, VSID = 0 */ |
| 1054 | li r4,0 |
| 1055 | 3: mtsrin r3,r4 |
| 1056 | addi r3,r3,0x111 /* increment VSID */ |
| 1057 | addis r4,r4,0x1000 /* address of next segment */ |
| 1058 | bdnz 3b |
Paul Mackerras | 187a006 | 2005-10-06 12:49:05 +1000 | [diff] [blame] | 1059 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1060 | /* Load the BAT registers with the values set up by MMU_init. |
| 1061 | MMU_init takes care of whether we're on a 601 or not. */ |
| 1062 | mfpvr r3 |
| 1063 | srwi r3,r3,16 |
| 1064 | cmpwi r3,1 |
| 1065 | lis r3,BATS@ha |
| 1066 | addi r3,r3,BATS@l |
| 1067 | tophys(r3,r3) |
| 1068 | LOAD_BAT(0,r3,r4,r5) |
| 1069 | LOAD_BAT(1,r3,r4,r5) |
| 1070 | LOAD_BAT(2,r3,r4,r5) |
| 1071 | LOAD_BAT(3,r3,r4,r5) |
Paul Mackerras | 187a006 | 2005-10-06 12:49:05 +1000 | [diff] [blame] | 1072 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1073 | blr |
| 1074 | |
| 1075 | /* |
| 1076 | * This is where the main kernel code starts. |
| 1077 | */ |
| 1078 | start_here: |
| 1079 | /* ptr to current */ |
| 1080 | lis r2,init_task@h |
| 1081 | ori r2,r2,init_task@l |
| 1082 | /* Set up for using our exception vectors */ |
| 1083 | /* ptr to phys current thread */ |
| 1084 | tophys(r4,r2) |
| 1085 | addi r4,r4,THREAD /* init task's THREAD */ |
| 1086 | CLR_TOP32(r4) |
| 1087 | mtspr SPRN_SPRG3,r4 |
| 1088 | li r3,0 |
| 1089 | mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */ |
| 1090 | |
| 1091 | /* stack */ |
| 1092 | lis r1,init_thread_union@ha |
| 1093 | addi r1,r1,init_thread_union@l |
| 1094 | li r0,0 |
| 1095 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) |
| 1096 | /* |
Paul Mackerras | 187a006 | 2005-10-06 12:49:05 +1000 | [diff] [blame] | 1097 | * Do early platform-specific initialization, |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1098 | * and set up the MMU. |
| 1099 | */ |
| 1100 | mr r3,r31 |
| 1101 | mr r4,r30 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1102 | bl machine_init |
| 1103 | bl MMU_init |
| 1104 | |
| 1105 | #ifdef CONFIG_APUS |
| 1106 | /* Copy exception code to exception vector base on APUS. */ |
| 1107 | lis r4,KERNELBASE@h |
| 1108 | #ifdef CONFIG_APUS_FAST_EXCEPT |
| 1109 | lis r3,0xfff0 /* Copy to 0xfff00000 */ |
| 1110 | #else |
| 1111 | lis r3,0 /* Copy to 0x00000000 */ |
| 1112 | #endif |
| 1113 | li r5,0x4000 /* # bytes of memory to copy */ |
| 1114 | li r6,0 |
| 1115 | bl copy_and_flush /* copy the first 0x4000 bytes */ |
| 1116 | #endif /* CONFIG_APUS */ |
| 1117 | |
| 1118 | /* |
| 1119 | * Go back to running unmapped so we can load up new values |
| 1120 | * for SDR1 (hash table pointer) and the segment registers |
| 1121 | * and change to using our exception vectors. |
| 1122 | */ |
| 1123 | lis r4,2f@h |
| 1124 | ori r4,r4,2f@l |
| 1125 | tophys(r4,r4) |
| 1126 | li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) |
| 1127 | FIX_SRR1(r3,r5) |
| 1128 | mtspr SPRN_SRR0,r4 |
| 1129 | mtspr SPRN_SRR1,r3 |
| 1130 | SYNC |
| 1131 | RFI |
| 1132 | /* Load up the kernel context */ |
| 1133 | 2: bl load_up_mmu |
| 1134 | |
| 1135 | #ifdef CONFIG_BDI_SWITCH |
| 1136 | /* Add helper information for the Abatron bdiGDB debugger. |
| 1137 | * We do this here because we know the mmu is disabled, and |
| 1138 | * will be enabled for real in just a few instructions. |
| 1139 | */ |
| 1140 | lis r5, abatron_pteptrs@h |
| 1141 | ori r5, r5, abatron_pteptrs@l |
| 1142 | stw r5, 0xf0(r0) /* This much match your Abatron config */ |
| 1143 | lis r6, swapper_pg_dir@h |
| 1144 | ori r6, r6, swapper_pg_dir@l |
| 1145 | tophys(r5, r5) |
| 1146 | stw r6, 0(r5) |
| 1147 | #endif /* CONFIG_BDI_SWITCH */ |
| 1148 | |
| 1149 | /* Now turn on the MMU for real! */ |
| 1150 | li r4,MSR_KERNEL |
| 1151 | FIX_SRR1(r4,r5) |
| 1152 | lis r3,start_kernel@h |
| 1153 | ori r3,r3,start_kernel@l |
| 1154 | mtspr SPRN_SRR0,r3 |
| 1155 | mtspr SPRN_SRR1,r4 |
| 1156 | SYNC |
| 1157 | RFI |
| 1158 | |
| 1159 | /* |
| 1160 | * Set up the segment registers for a new context. |
| 1161 | */ |
| 1162 | _GLOBAL(set_context) |
| 1163 | mulli r3,r3,897 /* multiply context by skew factor */ |
| 1164 | rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */ |
| 1165 | addis r3,r3,0x6000 /* Set Ks, Ku bits */ |
| 1166 | li r0,NUM_USER_SEGMENTS |
| 1167 | mtctr r0 |
| 1168 | |
| 1169 | #ifdef CONFIG_BDI_SWITCH |
| 1170 | /* Context switch the PTE pointer for the Abatron BDI2000. |
| 1171 | * The PGDIR is passed as second argument. |
| 1172 | */ |
| 1173 | lis r5, KERNELBASE@h |
| 1174 | lwz r5, 0xf0(r5) |
| 1175 | stw r4, 0x4(r5) |
| 1176 | #endif |
| 1177 | li r4,0 |
| 1178 | isync |
| 1179 | 3: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1180 | mtsrin r3,r4 |
| 1181 | addi r3,r3,0x111 /* next VSID */ |
| 1182 | rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */ |
| 1183 | addis r4,r4,0x1000 /* address of next segment */ |
| 1184 | bdnz 3b |
| 1185 | sync |
| 1186 | isync |
| 1187 | blr |
| 1188 | |
| 1189 | /* |
| 1190 | * An undocumented "feature" of 604e requires that the v bit |
| 1191 | * be cleared before changing BAT values. |
| 1192 | * |
| 1193 | * Also, newer IBM firmware does not clear bat3 and 4 so |
| 1194 | * this makes sure it's done. |
| 1195 | * -- Cort |
| 1196 | */ |
| 1197 | clear_bats: |
| 1198 | li r10,0 |
| 1199 | mfspr r9,SPRN_PVR |
| 1200 | rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ |
| 1201 | cmpwi r9, 1 |
| 1202 | beq 1f |
| 1203 | |
| 1204 | mtspr SPRN_DBAT0U,r10 |
| 1205 | mtspr SPRN_DBAT0L,r10 |
| 1206 | mtspr SPRN_DBAT1U,r10 |
| 1207 | mtspr SPRN_DBAT1L,r10 |
| 1208 | mtspr SPRN_DBAT2U,r10 |
| 1209 | mtspr SPRN_DBAT2L,r10 |
| 1210 | mtspr SPRN_DBAT3U,r10 |
| 1211 | mtspr SPRN_DBAT3L,r10 |
| 1212 | 1: |
| 1213 | mtspr SPRN_IBAT0U,r10 |
| 1214 | mtspr SPRN_IBAT0L,r10 |
| 1215 | mtspr SPRN_IBAT1U,r10 |
| 1216 | mtspr SPRN_IBAT1L,r10 |
| 1217 | mtspr SPRN_IBAT2U,r10 |
| 1218 | mtspr SPRN_IBAT2L,r10 |
| 1219 | mtspr SPRN_IBAT3U,r10 |
| 1220 | mtspr SPRN_IBAT3L,r10 |
| 1221 | BEGIN_FTR_SECTION |
| 1222 | /* Here's a tweak: at this point, CPU setup have |
| 1223 | * not been called yet, so HIGH_BAT_EN may not be |
| 1224 | * set in HID0 for the 745x processors. However, it |
| 1225 | * seems that doesn't affect our ability to actually |
| 1226 | * write to these SPRs. |
| 1227 | */ |
| 1228 | mtspr SPRN_DBAT4U,r10 |
| 1229 | mtspr SPRN_DBAT4L,r10 |
| 1230 | mtspr SPRN_DBAT5U,r10 |
| 1231 | mtspr SPRN_DBAT5L,r10 |
| 1232 | mtspr SPRN_DBAT6U,r10 |
| 1233 | mtspr SPRN_DBAT6L,r10 |
| 1234 | mtspr SPRN_DBAT7U,r10 |
| 1235 | mtspr SPRN_DBAT7L,r10 |
| 1236 | mtspr SPRN_IBAT4U,r10 |
| 1237 | mtspr SPRN_IBAT4L,r10 |
| 1238 | mtspr SPRN_IBAT5U,r10 |
| 1239 | mtspr SPRN_IBAT5L,r10 |
| 1240 | mtspr SPRN_IBAT6U,r10 |
| 1241 | mtspr SPRN_IBAT6L,r10 |
| 1242 | mtspr SPRN_IBAT7U,r10 |
| 1243 | mtspr SPRN_IBAT7L,r10 |
| 1244 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS) |
| 1245 | blr |
| 1246 | |
| 1247 | flush_tlbs: |
| 1248 | lis r10, 0x40 |
| 1249 | 1: addic. r10, r10, -0x1000 |
| 1250 | tlbie r10 |
| 1251 | blt 1b |
| 1252 | sync |
| 1253 | blr |
| 1254 | |
| 1255 | mmu_off: |
| 1256 | addi r4, r3, __after_mmu_off - _start |
| 1257 | mfmsr r3 |
| 1258 | andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */ |
| 1259 | beqlr |
| 1260 | andc r3,r3,r0 |
| 1261 | mtspr SPRN_SRR0,r4 |
| 1262 | mtspr SPRN_SRR1,r3 |
| 1263 | sync |
| 1264 | RFI |
| 1265 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1266 | /* |
| 1267 | * Use the first pair of BAT registers to map the 1st 16MB |
| 1268 | * of RAM to KERNELBASE. From this point on we can't safely |
| 1269 | * call OF any more. |
| 1270 | */ |
| 1271 | initial_bats: |
| 1272 | lis r11,KERNELBASE@h |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1273 | mfspr r9,SPRN_PVR |
| 1274 | rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ |
| 1275 | cmpwi 0,r9,1 |
| 1276 | bne 4f |
| 1277 | ori r11,r11,4 /* set up BAT registers for 601 */ |
| 1278 | li r8,0x7f /* valid, block length = 8MB */ |
| 1279 | oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */ |
| 1280 | oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */ |
| 1281 | mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */ |
| 1282 | mtspr SPRN_IBAT0L,r8 /* lower BAT register */ |
| 1283 | mtspr SPRN_IBAT1U,r9 |
| 1284 | mtspr SPRN_IBAT1L,r10 |
| 1285 | isync |
| 1286 | blr |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1287 | |
| 1288 | 4: tophys(r8,r11) |
| 1289 | #ifdef CONFIG_SMP |
| 1290 | ori r8,r8,0x12 /* R/W access, M=1 */ |
| 1291 | #else |
| 1292 | ori r8,r8,2 /* R/W access */ |
| 1293 | #endif /* CONFIG_SMP */ |
| 1294 | #ifdef CONFIG_APUS |
| 1295 | ori r11,r11,BL_8M<<2|0x2 /* set up 8MB BAT registers for 604 */ |
| 1296 | #else |
| 1297 | ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */ |
| 1298 | #endif /* CONFIG_APUS */ |
| 1299 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1300 | mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */ |
| 1301 | mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */ |
| 1302 | mtspr SPRN_IBAT0L,r8 |
| 1303 | mtspr SPRN_IBAT0U,r11 |
| 1304 | isync |
| 1305 | blr |
| 1306 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1307 | |
| 1308 | #ifdef CONFIG_8260 |
| 1309 | /* Jump into the system reset for the rom. |
| 1310 | * We first disable the MMU, and then jump to the ROM reset address. |
| 1311 | * |
| 1312 | * r3 is the board info structure, r4 is the location for starting. |
| 1313 | * I use this for building a small kernel that can load other kernels, |
| 1314 | * rather than trying to write or rely on a rom monitor that can tftp load. |
| 1315 | */ |
| 1316 | .globl m8260_gorom |
| 1317 | m8260_gorom: |
| 1318 | mfmsr r0 |
| 1319 | rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */ |
| 1320 | sync |
| 1321 | mtmsr r0 |
| 1322 | sync |
| 1323 | mfspr r11, SPRN_HID0 |
| 1324 | lis r10, 0 |
| 1325 | ori r10,r10,HID0_ICE|HID0_DCE |
| 1326 | andc r11, r11, r10 |
| 1327 | mtspr SPRN_HID0, r11 |
| 1328 | isync |
| 1329 | li r5, MSR_ME|MSR_RI |
| 1330 | lis r6,2f@h |
| 1331 | addis r6,r6,-KERNELBASE@h |
| 1332 | ori r6,r6,2f@l |
| 1333 | mtspr SPRN_SRR0,r6 |
| 1334 | mtspr SPRN_SRR1,r5 |
| 1335 | isync |
| 1336 | sync |
| 1337 | rfi |
| 1338 | 2: |
| 1339 | mtlr r4 |
| 1340 | blr |
| 1341 | #endif |
| 1342 | |
| 1343 | |
| 1344 | /* |
| 1345 | * We put a few things here that have to be page-aligned. |
| 1346 | * This stuff goes at the beginning of the data segment, |
| 1347 | * which is page-aligned. |
| 1348 | */ |
| 1349 | .data |
| 1350 | .globl sdata |
| 1351 | sdata: |
| 1352 | .globl empty_zero_page |
| 1353 | empty_zero_page: |
| 1354 | .space 4096 |
| 1355 | |
| 1356 | .globl swapper_pg_dir |
| 1357 | swapper_pg_dir: |
| 1358 | .space 4096 |
| 1359 | |
| 1360 | /* |
| 1361 | * This space gets a copy of optional info passed to us by the bootstrap |
| 1362 | * Used to pass parameters into the kernel like root=/dev/sda1, etc. |
| 1363 | */ |
| 1364 | .globl cmd_line |
| 1365 | cmd_line: |
| 1366 | .space 512 |
| 1367 | |
| 1368 | .globl intercept_table |
| 1369 | intercept_table: |
| 1370 | .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700 |
| 1371 | .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0 |
| 1372 | .long 0, 0, 0, i0x1300, 0, 0, 0, 0 |
| 1373 | .long 0, 0, 0, 0, 0, 0, 0, 0 |
| 1374 | .long 0, 0, 0, 0, 0, 0, 0, 0 |
| 1375 | .long 0, 0, 0, 0, 0, 0, 0, 0 |
| 1376 | |
| 1377 | /* Room for two PTE pointers, usually the kernel and current user pointers |
| 1378 | * to their respective root page table. |
| 1379 | */ |
| 1380 | abatron_pteptrs: |
| 1381 | .space 8 |