| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-mv78xx0/include/mach/bridge-regs.h |
| 3 | * |
| 4 | * This file is licensed under the terms of the GNU General Public |
| 5 | * License version 2. This program is licensed "as is" without any |
| 6 | * warranty of any kind, whether express or implied. |
| 7 | */ |
| 8 | |
| 9 | #ifndef __ASM_ARCH_BRIDGE_REGS_H |
| 10 | #define __ASM_ARCH_BRIDGE_REGS_H |
| 11 | |
| 12 | #include <mach/mv78xx0.h> |
| 13 | |
| Thomas Petazzoni | 5ae9f5d | 2012-09-11 14:27:16 +0200 | [diff] [blame] | 14 | #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 15 | #define L2_WRITETHROUGH 0x00020000 |
| 16 | |
| Thomas Petazzoni | 5ae9f5d | 2012-09-11 14:27:16 +0200 | [diff] [blame] | 17 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) |
| Ezequiel Garcia | 868eb61 | 2014-02-10 20:00:25 -0300 | [diff] [blame] | 18 | #define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 19 | #define SOFT_RESET_OUT_EN 0x00000004 |
| 20 | |
| Thomas Petazzoni | 5ae9f5d | 2012-09-11 14:27:16 +0200 | [diff] [blame] | 21 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 22 | #define SOFT_RESET 0x00000001 |
| 23 | |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 24 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) |
| 25 | |
| Thomas Petazzoni | 5ae9f5d | 2012-09-11 14:27:16 +0200 | [diff] [blame] | 26 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 27 | #define IRQ_CAUSE_ERR_OFF 0x0000 |
| 28 | #define IRQ_CAUSE_LOW_OFF 0x0004 |
| 29 | #define IRQ_CAUSE_HIGH_OFF 0x0008 |
| 30 | #define IRQ_MASK_ERR_OFF 0x000c |
| 31 | #define IRQ_MASK_LOW_OFF 0x0010 |
| 32 | #define IRQ_MASK_HIGH_OFF 0x0014 |
| 33 | |
| Thomas Petazzoni | 5ae9f5d | 2012-09-11 14:27:16 +0200 | [diff] [blame] | 34 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) |
| 35 | #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 36 | |
| 37 | #endif |