blob: 25d9a11eb61750ade3ba77abd7771068ebe668ee [file] [log] [blame]
Russell Kingd111e8f2006-09-27 15:27:33 +01001/*
2 * linux/arch/arm/mm/mmu.c
3 *
4 * Copyright (C) 1995-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
Russell Kingae8f1542006-09-27 15:38:34 +010010#include <linux/module.h>
Russell Kingd111e8f2006-09-27 15:27:33 +010011#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/bootmem.h>
15#include <linux/mman.h>
16#include <linux/nodemask.h>
17
18#include <asm/mach-types.h>
19#include <asm/setup.h>
20#include <asm/sizes.h>
21#include <asm/tlb.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25
26#include "mm.h"
27
28DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
29
Russell King6ae5a6e2006-09-30 10:50:05 +010030extern void _stext, _etext, __data_start, _end;
Russell Kingd111e8f2006-09-27 15:27:33 +010031extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
32
33/*
34 * empty_zero_page is a special page that is used for
35 * zero-initialized data and COW.
36 */
37struct page *empty_zero_page;
Aneesh Kumar K.V3653f3a2008-04-29 08:11:12 -040038EXPORT_SYMBOL(empty_zero_page);
Russell Kingd111e8f2006-09-27 15:27:33 +010039
40/*
41 * The pmd table for the upper-most set of pages.
42 */
43pmd_t *top_pmd;
44
Russell Kingae8f1542006-09-27 15:38:34 +010045#define CPOLICY_UNCACHED 0
46#define CPOLICY_BUFFERED 1
47#define CPOLICY_WRITETHROUGH 2
48#define CPOLICY_WRITEBACK 3
49#define CPOLICY_WRITEALLOC 4
50
51static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
52static unsigned int ecc_mask __initdata = 0;
Imre_Deak44b18692007-02-11 13:45:13 +010053pgprot_t pgprot_user;
Russell Kingae8f1542006-09-27 15:38:34 +010054pgprot_t pgprot_kernel;
55
Imre_Deak44b18692007-02-11 13:45:13 +010056EXPORT_SYMBOL(pgprot_user);
Russell Kingae8f1542006-09-27 15:38:34 +010057EXPORT_SYMBOL(pgprot_kernel);
58
59struct cachepolicy {
60 const char policy[16];
61 unsigned int cr_mask;
62 unsigned int pmd;
63 unsigned int pte;
64};
65
66static struct cachepolicy cache_policies[] __initdata = {
67 {
68 .policy = "uncached",
69 .cr_mask = CR_W|CR_C,
70 .pmd = PMD_SECT_UNCACHED,
71 .pte = 0,
72 }, {
73 .policy = "buffered",
74 .cr_mask = CR_C,
75 .pmd = PMD_SECT_BUFFERED,
76 .pte = PTE_BUFFERABLE,
77 }, {
78 .policy = "writethrough",
79 .cr_mask = 0,
80 .pmd = PMD_SECT_WT,
81 .pte = PTE_CACHEABLE,
82 }, {
83 .policy = "writeback",
84 .cr_mask = 0,
85 .pmd = PMD_SECT_WB,
86 .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
87 }, {
88 .policy = "writealloc",
89 .cr_mask = 0,
90 .pmd = PMD_SECT_WBWA,
91 .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
92 }
93};
94
95/*
Simon Arlott6cbdc8c2007-05-11 20:40:30 +010096 * These are useful for identifying cache coherency
Russell Kingae8f1542006-09-27 15:38:34 +010097 * problems by allowing the cache or the cache and
98 * writebuffer to be turned off. (Note: the write
99 * buffer should not be on and the cache off).
100 */
101static void __init early_cachepolicy(char **p)
102{
103 int i;
104
105 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
106 int len = strlen(cache_policies[i].policy);
107
108 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
109 cachepolicy = i;
110 cr_alignment &= ~cache_policies[i].cr_mask;
111 cr_no_alignment &= ~cache_policies[i].cr_mask;
112 *p += len;
113 break;
114 }
115 }
116 if (i == ARRAY_SIZE(cache_policies))
117 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
Catalin Marinas11179d82007-07-20 11:42:24 +0100118 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
119 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
120 cachepolicy = CPOLICY_WRITEBACK;
121 }
Russell Kingae8f1542006-09-27 15:38:34 +0100122 flush_cache_all();
123 set_cr(cr_alignment);
124}
125__early_param("cachepolicy=", early_cachepolicy);
126
127static void __init early_nocache(char **__unused)
128{
129 char *p = "buffered";
130 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
131 early_cachepolicy(&p);
132}
133__early_param("nocache", early_nocache);
134
135static void __init early_nowrite(char **__unused)
136{
137 char *p = "uncached";
138 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
139 early_cachepolicy(&p);
140}
141__early_param("nowb", early_nowrite);
142
143static void __init early_ecc(char **p)
144{
145 if (memcmp(*p, "on", 2) == 0) {
146 ecc_mask = PMD_PROTECTION;
147 *p += 2;
148 } else if (memcmp(*p, "off", 3) == 0) {
149 ecc_mask = 0;
150 *p += 3;
151 }
152}
153__early_param("ecc=", early_ecc);
154
155static int __init noalign_setup(char *__unused)
156{
157 cr_alignment &= ~CR_A;
158 cr_no_alignment &= ~CR_A;
159 set_cr(cr_alignment);
160 return 1;
161}
162__setup("noalign", noalign_setup);
163
Russell King255d1f82006-12-18 00:12:47 +0000164#ifndef CONFIG_SMP
165void adjust_cr(unsigned long mask, unsigned long set)
166{
167 unsigned long flags;
168
169 mask &= ~CR_A;
170
171 set &= mask;
172
173 local_irq_save(flags);
174
175 cr_no_alignment = (cr_no_alignment & ~mask) | set;
176 cr_alignment = (cr_alignment & ~mask) | set;
177
178 set_cr((get_cr() & ~mask) | set);
179
180 local_irq_restore(flags);
181}
182#endif
183
Russell King0af92be2007-05-05 20:28:16 +0100184#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
185#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_XN|PMD_SECT_AP_WRITE
186
Russell Kingb29e9f52007-04-21 10:47:29 +0100187static struct mem_type mem_types[] = {
Russell King0af92be2007-05-05 20:28:16 +0100188 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
189 .prot_pte = PROT_PTE_DEVICE,
190 .prot_l1 = PMD_TYPE_TABLE,
191 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_UNCACHED,
192 .domain = DOMAIN_IO,
193 },
194 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
195 .prot_pte = PROT_PTE_DEVICE,
196 .prot_pte_ext = PTE_EXT_TEX(2),
197 .prot_l1 = PMD_TYPE_TABLE,
198 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2),
199 .domain = DOMAIN_IO,
200 },
201 [MT_DEVICE_CACHED] = { /* ioremap_cached */
202 .prot_pte = PROT_PTE_DEVICE | L_PTE_CACHEABLE | L_PTE_BUFFERABLE,
203 .prot_l1 = PMD_TYPE_TABLE,
204 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
205 .domain = DOMAIN_IO,
206 },
207 [MT_DEVICE_IXP2000] = { /* IXP2400 requires XCB=101 for on-chip I/O */
208 .prot_pte = PROT_PTE_DEVICE,
209 .prot_l1 = PMD_TYPE_TABLE,
210 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE |
211 PMD_SECT_TEX(1),
212 .domain = DOMAIN_IO,
Russell Kingae8f1542006-09-27 15:38:34 +0100213 },
214 [MT_CACHECLEAN] = {
Russell King9ef79632007-05-05 20:03:35 +0100215 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
Russell Kingae8f1542006-09-27 15:38:34 +0100216 .domain = DOMAIN_KERNEL,
217 },
218 [MT_MINICLEAN] = {
Russell King9ef79632007-05-05 20:03:35 +0100219 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
Russell Kingae8f1542006-09-27 15:38:34 +0100220 .domain = DOMAIN_KERNEL,
221 },
222 [MT_LOW_VECTORS] = {
223 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
224 L_PTE_EXEC,
225 .prot_l1 = PMD_TYPE_TABLE,
226 .domain = DOMAIN_USER,
227 },
228 [MT_HIGH_VECTORS] = {
229 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
230 L_PTE_USER | L_PTE_EXEC,
231 .prot_l1 = PMD_TYPE_TABLE,
232 .domain = DOMAIN_USER,
233 },
234 [MT_MEMORY] = {
Russell King9ef79632007-05-05 20:03:35 +0100235 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
Russell Kingae8f1542006-09-27 15:38:34 +0100236 .domain = DOMAIN_KERNEL,
237 },
238 [MT_ROM] = {
Russell King9ef79632007-05-05 20:03:35 +0100239 .prot_sect = PMD_TYPE_SECT,
Russell Kingae8f1542006-09-27 15:38:34 +0100240 .domain = DOMAIN_KERNEL,
241 },
Russell Kingae8f1542006-09-27 15:38:34 +0100242};
243
Russell Kingb29e9f52007-04-21 10:47:29 +0100244const struct mem_type *get_mem_type(unsigned int type)
245{
246 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
247}
248
Russell Kingae8f1542006-09-27 15:38:34 +0100249/*
250 * Adjust the PMD section entries according to the CPU in use.
251 */
252static void __init build_mem_type_table(void)
253{
254 struct cachepolicy *cp;
255 unsigned int cr = get_cr();
256 unsigned int user_pgprot, kern_pgprot;
257 int cpu_arch = cpu_architecture();
258 int i;
259
Catalin Marinas11179d82007-07-20 11:42:24 +0100260 if (cpu_arch < CPU_ARCH_ARMv6) {
Russell Kingae8f1542006-09-27 15:38:34 +0100261#if defined(CONFIG_CPU_DCACHE_DISABLE)
Catalin Marinas11179d82007-07-20 11:42:24 +0100262 if (cachepolicy > CPOLICY_BUFFERED)
263 cachepolicy = CPOLICY_BUFFERED;
Russell Kingae8f1542006-09-27 15:38:34 +0100264#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
Catalin Marinas11179d82007-07-20 11:42:24 +0100265 if (cachepolicy > CPOLICY_WRITETHROUGH)
266 cachepolicy = CPOLICY_WRITETHROUGH;
Russell Kingae8f1542006-09-27 15:38:34 +0100267#endif
Catalin Marinas11179d82007-07-20 11:42:24 +0100268 }
Russell Kingae8f1542006-09-27 15:38:34 +0100269 if (cpu_arch < CPU_ARCH_ARMv5) {
270 if (cachepolicy >= CPOLICY_WRITEALLOC)
271 cachepolicy = CPOLICY_WRITEBACK;
272 ecc_mask = 0;
273 }
274
275 /*
Russell King9ef79632007-05-05 20:03:35 +0100276 * ARMv5 and lower, bit 4 must be set for page tables.
277 * (was: cache "update-able on write" bit on ARM610)
278 * However, Xscale cores require this bit to be cleared.
Russell Kingae8f1542006-09-27 15:38:34 +0100279 */
Russell King9ef79632007-05-05 20:03:35 +0100280 if (cpu_is_xscale()) {
281 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
Russell Kingae8f1542006-09-27 15:38:34 +0100282 mem_types[i].prot_sect &= ~PMD_BIT4;
Russell King9ef79632007-05-05 20:03:35 +0100283 mem_types[i].prot_l1 &= ~PMD_BIT4;
284 }
285 } else if (cpu_arch < CPU_ARCH_ARMv6) {
286 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
Russell Kingae8f1542006-09-27 15:38:34 +0100287 if (mem_types[i].prot_l1)
288 mem_types[i].prot_l1 |= PMD_BIT4;
Russell King9ef79632007-05-05 20:03:35 +0100289 if (mem_types[i].prot_sect)
290 mem_types[i].prot_sect |= PMD_BIT4;
291 }
292 }
Russell Kingae8f1542006-09-27 15:38:34 +0100293
294 cp = &cache_policies[cachepolicy];
295 kern_pgprot = user_pgprot = cp->pte;
296
297 /*
298 * Enable CPU-specific coherency if supported.
299 * (Only available on XSC3 at the moment.)
300 */
301 if (arch_is_coherent()) {
302 if (cpu_is_xsc3()) {
303 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
Lennert Buytenhek0e5fdca2006-12-02 00:03:47 +0100304 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
Russell Kingae8f1542006-09-27 15:38:34 +0100305 }
306 }
307
308 /*
309 * ARMv6 and above have extended page tables.
310 */
311 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
312 /*
Russell Kingae8f1542006-09-27 15:38:34 +0100313 * Mark cache clean areas and XIP ROM read only
314 * from SVC mode and no access from userspace.
315 */
316 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
317 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
318 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
319
320 /*
321 * Mark the device area as "shared device"
322 */
323 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
324 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
325
Russell Kingae8f1542006-09-27 15:38:34 +0100326#ifdef CONFIG_SMP
327 /*
328 * Mark memory with the "shared" attribute for SMP systems
329 */
330 user_pgprot |= L_PTE_SHARED;
331 kern_pgprot |= L_PTE_SHARED;
332 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
333#endif
334 }
335
336 for (i = 0; i < 16; i++) {
337 unsigned long v = pgprot_val(protection_map[i]);
338 v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot;
339 protection_map[i] = __pgprot(v);
340 }
341
342 mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot;
343 mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot;
344
345 if (cpu_arch >= CPU_ARCH_ARMv5) {
346#ifndef CONFIG_SMP
347 /*
348 * Only use write-through for non-SMP systems
349 */
350 mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
351 mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
352#endif
353 } else {
354 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
355 }
356
Imre_Deak44b18692007-02-11 13:45:13 +0100357 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
Russell Kingae8f1542006-09-27 15:38:34 +0100358 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
359 L_PTE_DIRTY | L_PTE_WRITE |
360 L_PTE_EXEC | kern_pgprot);
361
362 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
363 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
364 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
365 mem_types[MT_ROM].prot_sect |= cp->pmd;
366
367 switch (cp->pmd) {
368 case PMD_SECT_WT:
369 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
370 break;
371 case PMD_SECT_WB:
372 case PMD_SECT_WBWA:
373 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
374 break;
375 }
376 printk("Memory policy: ECC %sabled, Data cache %s\n",
377 ecc_mask ? "en" : "dis", cp->policy);
Russell King2497f0a2007-04-21 09:59:44 +0100378
379 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
380 struct mem_type *t = &mem_types[i];
381 if (t->prot_l1)
382 t->prot_l1 |= PMD_DOMAIN(t->domain);
383 if (t->prot_sect)
384 t->prot_sect |= PMD_DOMAIN(t->domain);
385 }
Russell Kingae8f1542006-09-27 15:38:34 +0100386}
387
388#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
389
Russell King24e6c692007-04-21 10:21:28 +0100390static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
391 unsigned long end, unsigned long pfn,
392 const struct mem_type *type)
Russell Kingae8f1542006-09-27 15:38:34 +0100393{
Russell King24e6c692007-04-21 10:21:28 +0100394 pte_t *pte;
Russell Kingae8f1542006-09-27 15:38:34 +0100395
Russell King24e6c692007-04-21 10:21:28 +0100396 if (pmd_none(*pmd)) {
397 pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
398 __pmd_populate(pmd, __pa(pte) | type->prot_l1);
399 }
Russell Kingae8f1542006-09-27 15:38:34 +0100400
Russell King24e6c692007-04-21 10:21:28 +0100401 pte = pte_offset_kernel(pmd, addr);
402 do {
Russell Kingc172cc92007-04-21 10:52:32 +0100403 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
404 type->prot_pte_ext);
Russell King24e6c692007-04-21 10:21:28 +0100405 pfn++;
406 } while (pte++, addr += PAGE_SIZE, addr != end);
Russell Kingae8f1542006-09-27 15:38:34 +0100407}
408
Russell King24e6c692007-04-21 10:21:28 +0100409static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
410 unsigned long end, unsigned long phys,
411 const struct mem_type *type)
Russell Kingae8f1542006-09-27 15:38:34 +0100412{
Russell King24e6c692007-04-21 10:21:28 +0100413 pmd_t *pmd = pmd_offset(pgd, addr);
Russell Kingae8f1542006-09-27 15:38:34 +0100414
Russell King24e6c692007-04-21 10:21:28 +0100415 /*
416 * Try a section mapping - end, addr and phys must all be aligned
417 * to a section boundary. Note that PMDs refer to the individual
418 * L1 entries, whereas PGDs refer to a group of L1 entries making
419 * up one logical pointer to an L2 table.
420 */
421 if (((addr | end | phys) & ~SECTION_MASK) == 0) {
422 pmd_t *p = pmd;
Russell Kingae8f1542006-09-27 15:38:34 +0100423
Russell King24e6c692007-04-21 10:21:28 +0100424 if (addr & SECTION_SIZE)
425 pmd++;
426
427 do {
428 *pmd = __pmd(phys | type->prot_sect);
429 phys += SECTION_SIZE;
430 } while (pmd++, addr += SECTION_SIZE, addr != end);
431
432 flush_pmd_entry(p);
433 } else {
434 /*
435 * No need to loop; pte's aren't interested in the
436 * individual L1 entries.
437 */
438 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
Russell Kingae8f1542006-09-27 15:38:34 +0100439 }
Russell Kingae8f1542006-09-27 15:38:34 +0100440}
441
Russell King4a56c1e2007-04-21 10:16:48 +0100442static void __init create_36bit_mapping(struct map_desc *md,
443 const struct mem_type *type)
444{
445 unsigned long phys, addr, length, end;
446 pgd_t *pgd;
447
448 addr = md->virtual;
449 phys = (unsigned long)__pfn_to_phys(md->pfn);
450 length = PAGE_ALIGN(md->length);
451
452 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
453 printk(KERN_ERR "MM: CPU does not support supersection "
454 "mapping for 0x%08llx at 0x%08lx\n",
455 __pfn_to_phys((u64)md->pfn), addr);
456 return;
457 }
458
459 /* N.B. ARMv6 supersections are only defined to work with domain 0.
460 * Since domain assignments can in fact be arbitrary, the
461 * 'domain == 0' check below is required to insure that ARMv6
462 * supersections are only allocated for domain 0 regardless
463 * of the actual domain assignments in use.
464 */
465 if (type->domain) {
466 printk(KERN_ERR "MM: invalid domain in supersection "
467 "mapping for 0x%08llx at 0x%08lx\n",
468 __pfn_to_phys((u64)md->pfn), addr);
469 return;
470 }
471
472 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
473 printk(KERN_ERR "MM: cannot create mapping for "
474 "0x%08llx at 0x%08lx invalid alignment\n",
475 __pfn_to_phys((u64)md->pfn), addr);
476 return;
477 }
478
479 /*
480 * Shift bits [35:32] of address into bits [23:20] of PMD
481 * (See ARMv6 spec).
482 */
483 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
484
485 pgd = pgd_offset_k(addr);
486 end = addr + length;
487 do {
488 pmd_t *pmd = pmd_offset(pgd, addr);
489 int i;
490
491 for (i = 0; i < 16; i++)
492 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
493
494 addr += SUPERSECTION_SIZE;
495 phys += SUPERSECTION_SIZE;
496 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
497 } while (addr != end);
498}
499
Russell Kingae8f1542006-09-27 15:38:34 +0100500/*
501 * Create the page directory entries and any necessary
502 * page tables for the mapping specified by `md'. We
503 * are able to cope here with varying sizes and address
504 * offsets, and we take full advantage of sections and
505 * supersections.
506 */
507void __init create_mapping(struct map_desc *md)
508{
Russell King24e6c692007-04-21 10:21:28 +0100509 unsigned long phys, addr, length, end;
Russell Kingd5c98172007-04-21 10:05:32 +0100510 const struct mem_type *type;
Russell King24e6c692007-04-21 10:21:28 +0100511 pgd_t *pgd;
Russell Kingae8f1542006-09-27 15:38:34 +0100512
513 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
514 printk(KERN_WARNING "BUG: not creating mapping for "
515 "0x%08llx at 0x%08lx in user region\n",
516 __pfn_to_phys((u64)md->pfn), md->virtual);
517 return;
518 }
519
520 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
521 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
522 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
523 "overlaps vmalloc space\n",
524 __pfn_to_phys((u64)md->pfn), md->virtual);
525 }
526
Russell Kingd5c98172007-04-21 10:05:32 +0100527 type = &mem_types[md->type];
Russell Kingae8f1542006-09-27 15:38:34 +0100528
529 /*
530 * Catch 36-bit addresses
531 */
Russell King4a56c1e2007-04-21 10:16:48 +0100532 if (md->pfn >= 0x100000) {
533 create_36bit_mapping(md, type);
534 return;
Russell Kingae8f1542006-09-27 15:38:34 +0100535 }
536
Russell King7b9c7b42007-07-04 21:16:33 +0100537 addr = md->virtual & PAGE_MASK;
Russell King24e6c692007-04-21 10:21:28 +0100538 phys = (unsigned long)__pfn_to_phys(md->pfn);
Russell King7b9c7b42007-07-04 21:16:33 +0100539 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
Russell Kingae8f1542006-09-27 15:38:34 +0100540
Russell King24e6c692007-04-21 10:21:28 +0100541 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
Russell Kingae8f1542006-09-27 15:38:34 +0100542 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
543 "be mapped using pages, ignoring.\n",
Russell King24e6c692007-04-21 10:21:28 +0100544 __pfn_to_phys(md->pfn), addr);
Russell Kingae8f1542006-09-27 15:38:34 +0100545 return;
546 }
547
Russell King24e6c692007-04-21 10:21:28 +0100548 pgd = pgd_offset_k(addr);
549 end = addr + length;
550 do {
551 unsigned long next = pgd_addr_end(addr, end);
Russell Kingae8f1542006-09-27 15:38:34 +0100552
Russell King24e6c692007-04-21 10:21:28 +0100553 alloc_init_section(pgd, addr, next, phys, type);
Russell Kingae8f1542006-09-27 15:38:34 +0100554
Russell King24e6c692007-04-21 10:21:28 +0100555 phys += next - addr;
556 addr = next;
557 } while (pgd++, addr != end);
Russell Kingae8f1542006-09-27 15:38:34 +0100558}
559
560/*
561 * Create the architecture specific mappings
562 */
563void __init iotable_init(struct map_desc *io_desc, int nr)
564{
565 int i;
566
567 for (i = 0; i < nr; i++)
568 create_mapping(io_desc + i);
569}
570
Lennert Buytenhek60296c72008-08-05 01:56:13 +0200571static int __init check_membank_valid(struct membank *mb)
572{
573 /*
574 * Check whether this memory region has non-zero size.
575 */
576 if (mb->size == 0)
577 return 0;
578
579 /*
580 * Check whether this memory region would entirely overlap
581 * the vmalloc area.
582 */
583 if (phys_to_virt(mb->start) >= VMALLOC_MIN) {
584 printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
585 "(vmalloc region overlap).\n",
586 mb->start, mb->start + mb->size - 1);
587 return 0;
588 }
589
590 /*
591 * Check whether this memory region would partially overlap
592 * the vmalloc area.
593 */
594 if (phys_to_virt(mb->start + mb->size) < phys_to_virt(mb->start) ||
595 phys_to_virt(mb->start + mb->size) > VMALLOC_MIN) {
596 unsigned long newsize = VMALLOC_MIN - phys_to_virt(mb->start);
597
598 printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
599 "to -%.8lx (vmalloc region overlap).\n",
600 mb->start, mb->start + mb->size - 1,
601 mb->start + newsize - 1);
602 mb->size = newsize;
603 }
604
605 return 1;
606}
607
608static void __init sanity_check_meminfo(struct meminfo *mi)
609{
610 int i;
611 int j;
612
613 for (i = 0, j = 0; i < mi->nr_banks; i++) {
614 if (check_membank_valid(&mi->bank[i]))
615 mi->bank[j++] = mi->bank[i];
616 }
617 mi->nr_banks = j;
618}
619
Russell Kingd111e8f2006-09-27 15:27:33 +0100620static inline void prepare_page_table(struct meminfo *mi)
621{
622 unsigned long addr;
623
624 /*
625 * Clear out all the mappings below the kernel image.
626 */
627 for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE)
628 pmd_clear(pmd_off_k(addr));
629
630#ifdef CONFIG_XIP_KERNEL
631 /* The XIP kernel is mapped in the module area -- skip over it */
632 addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
633#endif
634 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
635 pmd_clear(pmd_off_k(addr));
636
637 /*
638 * Clear out all the kernel space mappings, except for the first
639 * memory bank, up to the end of the vmalloc region.
640 */
641 for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size);
642 addr < VMALLOC_END; addr += PGDIR_SIZE)
643 pmd_clear(pmd_off_k(addr));
644}
645
646/*
647 * Reserve the various regions of node 0
648 */
649void __init reserve_node_zero(pg_data_t *pgdat)
650{
651 unsigned long res_size = 0;
652
653 /*
654 * Register the kernel text and data with bootmem.
655 * Note that this can only be in node 0.
656 */
657#ifdef CONFIG_XIP_KERNEL
Bernhard Walle72a7fe32008-02-07 00:15:17 -0800658 reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start,
659 BOOTMEM_DEFAULT);
Russell Kingd111e8f2006-09-27 15:27:33 +0100660#else
Bernhard Walle72a7fe32008-02-07 00:15:17 -0800661 reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext,
662 BOOTMEM_DEFAULT);
Russell Kingd111e8f2006-09-27 15:27:33 +0100663#endif
664
665 /*
666 * Reserve the page tables. These are already in use,
667 * and can only be in node 0.
668 */
669 reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
Bernhard Walle72a7fe32008-02-07 00:15:17 -0800670 PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT);
Russell Kingd111e8f2006-09-27 15:27:33 +0100671
672 /*
673 * Hmm... This should go elsewhere, but we really really need to
674 * stop things allocating the low memory; ideally we need a better
675 * implementation of GFP_DMA which does not assume that DMA-able
676 * memory starts at zero.
677 */
678 if (machine_is_integrator() || machine_is_cintegrator())
679 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
680
681 /*
682 * These should likewise go elsewhere. They pre-reserve the
683 * screen memory region at the start of main system memory.
684 */
685 if (machine_is_edb7211())
686 res_size = 0x00020000;
687 if (machine_is_p720t())
688 res_size = 0x00014000;
689
Ben Dooksbbf6f282006-12-07 20:47:58 +0100690 /* H1940 and RX3715 need to reserve this for suspend */
691
692 if (machine_is_h1940() || machine_is_rx3715()) {
Bernhard Walle72a7fe32008-02-07 00:15:17 -0800693 reserve_bootmem_node(pgdat, 0x30003000, 0x1000,
694 BOOTMEM_DEFAULT);
695 reserve_bootmem_node(pgdat, 0x30081000, 0x1000,
696 BOOTMEM_DEFAULT);
Ben Dooks90733412006-12-06 01:50:24 +0100697 }
698
Russell Kingd111e8f2006-09-27 15:27:33 +0100699#ifdef CONFIG_SA1111
700 /*
701 * Because of the SA1111 DMA bug, we want to preserve our
702 * precious DMA-able memory...
703 */
704 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
705#endif
706 if (res_size)
Bernhard Walle72a7fe32008-02-07 00:15:17 -0800707 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size,
708 BOOTMEM_DEFAULT);
Russell Kingd111e8f2006-09-27 15:27:33 +0100709}
710
711/*
712 * Set up device the mappings. Since we clear out the page tables for all
713 * mappings above VMALLOC_END, we will remove any debug device mappings.
714 * This means you have to be careful how you debug this function, or any
715 * called function. This means you can't use any function or debugging
716 * method which may touch any device, otherwise the kernel _will_ crash.
717 */
718static void __init devicemaps_init(struct machine_desc *mdesc)
719{
720 struct map_desc map;
721 unsigned long addr;
722 void *vectors;
723
724 /*
725 * Allocate the vector page early.
726 */
727 vectors = alloc_bootmem_low_pages(PAGE_SIZE);
728 BUG_ON(!vectors);
729
730 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
731 pmd_clear(pmd_off_k(addr));
732
733 /*
734 * Map the kernel if it is XIP.
735 * It is always first in the modulearea.
736 */
737#ifdef CONFIG_XIP_KERNEL
738 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
739 map.virtual = MODULE_START;
740 map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
741 map.type = MT_ROM;
742 create_mapping(&map);
743#endif
744
745 /*
746 * Map the cache flushing regions.
747 */
748#ifdef FLUSH_BASE
749 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
750 map.virtual = FLUSH_BASE;
751 map.length = SZ_1M;
752 map.type = MT_CACHECLEAN;
753 create_mapping(&map);
754#endif
755#ifdef FLUSH_BASE_MINICACHE
756 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
757 map.virtual = FLUSH_BASE_MINICACHE;
758 map.length = SZ_1M;
759 map.type = MT_MINICLEAN;
760 create_mapping(&map);
761#endif
762
763 /*
764 * Create a mapping for the machine vectors at the high-vectors
765 * location (0xffff0000). If we aren't using high-vectors, also
766 * create a mapping at the low-vectors virtual address.
767 */
768 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
769 map.virtual = 0xffff0000;
770 map.length = PAGE_SIZE;
771 map.type = MT_HIGH_VECTORS;
772 create_mapping(&map);
773
774 if (!vectors_high()) {
775 map.virtual = 0;
776 map.type = MT_LOW_VECTORS;
777 create_mapping(&map);
778 }
779
780 /*
781 * Ask the machine support to map in the statically mapped devices.
782 */
783 if (mdesc->map_io)
784 mdesc->map_io();
785
786 /*
787 * Finally flush the caches and tlb to ensure that we're in a
788 * consistent state wrt the writebuffer. This also ensures that
789 * any write-allocated cache lines in the vector page are written
790 * back. After this point, we can start to touch devices again.
791 */
792 local_flush_tlb_all();
793 flush_cache_all();
794}
795
796/*
797 * paging_init() sets up the page tables, initialises the zone memory
798 * maps, and sets up the zero page, bad page and bad page tables.
799 */
800void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
801{
802 void *zero_page;
803
804 build_mem_type_table();
Lennert Buytenhek60296c72008-08-05 01:56:13 +0200805 sanity_check_meminfo(mi);
Russell Kingd111e8f2006-09-27 15:27:33 +0100806 prepare_page_table(mi);
807 bootmem_init(mi);
808 devicemaps_init(mdesc);
809
810 top_pmd = pmd_off_k(0xffff0000);
811
812 /*
813 * allocate the zero page. Note that we count on this going ok.
814 */
815 zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
816 memzero(zero_page, PAGE_SIZE);
817 empty_zero_page = virt_to_page(zero_page);
818 flush_dcache_page(empty_zero_page);
819}
Russell Kingae8f1542006-09-27 15:38:34 +0100820
821/*
822 * In order to soft-boot, we need to insert a 1:1 mapping in place of
823 * the user-mode pages. This will then ensure that we have predictable
824 * results when turning the mmu off
825 */
826void setup_mm_for_reboot(char mode)
827{
828 unsigned long base_pmdval;
829 pgd_t *pgd;
830 int i;
831
832 if (current->mm && current->mm->pgd)
833 pgd = current->mm->pgd;
834 else
835 pgd = init_mm.pgd;
836
837 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
838 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
839 base_pmdval |= PMD_BIT4;
840
841 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
842 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
843 pmd_t *pmd;
844
845 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
846 pmd[0] = __pmd(pmdval);
847 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
848 flush_pmd_entry(pmd);
849 }
850}