| Stephen Warren | 4fb0384 | 2012-04-10 16:32:00 -0600 | [diff] [blame] | 1 | NVIDIA Tegra30 I2S controller |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible : "nvidia,tegra30-i2s" |
| 5 | - reg : Should contain I2S registers location and length |
| Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 6 | - clocks : Must contain one entry, for the module clock. |
| 7 | See ../clocks/clock-bindings.txt for details. |
| Stephen Warren | 0799958 | 2013-11-07 10:11:27 -0700 | [diff] [blame] | 8 | - resets : Must contain an entry for each entry in reset-names. |
| 9 | See ../reset/reset.txt for details. |
| 10 | - reset-names : Must include the following entries: |
| 11 | - i2s |
| Stephen Warren | 4fb0384 | 2012-04-10 16:32:00 -0600 | [diff] [blame] | 12 | - nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback) |
| 13 | first, tx (capture) second. See nvidia,tegra30-ahub.txt for values. |
| 14 | |
| 15 | Example: |
| 16 | |
| Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 17 | i2s@70080300 { |
| Stephen Warren | 4fb0384 | 2012-04-10 16:32:00 -0600 | [diff] [blame] | 18 | compatible = "nvidia,tegra30-i2s"; |
| 19 | reg = <0x70080300 0x100>; |
| 20 | nvidia,ahub-cif-ids = <4 4>; |
| Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 21 | clocks = <&tegra_car 11>; |
| Stephen Warren | 0799958 | 2013-11-07 10:11:27 -0700 | [diff] [blame] | 22 | resets = <&tegra_car 11>; |
| 23 | reset-names = "i2s"; |
| Stephen Warren | 4fb0384 | 2012-04-10 16:32:00 -0600 | [diff] [blame] | 24 | }; |