Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 1 | #include <linux/linkage.h> |
Russell King | 941aefa | 2011-02-11 11:32:19 +0000 | [diff] [blame] | 2 | #include <linux/threads.h> |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 3 | #include <asm/asm-offsets.h> |
| 4 | #include <asm/assembler.h> |
| 5 | #include <asm/glue-cache.h> |
| 6 | #include <asm/glue-proc.h> |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 7 | .text |
| 8 | |
| 9 | /* |
Russell King | abda1bd | 2011-09-01 11:52:33 +0100 | [diff] [blame] | 10 | * Save CPU state for a suspend. This saves the CPU general purpose |
| 11 | * registers, and allocates space on the kernel stack to save the CPU |
| 12 | * specific registers and some other data for resume. |
| 13 | * r0 = suspend function arg0 |
| 14 | * r1 = suspend function |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 15 | */ |
Russell King | 2c74a0c | 2011-06-22 17:41:48 +0100 | [diff] [blame] | 16 | ENTRY(__cpu_suspend) |
Russell King | e8856a8 | 2011-06-13 15:58:34 +0100 | [diff] [blame] | 17 | stmfd sp!, {r4 - r11, lr} |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 18 | #ifdef MULTI_CPU |
| 19 | ldr r10, =processor |
Russell King | abda1bd | 2011-09-01 11:52:33 +0100 | [diff] [blame] | 20 | ldr r4, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state |
Russell King | 3fd431b | 2011-06-13 13:53:06 +0100 | [diff] [blame] | 21 | #else |
Russell King | abda1bd | 2011-09-01 11:52:33 +0100 | [diff] [blame] | 22 | ldr r4, =cpu_suspend_size |
Russell King | 3fd431b | 2011-06-13 13:53:06 +0100 | [diff] [blame] | 23 | #endif |
Russell King | abda1bd | 2011-09-01 11:52:33 +0100 | [diff] [blame] | 24 | mov r5, sp @ current virtual SP |
| 25 | add r4, r4, #12 @ Space for pgd, virt sp, phys resume fn |
| 26 | sub sp, sp, r4 @ allocate CPU state on stack |
| 27 | stmfd sp!, {r0, r1} @ save suspend func arg and pointer |
| 28 | add r0, sp, #8 @ save pointer to save block |
| 29 | mov r1, r4 @ size of save block |
| 30 | mov r2, r5 @ virtual SP |
| 31 | ldr r3, =sleep_save_sp |
Russell King | 941aefa | 2011-02-11 11:32:19 +0000 | [diff] [blame] | 32 | #ifdef CONFIG_SMP |
| 33 | ALT_SMP(mrc p15, 0, lr, c0, c0, 5) |
| 34 | ALT_UP(mov lr, #0) |
| 35 | and lr, lr, #15 |
Russell King | abda1bd | 2011-09-01 11:52:33 +0100 | [diff] [blame] | 36 | add r3, r3, lr, lsl #2 |
Russell King | 941aefa | 2011-02-11 11:32:19 +0000 | [diff] [blame] | 37 | #endif |
Russell King | abda1bd | 2011-09-01 11:52:33 +0100 | [diff] [blame] | 38 | bl __cpu_suspend_save |
Russell King | 29cb3cd | 2011-07-02 09:54:01 +0100 | [diff] [blame] | 39 | adr lr, BSYM(cpu_suspend_abort) |
Russell King | 3799bbe | 2011-06-13 15:28:40 +0100 | [diff] [blame] | 40 | ldmfd sp!, {r0, pc} @ call suspend fn |
Russell King | 2c74a0c | 2011-06-22 17:41:48 +0100 | [diff] [blame] | 41 | ENDPROC(__cpu_suspend) |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 42 | .ltorg |
| 43 | |
Russell King | 29cb3cd | 2011-07-02 09:54:01 +0100 | [diff] [blame] | 44 | cpu_suspend_abort: |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 45 | ldmia sp!, {r1 - r3} @ pop phys pgd, virt SP, phys resume fn |
Russell King | f5fa68d | 2011-08-27 11:17:36 +0100 | [diff] [blame] | 46 | teq r0, #0 |
| 47 | moveq r0, #1 @ force non-zero value |
Russell King | 29cb3cd | 2011-07-02 09:54:01 +0100 | [diff] [blame] | 48 | mov sp, r2 |
| 49 | ldmfd sp!, {r4 - r11, pc} |
| 50 | ENDPROC(cpu_suspend_abort) |
| 51 | |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 52 | /* |
| 53 | * r0 = control register value |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 54 | */ |
Russell King | 62b2d07 | 2011-08-31 23:26:18 +0100 | [diff] [blame] | 55 | .align 5 |
Will Deacon | e6eadc6 | 2011-11-15 11:11:19 +0000 | [diff] [blame] | 56 | .pushsection .idmap.text,"ax" |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 57 | ENTRY(cpu_resume_mmu) |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 58 | ldr r3, =cpu_resume_after_mmu |
Will Deacon | d675d0b | 2011-11-22 17:30:28 +0000 | [diff] [blame] | 59 | instr_sync |
Russell King | e8ce0eb | 2011-08-26 20:28:52 +0100 | [diff] [blame] | 60 | mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc |
| 61 | mrc p15, 0, r0, c0, c0, 0 @ read id reg |
Will Deacon | d675d0b | 2011-11-22 17:30:28 +0000 | [diff] [blame] | 62 | instr_sync |
Russell King | e8ce0eb | 2011-08-26 20:28:52 +0100 | [diff] [blame] | 63 | mov r0, r0 |
| 64 | mov r0, r0 |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 65 | mov pc, r3 @ jump to virtual address |
Russell King | 62b2d07 | 2011-08-31 23:26:18 +0100 | [diff] [blame] | 66 | ENDPROC(cpu_resume_mmu) |
Will Deacon | e6eadc6 | 2011-11-15 11:11:19 +0000 | [diff] [blame] | 67 | .popsection |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 68 | cpu_resume_after_mmu: |
Russell King | 14cd8fd | 2011-06-21 16:32:58 +0100 | [diff] [blame] | 69 | bl cpu_init @ restore the und/abt/irq banked regs |
Russell King | 29cb3cd | 2011-07-02 09:54:01 +0100 | [diff] [blame] | 70 | mov r0, #0 @ return zero on success |
Russell King | 5fa94c8 | 2011-06-13 15:04:14 +0100 | [diff] [blame] | 71 | ldmfd sp!, {r4 - r11, pc} |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 72 | ENDPROC(cpu_resume_after_mmu) |
| 73 | |
| 74 | /* |
| 75 | * Note: Yes, part of the following code is located into the .data section. |
| 76 | * This is to allow sleep_save_sp to be accessed with a relative load |
| 77 | * while we can't rely on any MMU translation. We could have put |
| 78 | * sleep_save_sp in the .text section as well, but some setups might |
| 79 | * insist on it to be truly read-only. |
| 80 | */ |
| 81 | .data |
| 82 | .align |
| 83 | ENTRY(cpu_resume) |
Russell King | 941aefa | 2011-02-11 11:32:19 +0000 | [diff] [blame] | 84 | #ifdef CONFIG_SMP |
| 85 | adr r0, sleep_save_sp |
| 86 | ALT_SMP(mrc p15, 0, r1, c0, c0, 5) |
| 87 | ALT_UP(mov r1, #0) |
| 88 | and r1, r1, #15 |
| 89 | ldr r0, [r0, r1, lsl #2] @ stack phys addr |
| 90 | #else |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 91 | ldr r0, sleep_save_sp @ stack phys addr |
Russell King | 941aefa | 2011-02-11 11:32:19 +0000 | [diff] [blame] | 92 | #endif |
Nicolas Pitre | fb4fe87 | 2011-03-22 19:09:14 +0100 | [diff] [blame] | 93 | setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 94 | @ load phys pgd, stack, resume fn |
| 95 | ARM( ldmia r0!, {r1, sp, pc} ) |
| 96 | THUMB( ldmia r0!, {r1, r2, r3} ) |
| 97 | THUMB( mov sp, r2 ) |
| 98 | THUMB( bx r3 ) |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 99 | ENDPROC(cpu_resume) |
| 100 | |
| 101 | sleep_save_sp: |
Russell King | 941aefa | 2011-02-11 11:32:19 +0000 | [diff] [blame] | 102 | .rept CONFIG_NR_CPUS |
| 103 | .long 0 @ preserve stack phys ptr here |
| 104 | .endr |