Sergey Ryazanov | ba91034 | 2014-10-29 03:18:40 +0400 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. |
| 7 | * Copyright (C) 2006 FON Technology, SL. |
| 8 | * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org> |
| 9 | * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org> |
| 10 | * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com> |
| 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * Platform devices for Atheros AR2315 SoCs |
| 15 | */ |
| 16 | |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/kernel.h> |
Sergey Ryazanov | 1753e74 | 2014-10-29 03:18:41 +0400 | [diff] [blame] | 19 | #include <linux/bitops.h> |
| 20 | #include <linux/irqdomain.h> |
| 21 | #include <linux/interrupt.h> |
Sergey Ryazanov | ba91034 | 2014-10-29 03:18:40 +0400 | [diff] [blame] | 22 | #include <linux/reboot.h> |
| 23 | #include <asm/bootinfo.h> |
| 24 | #include <asm/reboot.h> |
| 25 | #include <asm/time.h> |
| 26 | |
| 27 | #include "devices.h" |
| 28 | #include "ar2315.h" |
| 29 | #include "ar2315_regs.h" |
| 30 | |
| 31 | static void __iomem *ar2315_rst_base; |
Sergey Ryazanov | 1753e74 | 2014-10-29 03:18:41 +0400 | [diff] [blame] | 32 | static struct irq_domain *ar2315_misc_irq_domain; |
Sergey Ryazanov | ba91034 | 2014-10-29 03:18:40 +0400 | [diff] [blame] | 33 | |
| 34 | static inline u32 ar2315_rst_reg_read(u32 reg) |
| 35 | { |
| 36 | return __raw_readl(ar2315_rst_base + reg); |
| 37 | } |
| 38 | |
| 39 | static inline void ar2315_rst_reg_write(u32 reg, u32 val) |
| 40 | { |
| 41 | __raw_writel(val, ar2315_rst_base + reg); |
| 42 | } |
| 43 | |
| 44 | static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val) |
| 45 | { |
| 46 | u32 ret = ar2315_rst_reg_read(reg); |
| 47 | |
| 48 | ret &= ~mask; |
| 49 | ret |= val; |
| 50 | ar2315_rst_reg_write(reg, ret); |
| 51 | } |
| 52 | |
Sergey Ryazanov | 1753e74 | 2014-10-29 03:18:41 +0400 | [diff] [blame] | 53 | static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id) |
| 54 | { |
| 55 | ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET); |
| 56 | ar2315_rst_reg_read(AR2315_AHB_ERR1); |
| 57 | |
| 58 | pr_emerg("AHB fatal error\n"); |
| 59 | machine_restart("AHB error"); /* Catastrophic failure */ |
| 60 | |
| 61 | return IRQ_HANDLED; |
| 62 | } |
| 63 | |
| 64 | static struct irqaction ar2315_ahb_err_interrupt = { |
| 65 | .handler = ar2315_ahb_err_handler, |
| 66 | .name = "ar2315-ahb-error", |
| 67 | }; |
| 68 | |
| 69 | static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc) |
| 70 | { |
| 71 | u32 pending = ar2315_rst_reg_read(AR2315_ISR) & |
| 72 | ar2315_rst_reg_read(AR2315_IMR); |
| 73 | unsigned nr, misc_irq = 0; |
| 74 | |
| 75 | if (pending) { |
| 76 | struct irq_domain *domain = irq_get_handler_data(irq); |
| 77 | |
| 78 | nr = __ffs(pending); |
| 79 | misc_irq = irq_find_mapping(domain, nr); |
| 80 | } |
| 81 | |
| 82 | if (misc_irq) { |
| 83 | if (nr == AR2315_MISC_IRQ_GPIO) |
| 84 | ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO); |
| 85 | else if (nr == AR2315_MISC_IRQ_WATCHDOG) |
| 86 | ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD); |
| 87 | generic_handle_irq(misc_irq); |
| 88 | } else { |
| 89 | spurious_interrupt(); |
| 90 | } |
| 91 | } |
| 92 | |
| 93 | static void ar2315_misc_irq_unmask(struct irq_data *d) |
| 94 | { |
| 95 | ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq)); |
| 96 | } |
| 97 | |
| 98 | static void ar2315_misc_irq_mask(struct irq_data *d) |
| 99 | { |
| 100 | ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0); |
| 101 | } |
| 102 | |
| 103 | static struct irq_chip ar2315_misc_irq_chip = { |
| 104 | .name = "ar2315-misc", |
| 105 | .irq_unmask = ar2315_misc_irq_unmask, |
| 106 | .irq_mask = ar2315_misc_irq_mask, |
| 107 | }; |
| 108 | |
| 109 | static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq, |
| 110 | irq_hw_number_t hw) |
| 111 | { |
| 112 | irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq); |
| 113 | return 0; |
| 114 | } |
| 115 | |
| 116 | static struct irq_domain_ops ar2315_misc_irq_domain_ops = { |
| 117 | .map = ar2315_misc_irq_map, |
| 118 | }; |
| 119 | |
| 120 | /* |
| 121 | * Called when an interrupt is received, this function |
| 122 | * determines exactly which interrupt it was, and it |
| 123 | * invokes the appropriate handler. |
| 124 | * |
| 125 | * Implicitly, we also define interrupt priority by |
| 126 | * choosing which to dispatch first. |
| 127 | */ |
| 128 | static void ar2315_irq_dispatch(void) |
| 129 | { |
| 130 | u32 pending = read_c0_status() & read_c0_cause(); |
| 131 | |
| 132 | if (pending & CAUSEF_IP3) |
| 133 | do_IRQ(AR2315_IRQ_WLAN0); |
| 134 | else if (pending & CAUSEF_IP2) |
| 135 | do_IRQ(AR2315_IRQ_MISC); |
| 136 | else if (pending & CAUSEF_IP7) |
| 137 | do_IRQ(ATH25_IRQ_CPU_CLOCK); |
| 138 | else |
| 139 | spurious_interrupt(); |
| 140 | } |
| 141 | |
| 142 | void __init ar2315_arch_init_irq(void) |
| 143 | { |
| 144 | struct irq_domain *domain; |
| 145 | unsigned irq; |
| 146 | |
| 147 | ath25_irq_dispatch = ar2315_irq_dispatch; |
| 148 | |
| 149 | domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT, |
| 150 | &ar2315_misc_irq_domain_ops, NULL); |
| 151 | if (!domain) |
| 152 | panic("Failed to add IRQ domain"); |
| 153 | |
| 154 | irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB); |
| 155 | setup_irq(irq, &ar2315_ahb_err_interrupt); |
| 156 | |
| 157 | irq_set_chained_handler(AR2315_IRQ_MISC, ar2315_misc_irq_handler); |
| 158 | irq_set_handler_data(AR2315_IRQ_MISC, domain); |
| 159 | |
| 160 | ar2315_misc_irq_domain = domain; |
| 161 | } |
| 162 | |
Sergey Ryazanov | a747371 | 2014-10-29 03:18:44 +0400 | [diff] [blame^] | 163 | void __init ar2315_init_devices(void) |
| 164 | { |
| 165 | /* Find board configuration */ |
| 166 | ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE); |
| 167 | } |
| 168 | |
Sergey Ryazanov | ba91034 | 2014-10-29 03:18:40 +0400 | [diff] [blame] | 169 | static void ar2315_restart(char *command) |
| 170 | { |
| 171 | void (*mips_reset_vec)(void) = (void *)0xbfc00000; |
| 172 | |
| 173 | local_irq_disable(); |
| 174 | |
| 175 | /* try reset the system via reset control */ |
| 176 | ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM); |
| 177 | |
| 178 | /* Cold reset does not work on the AR2315/6, use the GPIO reset bits |
| 179 | * a workaround. Give it some time to attempt a gpio based hardware |
| 180 | * reset (atheros reference design workaround) */ |
| 181 | |
| 182 | /* TODO: implement the GPIO reset workaround */ |
| 183 | |
| 184 | /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic |
| 185 | * workaround. Attempt to jump to the mips reset location - |
| 186 | * the boot loader itself might be able to recover the system */ |
| 187 | mips_reset_vec(); |
| 188 | } |
| 189 | |
| 190 | /* |
| 191 | * This table is indexed by bits 5..4 of the CLOCKCTL1 register |
| 192 | * to determine the predevisor value. |
| 193 | */ |
| 194 | static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 }; |
| 195 | static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 }; |
| 196 | |
| 197 | static unsigned __init ar2315_sys_clk(u32 clock_ctl) |
| 198 | { |
| 199 | unsigned int pllc_ctrl, cpu_div; |
| 200 | unsigned int pllc_out, refdiv, fdiv, divby2; |
| 201 | unsigned int clk_div; |
| 202 | |
| 203 | pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL); |
| 204 | refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV); |
| 205 | refdiv = clockctl1_predivide_table[refdiv]; |
| 206 | fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV); |
| 207 | divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1; |
| 208 | pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv; |
| 209 | |
| 210 | /* clkm input selected */ |
| 211 | switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) { |
| 212 | case 0: |
| 213 | case 1: |
| 214 | clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV); |
| 215 | clk_div = pllc_divide_table[clk_div]; |
| 216 | break; |
| 217 | case 2: |
| 218 | clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV); |
| 219 | clk_div = pllc_divide_table[clk_div]; |
| 220 | break; |
| 221 | default: |
| 222 | pllc_out = 40000000; |
| 223 | clk_div = 1; |
| 224 | break; |
| 225 | } |
| 226 | |
| 227 | cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV); |
| 228 | cpu_div = cpu_div * 2 ?: 1; |
| 229 | |
| 230 | return pllc_out / (clk_div * cpu_div); |
| 231 | } |
| 232 | |
| 233 | static inline unsigned ar2315_cpu_frequency(void) |
| 234 | { |
| 235 | return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK)); |
| 236 | } |
| 237 | |
| 238 | static inline unsigned ar2315_apb_frequency(void) |
| 239 | { |
| 240 | return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK)); |
| 241 | } |
| 242 | |
| 243 | void __init ar2315_plat_time_init(void) |
| 244 | { |
| 245 | mips_hpt_frequency = ar2315_cpu_frequency() / 2; |
| 246 | } |
| 247 | |
| 248 | void __init ar2315_plat_mem_setup(void) |
| 249 | { |
| 250 | void __iomem *sdram_base; |
| 251 | u32 memsize, memcfg; |
| 252 | u32 config; |
| 253 | |
| 254 | /* Detect memory size */ |
| 255 | sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE, |
| 256 | AR2315_SDRAMCTL_SIZE); |
| 257 | memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG); |
| 258 | memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH); |
| 259 | memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH); |
| 260 | memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH); |
| 261 | memsize <<= 3; |
| 262 | add_memory_region(0, memsize, BOOT_MEM_RAM); |
| 263 | iounmap(sdram_base); |
| 264 | |
| 265 | ar2315_rst_base = ioremap_nocache(AR2315_RST_BASE, AR2315_RST_SIZE); |
| 266 | |
| 267 | /* Clear any lingering AHB errors */ |
| 268 | config = read_c0_config(); |
| 269 | write_c0_config(config & ~0x3); |
| 270 | ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET); |
| 271 | ar2315_rst_reg_read(AR2315_AHB_ERR1); |
| 272 | ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE); |
| 273 | |
| 274 | _machine_restart = ar2315_restart; |
| 275 | } |
Sergey Ryazanov | 1ac91b1 | 2014-10-29 03:18:43 +0400 | [diff] [blame] | 276 | |
| 277 | void __init ar2315_arch_init(void) |
| 278 | { |
| 279 | unsigned irq = irq_create_mapping(ar2315_misc_irq_domain, |
| 280 | AR2315_MISC_IRQ_UART0); |
| 281 | |
| 282 | ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency()); |
| 283 | } |