Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Parisc performance counters |
| 3 | * Copyright (C) 2001 Randolph Chung <tausq@debian.org> |
| 4 | * |
| 5 | * This code is derived, with permission, from HP/UX sources. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2, or (at your option) |
| 10 | * any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * Edited comment from original sources: |
| 24 | * |
| 25 | * This driver programs the PCX-U/PCX-W performance counters |
| 26 | * on the PA-RISC 2.0 chips. The driver keeps all images now |
| 27 | * internally to the kernel to hopefully eliminate the possiblity |
| 28 | * of a bad image halting the CPU. Also, there are different |
| 29 | * images for the PCX-W and later chips vs the PCX-U chips. |
| 30 | * |
| 31 | * Only 1 process is allowed to access the driver at any time, |
| 32 | * so the only protection that is needed is at open and close. |
| 33 | * A variable "perf_enabled" is used to hold the state of the |
| 34 | * driver. The spinlock "perf_lock" is used to protect the |
| 35 | * modification of the state during open/close operations so |
| 36 | * multiple processes don't get into the driver simultaneously. |
| 37 | * |
| 38 | * This driver accesses the processor directly vs going through |
| 39 | * the PDC INTRIGUE calls. This is done to eliminate bugs introduced |
| 40 | * in various PDC revisions. The code is much more maintainable |
| 41 | * and reliable this way vs having to debug on every version of PDC |
| 42 | * on every box. |
| 43 | */ |
| 44 | |
Randy Dunlap | a941564 | 2006-01-11 12:17:48 -0800 | [diff] [blame] | 45 | #include <linux/capability.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | #include <linux/init.h> |
| 47 | #include <linux/proc_fs.h> |
| 48 | #include <linux/miscdevice.h> |
| 49 | #include <linux/spinlock.h> |
| 50 | |
| 51 | #include <asm/uaccess.h> |
| 52 | #include <asm/perf.h> |
| 53 | #include <asm/parisc-device.h> |
| 54 | #include <asm/processor.h> |
| 55 | #include <asm/runway.h> |
| 56 | #include <asm/io.h> /* for __raw_read() */ |
| 57 | |
| 58 | #include "perf_images.h" |
| 59 | |
| 60 | #define MAX_RDR_WORDS 24 |
| 61 | #define PERF_VERSION 2 /* derived from hpux's PI v2 interface */ |
| 62 | |
| 63 | /* definition of RDR regs */ |
| 64 | struct rdr_tbl_ent { |
| 65 | uint16_t width; |
| 66 | uint8_t num_words; |
| 67 | uint8_t write_control; |
| 68 | }; |
| 69 | |
Helge Deller | 8039de1 | 2006-01-10 20:35:03 -0500 | [diff] [blame] | 70 | static int perf_processor_interface __read_mostly = UNKNOWN_INTF; |
Helge Deller | cb6fc18 | 2006-01-17 12:40:40 -0700 | [diff] [blame] | 71 | static int perf_enabled __read_mostly; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | static spinlock_t perf_lock; |
Helge Deller | cb6fc18 | 2006-01-17 12:40:40 -0700 | [diff] [blame] | 73 | struct parisc_device *cpu_device __read_mostly; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | |
| 75 | /* RDRs to write for PCX-W */ |
Helge Deller | cb6fc18 | 2006-01-17 12:40:40 -0700 | [diff] [blame] | 76 | static const int perf_rdrs_W[] = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 77 | { 0, 1, 4, 5, 6, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 }; |
| 78 | |
| 79 | /* RDRs to write for PCX-U */ |
Helge Deller | cb6fc18 | 2006-01-17 12:40:40 -0700 | [diff] [blame] | 80 | static const int perf_rdrs_U[] = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | { 0, 1, 4, 5, 6, 7, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 }; |
| 82 | |
| 83 | /* RDR register descriptions for PCX-W */ |
Helge Deller | cb6fc18 | 2006-01-17 12:40:40 -0700 | [diff] [blame] | 84 | static const struct rdr_tbl_ent perf_rdr_tbl_W[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | { 19, 1, 8 }, /* RDR 0 */ |
| 86 | { 16, 1, 16 }, /* RDR 1 */ |
| 87 | { 72, 2, 0 }, /* RDR 2 */ |
| 88 | { 81, 2, 0 }, /* RDR 3 */ |
| 89 | { 328, 6, 0 }, /* RDR 4 */ |
| 90 | { 160, 3, 0 }, /* RDR 5 */ |
| 91 | { 336, 6, 0 }, /* RDR 6 */ |
| 92 | { 164, 3, 0 }, /* RDR 7 */ |
| 93 | { 0, 0, 0 }, /* RDR 8 */ |
| 94 | { 35, 1, 0 }, /* RDR 9 */ |
| 95 | { 6, 1, 0 }, /* RDR 10 */ |
| 96 | { 18, 1, 0 }, /* RDR 11 */ |
| 97 | { 13, 1, 0 }, /* RDR 12 */ |
| 98 | { 8, 1, 0 }, /* RDR 13 */ |
| 99 | { 8, 1, 0 }, /* RDR 14 */ |
| 100 | { 8, 1, 0 }, /* RDR 15 */ |
| 101 | { 1530, 24, 0 }, /* RDR 16 */ |
| 102 | { 16, 1, 0 }, /* RDR 17 */ |
| 103 | { 4, 1, 0 }, /* RDR 18 */ |
| 104 | { 0, 0, 0 }, /* RDR 19 */ |
| 105 | { 152, 3, 24 }, /* RDR 20 */ |
| 106 | { 152, 3, 24 }, /* RDR 21 */ |
| 107 | { 233, 4, 48 }, /* RDR 22 */ |
| 108 | { 233, 4, 48 }, /* RDR 23 */ |
| 109 | { 71, 2, 0 }, /* RDR 24 */ |
| 110 | { 71, 2, 0 }, /* RDR 25 */ |
| 111 | { 11, 1, 0 }, /* RDR 26 */ |
| 112 | { 18, 1, 0 }, /* RDR 27 */ |
| 113 | { 128, 2, 0 }, /* RDR 28 */ |
| 114 | { 0, 0, 0 }, /* RDR 29 */ |
| 115 | { 16, 1, 0 }, /* RDR 30 */ |
| 116 | { 16, 1, 0 }, /* RDR 31 */ |
| 117 | }; |
| 118 | |
| 119 | /* RDR register descriptions for PCX-U */ |
Helge Deller | cb6fc18 | 2006-01-17 12:40:40 -0700 | [diff] [blame] | 120 | static const struct rdr_tbl_ent perf_rdr_tbl_U[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 121 | { 19, 1, 8 }, /* RDR 0 */ |
| 122 | { 32, 1, 16 }, /* RDR 1 */ |
| 123 | { 20, 1, 0 }, /* RDR 2 */ |
| 124 | { 0, 0, 0 }, /* RDR 3 */ |
| 125 | { 344, 6, 0 }, /* RDR 4 */ |
| 126 | { 176, 3, 0 }, /* RDR 5 */ |
| 127 | { 336, 6, 0 }, /* RDR 6 */ |
| 128 | { 0, 0, 0 }, /* RDR 7 */ |
| 129 | { 0, 0, 0 }, /* RDR 8 */ |
| 130 | { 0, 0, 0 }, /* RDR 9 */ |
| 131 | { 28, 1, 0 }, /* RDR 10 */ |
| 132 | { 33, 1, 0 }, /* RDR 11 */ |
| 133 | { 0, 0, 0 }, /* RDR 12 */ |
| 134 | { 230, 4, 0 }, /* RDR 13 */ |
| 135 | { 32, 1, 0 }, /* RDR 14 */ |
| 136 | { 128, 2, 0 }, /* RDR 15 */ |
| 137 | { 1494, 24, 0 }, /* RDR 16 */ |
| 138 | { 18, 1, 0 }, /* RDR 17 */ |
| 139 | { 4, 1, 0 }, /* RDR 18 */ |
| 140 | { 0, 0, 0 }, /* RDR 19 */ |
| 141 | { 158, 3, 24 }, /* RDR 20 */ |
| 142 | { 158, 3, 24 }, /* RDR 21 */ |
| 143 | { 194, 4, 48 }, /* RDR 22 */ |
| 144 | { 194, 4, 48 }, /* RDR 23 */ |
| 145 | { 71, 2, 0 }, /* RDR 24 */ |
| 146 | { 71, 2, 0 }, /* RDR 25 */ |
| 147 | { 28, 1, 0 }, /* RDR 26 */ |
| 148 | { 33, 1, 0 }, /* RDR 27 */ |
| 149 | { 88, 2, 0 }, /* RDR 28 */ |
| 150 | { 32, 1, 0 }, /* RDR 29 */ |
| 151 | { 24, 1, 0 }, /* RDR 30 */ |
| 152 | { 16, 1, 0 }, /* RDR 31 */ |
| 153 | }; |
| 154 | |
| 155 | /* |
| 156 | * A non-zero write_control in the above tables is a byte offset into |
| 157 | * this array. |
| 158 | */ |
Helge Deller | cb6fc18 | 2006-01-17 12:40:40 -0700 | [diff] [blame] | 159 | static const uint64_t perf_bitmasks[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 160 | 0x0000000000000000ul, /* first dbl word must be zero */ |
| 161 | 0xfdffe00000000000ul, /* RDR0 bitmask */ |
| 162 | 0x003f000000000000ul, /* RDR1 bitmask */ |
| 163 | 0x00fffffffffffffful, /* RDR20-RDR21 bitmask (152 bits) */ |
| 164 | 0xfffffffffffffffful, |
| 165 | 0xfffffffc00000000ul, |
| 166 | 0xfffffffffffffffful, /* RDR22-RDR23 bitmask (233 bits) */ |
| 167 | 0xfffffffffffffffful, |
| 168 | 0xfffffffffffffffcul, |
| 169 | 0xff00000000000000ul |
| 170 | }; |
| 171 | |
| 172 | /* |
| 173 | * Write control bitmasks for Pa-8700 processor given |
Simon Arlott | 7022672 | 2007-05-11 20:42:34 +0100 | [diff] [blame] | 174 | * some things have changed slightly. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 175 | */ |
Helge Deller | cb6fc18 | 2006-01-17 12:40:40 -0700 | [diff] [blame] | 176 | static const uint64_t perf_bitmasks_piranha[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 177 | 0x0000000000000000ul, /* first dbl word must be zero */ |
| 178 | 0xfdffe00000000000ul, /* RDR0 bitmask */ |
| 179 | 0x003f000000000000ul, /* RDR1 bitmask */ |
| 180 | 0x00fffffffffffffful, /* RDR20-RDR21 bitmask (158 bits) */ |
| 181 | 0xfffffffffffffffful, |
| 182 | 0xfffffffc00000000ul, |
| 183 | 0xfffffffffffffffful, /* RDR22-RDR23 bitmask (210 bits) */ |
| 184 | 0xfffffffffffffffful, |
| 185 | 0xfffffffffffffffful, |
| 186 | 0xfffc000000000000ul |
| 187 | }; |
| 188 | |
Helge Deller | cb6fc18 | 2006-01-17 12:40:40 -0700 | [diff] [blame] | 189 | static const uint64_t *bitmask_array; /* array of bitmasks to use */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 190 | |
| 191 | /****************************************************************************** |
| 192 | * Function Prototypes |
| 193 | *****************************************************************************/ |
| 194 | static int perf_config(uint32_t *image_ptr); |
| 195 | static int perf_release(struct inode *inode, struct file *file); |
| 196 | static int perf_open(struct inode *inode, struct file *file); |
| 197 | static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos); |
| 198 | static ssize_t perf_write(struct file *file, const char __user *buf, size_t count, |
| 199 | loff_t *ppos); |
Christoph Hellwig | ad7dd33 | 2005-11-17 16:40:31 -0500 | [diff] [blame] | 200 | static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 201 | static void perf_start_counters(void); |
| 202 | static int perf_stop_counters(uint32_t *raddr); |
Helge Deller | cb6fc18 | 2006-01-17 12:40:40 -0700 | [diff] [blame] | 203 | static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 204 | static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer); |
| 205 | static int perf_rdr_clear(uint32_t rdr_num); |
| 206 | static int perf_write_image(uint64_t *memaddr); |
| 207 | static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer); |
| 208 | |
| 209 | /* External Assembly Routines */ |
| 210 | extern uint64_t perf_rdr_shift_in_W (uint32_t rdr_num, uint16_t width); |
| 211 | extern uint64_t perf_rdr_shift_in_U (uint32_t rdr_num, uint16_t width); |
| 212 | extern void perf_rdr_shift_out_W (uint32_t rdr_num, uint64_t buffer); |
| 213 | extern void perf_rdr_shift_out_U (uint32_t rdr_num, uint64_t buffer); |
| 214 | extern void perf_intrigue_enable_perf_counters (void); |
| 215 | extern void perf_intrigue_disable_perf_counters (void); |
| 216 | |
| 217 | /****************************************************************************** |
| 218 | * Function Definitions |
| 219 | *****************************************************************************/ |
| 220 | |
| 221 | |
| 222 | /* |
| 223 | * configure: |
| 224 | * |
| 225 | * Configure the cpu with a given data image. First turn off the counters, |
| 226 | * then download the image, then turn the counters back on. |
| 227 | */ |
| 228 | static int perf_config(uint32_t *image_ptr) |
| 229 | { |
| 230 | long error; |
| 231 | uint32_t raddr[4]; |
| 232 | |
| 233 | /* Stop the counters*/ |
| 234 | error = perf_stop_counters(raddr); |
| 235 | if (error != 0) { |
| 236 | printk("perf_config: perf_stop_counters = %ld\n", error); |
| 237 | return -EINVAL; |
| 238 | } |
| 239 | |
| 240 | printk("Preparing to write image\n"); |
| 241 | /* Write the image to the chip */ |
| 242 | error = perf_write_image((uint64_t *)image_ptr); |
| 243 | if (error != 0) { |
| 244 | printk("perf_config: DOWNLOAD = %ld\n", error); |
| 245 | return -EINVAL; |
| 246 | } |
| 247 | |
| 248 | printk("Preparing to start counters\n"); |
| 249 | |
| 250 | /* Start the counters */ |
| 251 | perf_start_counters(); |
| 252 | |
| 253 | return sizeof(uint32_t); |
| 254 | } |
| 255 | |
| 256 | /* |
| 257 | * Open the device and initialize all of its memory. The device is only |
| 258 | * opened once, but can be "queried" by multiple processes that know its |
| 259 | * file descriptor. |
| 260 | */ |
| 261 | static int perf_open(struct inode *inode, struct file *file) |
| 262 | { |
| 263 | spin_lock(&perf_lock); |
| 264 | if (perf_enabled) { |
| 265 | spin_unlock(&perf_lock); |
| 266 | return -EBUSY; |
| 267 | } |
| 268 | perf_enabled = 1; |
| 269 | spin_unlock(&perf_lock); |
| 270 | |
| 271 | return 0; |
| 272 | } |
| 273 | |
| 274 | /* |
| 275 | * Close the device. |
| 276 | */ |
| 277 | static int perf_release(struct inode *inode, struct file *file) |
| 278 | { |
| 279 | spin_lock(&perf_lock); |
| 280 | perf_enabled = 0; |
| 281 | spin_unlock(&perf_lock); |
| 282 | |
| 283 | return 0; |
| 284 | } |
| 285 | |
| 286 | /* |
| 287 | * Read does nothing for this driver |
| 288 | */ |
| 289 | static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos) |
| 290 | { |
| 291 | return 0; |
| 292 | } |
| 293 | |
| 294 | /* |
| 295 | * write: |
| 296 | * |
| 297 | * This routine downloads the image to the chip. It must be |
| 298 | * called on the processor that the download should happen |
| 299 | * on. |
| 300 | */ |
| 301 | static ssize_t perf_write(struct file *file, const char __user *buf, size_t count, |
| 302 | loff_t *ppos) |
| 303 | { |
| 304 | int err; |
| 305 | size_t image_size; |
| 306 | uint32_t image_type; |
| 307 | uint32_t interface_type; |
| 308 | uint32_t test; |
| 309 | |
| 310 | if (perf_processor_interface == ONYX_INTF) |
| 311 | image_size = PCXU_IMAGE_SIZE; |
| 312 | else if (perf_processor_interface == CUDA_INTF) |
| 313 | image_size = PCXW_IMAGE_SIZE; |
| 314 | else |
| 315 | return -EFAULT; |
| 316 | |
| 317 | if (!capable(CAP_SYS_ADMIN)) |
| 318 | return -EACCES; |
| 319 | |
| 320 | if (count != sizeof(uint32_t)) |
| 321 | return -EIO; |
| 322 | |
| 323 | if ((err = copy_from_user(&image_type, buf, sizeof(uint32_t))) != 0) |
| 324 | return err; |
| 325 | |
| 326 | /* Get the interface type and test type */ |
| 327 | interface_type = (image_type >> 16) & 0xffff; |
| 328 | test = (image_type & 0xffff); |
| 329 | |
| 330 | /* Make sure everything makes sense */ |
| 331 | |
| 332 | /* First check the machine type is correct for |
| 333 | the requested image */ |
| 334 | if (((perf_processor_interface == CUDA_INTF) && |
| 335 | (interface_type != CUDA_INTF)) || |
| 336 | ((perf_processor_interface == ONYX_INTF) && |
| 337 | (interface_type != ONYX_INTF))) |
| 338 | return -EINVAL; |
| 339 | |
| 340 | /* Next check to make sure the requested image |
| 341 | is valid */ |
| 342 | if (((interface_type == CUDA_INTF) && |
| 343 | (test >= MAX_CUDA_IMAGES)) || |
| 344 | ((interface_type == ONYX_INTF) && |
| 345 | (test >= MAX_ONYX_IMAGES))) |
| 346 | return -EINVAL; |
| 347 | |
| 348 | /* Copy the image into the processor */ |
| 349 | if (interface_type == CUDA_INTF) |
| 350 | return perf_config(cuda_images[test]); |
| 351 | else |
| 352 | return perf_config(onyx_images[test]); |
| 353 | |
| 354 | return count; |
| 355 | } |
| 356 | |
| 357 | /* |
| 358 | * Patch the images that need to know the IVA addresses. |
| 359 | */ |
| 360 | static void perf_patch_images(void) |
| 361 | { |
| 362 | #if 0 /* FIXME!! */ |
| 363 | /* |
| 364 | * NOTE: this routine is VERY specific to the current TLB image. |
| 365 | * If the image is changed, this routine might also need to be changed. |
| 366 | */ |
| 367 | extern void $i_itlb_miss_2_0(); |
| 368 | extern void $i_dtlb_miss_2_0(); |
| 369 | extern void PA2_0_iva(); |
| 370 | |
| 371 | /* |
| 372 | * We can only use the lower 32-bits, the upper 32-bits should be 0 |
| 373 | * anyway given this is in the kernel |
| 374 | */ |
| 375 | uint32_t itlb_addr = (uint32_t)&($i_itlb_miss_2_0); |
| 376 | uint32_t dtlb_addr = (uint32_t)&($i_dtlb_miss_2_0); |
| 377 | uint32_t IVAaddress = (uint32_t)&PA2_0_iva; |
| 378 | |
| 379 | if (perf_processor_interface == ONYX_INTF) { |
| 380 | /* clear last 2 bytes */ |
| 381 | onyx_images[TLBMISS][15] &= 0xffffff00; |
| 382 | /* set 2 bytes */ |
| 383 | onyx_images[TLBMISS][15] |= (0x000000ff&((dtlb_addr) >> 24)); |
| 384 | onyx_images[TLBMISS][16] = (dtlb_addr << 8)&0xffffff00; |
| 385 | onyx_images[TLBMISS][17] = itlb_addr; |
| 386 | |
| 387 | /* clear last 2 bytes */ |
| 388 | onyx_images[TLBHANDMISS][15] &= 0xffffff00; |
| 389 | /* set 2 bytes */ |
| 390 | onyx_images[TLBHANDMISS][15] |= (0x000000ff&((dtlb_addr) >> 24)); |
| 391 | onyx_images[TLBHANDMISS][16] = (dtlb_addr << 8)&0xffffff00; |
| 392 | onyx_images[TLBHANDMISS][17] = itlb_addr; |
| 393 | |
| 394 | /* clear last 2 bytes */ |
| 395 | onyx_images[BIG_CPI][15] &= 0xffffff00; |
| 396 | /* set 2 bytes */ |
| 397 | onyx_images[BIG_CPI][15] |= (0x000000ff&((dtlb_addr) >> 24)); |
| 398 | onyx_images[BIG_CPI][16] = (dtlb_addr << 8)&0xffffff00; |
| 399 | onyx_images[BIG_CPI][17] = itlb_addr; |
| 400 | |
| 401 | onyx_images[PANIC][15] &= 0xffffff00; /* clear last 2 bytes */ |
| 402 | onyx_images[PANIC][15] |= (0x000000ff&((IVAaddress) >> 24)); /* set 2 bytes */ |
| 403 | onyx_images[PANIC][16] = (IVAaddress << 8)&0xffffff00; |
| 404 | |
| 405 | |
| 406 | } else if (perf_processor_interface == CUDA_INTF) { |
| 407 | /* Cuda interface */ |
| 408 | cuda_images[TLBMISS][16] = |
| 409 | (cuda_images[TLBMISS][16]&0xffff0000) | |
| 410 | ((dtlb_addr >> 8)&0x0000ffff); |
| 411 | cuda_images[TLBMISS][17] = |
| 412 | ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); |
| 413 | cuda_images[TLBMISS][18] = (itlb_addr << 16)&0xffff0000; |
| 414 | |
| 415 | cuda_images[TLBHANDMISS][16] = |
| 416 | (cuda_images[TLBHANDMISS][16]&0xffff0000) | |
| 417 | ((dtlb_addr >> 8)&0x0000ffff); |
| 418 | cuda_images[TLBHANDMISS][17] = |
| 419 | ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); |
| 420 | cuda_images[TLBHANDMISS][18] = (itlb_addr << 16)&0xffff0000; |
| 421 | |
| 422 | cuda_images[BIG_CPI][16] = |
| 423 | (cuda_images[BIG_CPI][16]&0xffff0000) | |
| 424 | ((dtlb_addr >> 8)&0x0000ffff); |
| 425 | cuda_images[BIG_CPI][17] = |
| 426 | ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); |
| 427 | cuda_images[BIG_CPI][18] = (itlb_addr << 16)&0xffff0000; |
| 428 | } else { |
| 429 | /* Unknown type */ |
| 430 | } |
| 431 | #endif |
| 432 | } |
| 433 | |
| 434 | |
| 435 | /* |
| 436 | * ioctl routine |
| 437 | * All routines effect the processor that they are executed on. Thus you |
| 438 | * must be running on the processor that you wish to change. |
| 439 | */ |
| 440 | |
Christoph Hellwig | ad7dd33 | 2005-11-17 16:40:31 -0500 | [diff] [blame] | 441 | static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 442 | { |
| 443 | long error_start; |
Christoph Hellwig | ad7dd33 | 2005-11-17 16:40:31 -0500 | [diff] [blame] | 444 | uint32_t raddr[4]; |
| 445 | int error = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 446 | |
| 447 | switch (cmd) { |
| 448 | |
| 449 | case PA_PERF_ON: |
| 450 | /* Start the counters */ |
| 451 | perf_start_counters(); |
Christoph Hellwig | ad7dd33 | 2005-11-17 16:40:31 -0500 | [diff] [blame] | 452 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 453 | |
| 454 | case PA_PERF_OFF: |
| 455 | error_start = perf_stop_counters(raddr); |
| 456 | if (error_start != 0) { |
| 457 | printk(KERN_ERR "perf_off: perf_stop_counters = %ld\n", error_start); |
Christoph Hellwig | ad7dd33 | 2005-11-17 16:40:31 -0500 | [diff] [blame] | 458 | error = -EFAULT; |
| 459 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 460 | } |
| 461 | |
| 462 | /* copy out the Counters */ |
| 463 | if (copy_to_user((void __user *)arg, raddr, |
| 464 | sizeof (raddr)) != 0) { |
Christoph Hellwig | ad7dd33 | 2005-11-17 16:40:31 -0500 | [diff] [blame] | 465 | error = -EFAULT; |
| 466 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 467 | } |
Christoph Hellwig | ad7dd33 | 2005-11-17 16:40:31 -0500 | [diff] [blame] | 468 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 469 | |
| 470 | case PA_PERF_VERSION: |
| 471 | /* Return the version # */ |
Christoph Hellwig | ad7dd33 | 2005-11-17 16:40:31 -0500 | [diff] [blame] | 472 | error = put_user(PERF_VERSION, (int *)arg); |
| 473 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 474 | |
| 475 | default: |
Christoph Hellwig | ad7dd33 | 2005-11-17 16:40:31 -0500 | [diff] [blame] | 476 | error = -ENOTTY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 477 | } |
Christoph Hellwig | ad7dd33 | 2005-11-17 16:40:31 -0500 | [diff] [blame] | 478 | |
Christoph Hellwig | ad7dd33 | 2005-11-17 16:40:31 -0500 | [diff] [blame] | 479 | return error; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 480 | } |
| 481 | |
Arjan van de Ven | 5dfe4c9 | 2007-02-12 00:55:31 -0800 | [diff] [blame] | 482 | static const struct file_operations perf_fops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 483 | .llseek = no_llseek, |
| 484 | .read = perf_read, |
| 485 | .write = perf_write, |
Christoph Hellwig | ad7dd33 | 2005-11-17 16:40:31 -0500 | [diff] [blame] | 486 | .unlocked_ioctl = perf_ioctl, |
| 487 | .compat_ioctl = perf_ioctl, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 488 | .open = perf_open, |
| 489 | .release = perf_release |
| 490 | }; |
| 491 | |
| 492 | static struct miscdevice perf_dev = { |
| 493 | MISC_DYNAMIC_MINOR, |
| 494 | PA_PERF_DEV, |
| 495 | &perf_fops |
| 496 | }; |
| 497 | |
| 498 | /* |
| 499 | * Initialize the module |
| 500 | */ |
| 501 | static int __init perf_init(void) |
| 502 | { |
| 503 | int ret; |
| 504 | |
| 505 | /* Determine correct processor interface to use */ |
| 506 | bitmask_array = perf_bitmasks; |
| 507 | |
| 508 | if (boot_cpu_data.cpu_type == pcxu || |
| 509 | boot_cpu_data.cpu_type == pcxu_) { |
| 510 | perf_processor_interface = ONYX_INTF; |
| 511 | } else if (boot_cpu_data.cpu_type == pcxw || |
| 512 | boot_cpu_data.cpu_type == pcxw_ || |
| 513 | boot_cpu_data.cpu_type == pcxw2 || |
Kyle McMartin | 2cbd42d | 2007-03-27 16:47:49 -0400 | [diff] [blame] | 514 | boot_cpu_data.cpu_type == mako || |
| 515 | boot_cpu_data.cpu_type == mako2) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 516 | perf_processor_interface = CUDA_INTF; |
| 517 | if (boot_cpu_data.cpu_type == pcxw2 || |
Kyle McMartin | 2cbd42d | 2007-03-27 16:47:49 -0400 | [diff] [blame] | 518 | boot_cpu_data.cpu_type == mako || |
| 519 | boot_cpu_data.cpu_type == mako2) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 520 | bitmask_array = perf_bitmasks_piranha; |
| 521 | } else { |
| 522 | perf_processor_interface = UNKNOWN_INTF; |
| 523 | printk("Performance monitoring counters not supported on this processor\n"); |
| 524 | return -ENODEV; |
| 525 | } |
| 526 | |
| 527 | ret = misc_register(&perf_dev); |
| 528 | if (ret) { |
| 529 | printk(KERN_ERR "Performance monitoring counters: " |
| 530 | "cannot register misc device.\n"); |
| 531 | return ret; |
| 532 | } |
| 533 | |
| 534 | /* Patch the images to match the system */ |
| 535 | perf_patch_images(); |
| 536 | |
| 537 | spin_lock_init(&perf_lock); |
| 538 | |
| 539 | /* TODO: this only lets us access the first cpu.. what to do for SMP? */ |
| 540 | cpu_device = cpu_data[0].dev; |
| 541 | printk("Performance monitoring counters enabled for %s\n", |
| 542 | cpu_data[0].dev->name); |
| 543 | |
| 544 | return 0; |
| 545 | } |
| 546 | |
| 547 | /* |
| 548 | * perf_start_counters(void) |
| 549 | * |
| 550 | * Start the counters. |
| 551 | */ |
| 552 | static void perf_start_counters(void) |
| 553 | { |
| 554 | /* Enable performance monitor counters */ |
| 555 | perf_intrigue_enable_perf_counters(); |
| 556 | } |
| 557 | |
| 558 | /* |
| 559 | * perf_stop_counters |
| 560 | * |
| 561 | * Stop the performance counters and save counts |
| 562 | * in a per_processor array. |
| 563 | */ |
| 564 | static int perf_stop_counters(uint32_t *raddr) |
| 565 | { |
| 566 | uint64_t userbuf[MAX_RDR_WORDS]; |
| 567 | |
| 568 | /* Disable performance counters */ |
| 569 | perf_intrigue_disable_perf_counters(); |
| 570 | |
| 571 | if (perf_processor_interface == ONYX_INTF) { |
| 572 | uint64_t tmp64; |
| 573 | /* |
| 574 | * Read the counters |
| 575 | */ |
| 576 | if (!perf_rdr_read_ubuf(16, userbuf)) |
| 577 | return -13; |
| 578 | |
Simon Arlott | 7022672 | 2007-05-11 20:42:34 +0100 | [diff] [blame] | 579 | /* Counter0 is bits 1398 to 1429 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 580 | tmp64 = (userbuf[21] << 22) & 0x00000000ffc00000; |
| 581 | tmp64 |= (userbuf[22] >> 42) & 0x00000000003fffff; |
| 582 | /* OR sticky0 (bit 1430) to counter0 bit 32 */ |
| 583 | tmp64 |= (userbuf[22] >> 10) & 0x0000000080000000; |
| 584 | raddr[0] = (uint32_t)tmp64; |
| 585 | |
Simon Arlott | 7022672 | 2007-05-11 20:42:34 +0100 | [diff] [blame] | 586 | /* Counter1 is bits 1431 to 1462 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 587 | tmp64 = (userbuf[22] >> 9) & 0x00000000ffffffff; |
| 588 | /* OR sticky1 (bit 1463) to counter1 bit 32 */ |
| 589 | tmp64 |= (userbuf[22] << 23) & 0x0000000080000000; |
| 590 | raddr[1] = (uint32_t)tmp64; |
| 591 | |
Simon Arlott | 7022672 | 2007-05-11 20:42:34 +0100 | [diff] [blame] | 592 | /* Counter2 is bits 1464 to 1495 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 593 | tmp64 = (userbuf[22] << 24) & 0x00000000ff000000; |
| 594 | tmp64 |= (userbuf[23] >> 40) & 0x0000000000ffffff; |
| 595 | /* OR sticky2 (bit 1496) to counter2 bit 32 */ |
| 596 | tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000; |
| 597 | raddr[2] = (uint32_t)tmp64; |
| 598 | |
Simon Arlott | 7022672 | 2007-05-11 20:42:34 +0100 | [diff] [blame] | 599 | /* Counter3 is bits 1497 to 1528 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 600 | tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff; |
| 601 | /* OR sticky3 (bit 1529) to counter3 bit 32 */ |
| 602 | tmp64 |= (userbuf[23] << 25) & 0x0000000080000000; |
| 603 | raddr[3] = (uint32_t)tmp64; |
| 604 | |
| 605 | /* |
| 606 | * Zero out the counters |
| 607 | */ |
| 608 | |
| 609 | /* |
| 610 | * The counters and sticky-bits comprise the last 132 bits |
| 611 | * (1398 - 1529) of RDR16 on a U chip. We'll zero these |
| 612 | * out the easy way: zero out last 10 bits of dword 21, |
| 613 | * all of dword 22 and 58 bits (plus 6 don't care bits) of |
| 614 | * dword 23. |
| 615 | */ |
| 616 | userbuf[21] &= 0xfffffffffffffc00ul; /* 0 to last 10 bits */ |
| 617 | userbuf[22] = 0; |
| 618 | userbuf[23] = 0; |
| 619 | |
| 620 | /* |
Simon Arlott | 7022672 | 2007-05-11 20:42:34 +0100 | [diff] [blame] | 621 | * Write back the zeroed bytes + the image given |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | * the read was destructive. |
| 623 | */ |
| 624 | perf_rdr_write(16, userbuf); |
| 625 | } else { |
| 626 | |
| 627 | /* |
| 628 | * Read RDR-15 which contains the counters and sticky bits |
| 629 | */ |
| 630 | if (!perf_rdr_read_ubuf(15, userbuf)) { |
| 631 | return -13; |
| 632 | } |
| 633 | |
| 634 | /* |
| 635 | * Clear out the counters |
| 636 | */ |
| 637 | perf_rdr_clear(15); |
| 638 | |
| 639 | /* |
| 640 | * Copy the counters |
| 641 | */ |
| 642 | raddr[0] = (uint32_t)((userbuf[0] >> 32) & 0x00000000ffffffffUL); |
| 643 | raddr[1] = (uint32_t)(userbuf[0] & 0x00000000ffffffffUL); |
| 644 | raddr[2] = (uint32_t)((userbuf[1] >> 32) & 0x00000000ffffffffUL); |
| 645 | raddr[3] = (uint32_t)(userbuf[1] & 0x00000000ffffffffUL); |
| 646 | } |
| 647 | |
| 648 | return 0; |
| 649 | } |
| 650 | |
| 651 | /* |
| 652 | * perf_rdr_get_entry |
| 653 | * |
| 654 | * Retrieve a pointer to the description of what this |
| 655 | * RDR contains. |
| 656 | */ |
Helge Deller | cb6fc18 | 2006-01-17 12:40:40 -0700 | [diff] [blame] | 657 | static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 658 | { |
| 659 | if (perf_processor_interface == ONYX_INTF) { |
| 660 | return &perf_rdr_tbl_U[rdr_num]; |
| 661 | } else { |
| 662 | return &perf_rdr_tbl_W[rdr_num]; |
| 663 | } |
| 664 | } |
| 665 | |
| 666 | /* |
| 667 | * perf_rdr_read_ubuf |
| 668 | * |
| 669 | * Read the RDR value into the buffer specified. |
| 670 | */ |
| 671 | static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer) |
| 672 | { |
| 673 | uint64_t data, data_mask = 0; |
| 674 | uint32_t width, xbits, i; |
Helge Deller | cb6fc18 | 2006-01-17 12:40:40 -0700 | [diff] [blame] | 675 | const struct rdr_tbl_ent *tentry; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 676 | |
| 677 | tentry = perf_rdr_get_entry(rdr_num); |
| 678 | if ((width = tentry->width) == 0) |
| 679 | return 0; |
| 680 | |
| 681 | /* Clear out buffer */ |
| 682 | i = tentry->num_words; |
| 683 | while (i--) { |
| 684 | buffer[i] = 0; |
| 685 | } |
| 686 | |
| 687 | /* Check for bits an even number of 64 */ |
| 688 | if ((xbits = width & 0x03f) != 0) { |
| 689 | data_mask = 1; |
| 690 | data_mask <<= (64 - xbits); |
| 691 | data_mask--; |
| 692 | } |
| 693 | |
| 694 | /* Grab all of the data */ |
| 695 | i = tentry->num_words; |
| 696 | while (i--) { |
| 697 | |
| 698 | if (perf_processor_interface == ONYX_INTF) { |
| 699 | data = perf_rdr_shift_in_U(rdr_num, width); |
| 700 | } else { |
| 701 | data = perf_rdr_shift_in_W(rdr_num, width); |
| 702 | } |
| 703 | if (xbits) { |
| 704 | buffer[i] |= (data << (64 - xbits)); |
| 705 | if (i) { |
| 706 | buffer[i-1] |= ((data >> xbits) & data_mask); |
| 707 | } |
| 708 | } else { |
| 709 | buffer[i] = data; |
| 710 | } |
| 711 | } |
| 712 | |
| 713 | return 1; |
| 714 | } |
| 715 | |
| 716 | /* |
| 717 | * perf_rdr_clear |
| 718 | * |
| 719 | * Zero out the given RDR register |
| 720 | */ |
| 721 | static int perf_rdr_clear(uint32_t rdr_num) |
| 722 | { |
Helge Deller | cb6fc18 | 2006-01-17 12:40:40 -0700 | [diff] [blame] | 723 | const struct rdr_tbl_ent *tentry; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 724 | int32_t i; |
| 725 | |
| 726 | tentry = perf_rdr_get_entry(rdr_num); |
| 727 | |
| 728 | if (tentry->width == 0) { |
| 729 | return -1; |
| 730 | } |
| 731 | |
| 732 | i = tentry->num_words; |
| 733 | while (i--) { |
| 734 | if (perf_processor_interface == ONYX_INTF) { |
| 735 | perf_rdr_shift_out_U(rdr_num, 0UL); |
| 736 | } else { |
| 737 | perf_rdr_shift_out_W(rdr_num, 0UL); |
| 738 | } |
| 739 | } |
| 740 | |
| 741 | return 0; |
| 742 | } |
| 743 | |
| 744 | |
| 745 | /* |
| 746 | * perf_write_image |
| 747 | * |
| 748 | * Write the given image out to the processor |
| 749 | */ |
| 750 | static int perf_write_image(uint64_t *memaddr) |
| 751 | { |
| 752 | uint64_t buffer[MAX_RDR_WORDS]; |
| 753 | uint64_t *bptr; |
| 754 | uint32_t dwords; |
Helge Deller | cb6fc18 | 2006-01-17 12:40:40 -0700 | [diff] [blame] | 755 | const uint32_t *intrigue_rdr; |
| 756 | const uint64_t *intrigue_bitmask; |
| 757 | uint64_t tmp64; |
Matthew Wilcox | 53f01bb | 2005-10-21 22:36:40 -0400 | [diff] [blame] | 758 | void __iomem *runway; |
Helge Deller | cb6fc18 | 2006-01-17 12:40:40 -0700 | [diff] [blame] | 759 | const struct rdr_tbl_ent *tentry; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 760 | int i; |
| 761 | |
| 762 | /* Clear out counters */ |
| 763 | if (perf_processor_interface == ONYX_INTF) { |
| 764 | |
| 765 | perf_rdr_clear(16); |
| 766 | |
| 767 | /* Toggle performance monitor */ |
| 768 | perf_intrigue_enable_perf_counters(); |
| 769 | perf_intrigue_disable_perf_counters(); |
| 770 | |
| 771 | intrigue_rdr = perf_rdrs_U; |
| 772 | } else { |
| 773 | perf_rdr_clear(15); |
| 774 | intrigue_rdr = perf_rdrs_W; |
| 775 | } |
| 776 | |
| 777 | /* Write all RDRs */ |
| 778 | while (*intrigue_rdr != -1) { |
| 779 | tentry = perf_rdr_get_entry(*intrigue_rdr); |
| 780 | perf_rdr_read_ubuf(*intrigue_rdr, buffer); |
| 781 | bptr = &buffer[0]; |
| 782 | dwords = tentry->num_words; |
| 783 | if (tentry->write_control) { |
| 784 | intrigue_bitmask = &bitmask_array[tentry->write_control >> 3]; |
| 785 | while (dwords--) { |
| 786 | tmp64 = *intrigue_bitmask & *memaddr++; |
| 787 | tmp64 |= (~(*intrigue_bitmask++)) & *bptr; |
| 788 | *bptr++ = tmp64; |
| 789 | } |
| 790 | } else { |
| 791 | while (dwords--) { |
| 792 | *bptr++ = *memaddr++; |
| 793 | } |
| 794 | } |
| 795 | |
| 796 | perf_rdr_write(*intrigue_rdr, buffer); |
| 797 | intrigue_rdr++; |
| 798 | } |
| 799 | |
| 800 | /* |
| 801 | * Now copy out the Runway stuff which is not in RDRs |
| 802 | */ |
| 803 | |
| 804 | if (cpu_device == NULL) |
| 805 | { |
| 806 | printk(KERN_ERR "write_image: cpu_device not yet initialized!\n"); |
| 807 | return -1; |
| 808 | } |
| 809 | |
Helge Deller | 5076c15 | 2006-03-27 12:52:15 -0700 | [diff] [blame] | 810 | runway = ioremap_nocache(cpu_device->hpa.start, 4096); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 811 | |
| 812 | /* Merge intrigue bits into Runway STATUS 0 */ |
Matthew Wilcox | 53f01bb | 2005-10-21 22:36:40 -0400 | [diff] [blame] | 813 | tmp64 = __raw_readq(runway + RUNWAY_STATUS) & 0xffecfffffffffffful; |
| 814 | __raw_writeq(tmp64 | (*memaddr++ & 0x0013000000000000ul), |
| 815 | runway + RUNWAY_STATUS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 816 | |
| 817 | /* Write RUNWAY DEBUG registers */ |
| 818 | for (i = 0; i < 8; i++) { |
Matthew Wilcox | 53f01bb | 2005-10-21 22:36:40 -0400 | [diff] [blame] | 819 | __raw_writeq(*memaddr++, runway + RUNWAY_DEBUG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 820 | } |
| 821 | |
| 822 | return 0; |
| 823 | } |
| 824 | |
| 825 | /* |
| 826 | * perf_rdr_write |
| 827 | * |
| 828 | * Write the given RDR register with the contents |
| 829 | * of the given buffer. |
| 830 | */ |
| 831 | static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer) |
| 832 | { |
Helge Deller | cb6fc18 | 2006-01-17 12:40:40 -0700 | [diff] [blame] | 833 | const struct rdr_tbl_ent *tentry; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 834 | int32_t i; |
| 835 | |
| 836 | printk("perf_rdr_write\n"); |
| 837 | tentry = perf_rdr_get_entry(rdr_num); |
| 838 | if (tentry->width == 0) { return; } |
| 839 | |
| 840 | i = tentry->num_words; |
| 841 | while (i--) { |
| 842 | if (perf_processor_interface == ONYX_INTF) { |
| 843 | perf_rdr_shift_out_U(rdr_num, buffer[i]); |
| 844 | } else { |
| 845 | perf_rdr_shift_out_W(rdr_num, buffer[i]); |
| 846 | } |
| 847 | } |
| 848 | printk("perf_rdr_write done\n"); |
| 849 | } |
| 850 | |
| 851 | module_init(perf_init); |