James Liao | c1e81a3 | 2015-04-23 10:35:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014 MediaTek Inc. |
| 3 | * Author: James Liao <jamesjj.liao@mediatek.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
Stephen Boyd | c726639 | 2015-06-19 15:00:46 -0700 | [diff] [blame] | 15 | #include <linux/clk.h> |
James Liao | c1e81a3 | 2015-04-23 10:35:42 +0200 | [diff] [blame] | 16 | #include <linux/of.h> |
| 17 | #include <linux/of_address.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/mfd/syscon.h> |
| 20 | |
| 21 | #include "clk-mtk.h" |
| 22 | #include "clk-gate.h" |
| 23 | |
| 24 | #include <dt-bindings/clock/mt8173-clk.h> |
| 25 | |
| 26 | static DEFINE_SPINLOCK(mt8173_clk_lock); |
| 27 | |
| 28 | static const struct mtk_fixed_factor root_clk_alias[] __initconst = { |
| 29 | FACTOR(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk_null", 1, 1), |
| 30 | FACTOR(CLK_TOP_DPI, "dpi_ck", "clk_null", 1, 1), |
| 31 | FACTOR(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk_null", 1, 1), |
| 32 | FACTOR(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts", "clk_null", 1, 1), |
| 33 | }; |
| 34 | |
| 35 | static const struct mtk_fixed_factor top_divs[] __initconst = { |
| 36 | FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2), |
| 37 | FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3), |
| 38 | |
| 39 | FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2), |
| 40 | FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3), |
| 41 | FACTOR(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5), |
| 42 | FACTOR(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7), |
| 43 | |
| 44 | FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4), |
| 45 | FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3), |
| 46 | |
| 47 | FACTOR(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2), |
| 48 | FACTOR(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3), |
| 49 | FACTOR(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5), |
| 50 | FACTOR(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7), |
| 51 | FACTOR(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26), |
| 52 | |
| 53 | FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1), |
| 54 | FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793), |
| 55 | FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1), |
| 56 | |
| 57 | FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2), |
| 58 | FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3), |
| 59 | |
| 60 | FACTOR(CLK_TOP_ARMCA7PLL_D2, "armca7pll_d2", "armca7pll_754m", 1, 1), |
| 61 | FACTOR(CLK_TOP_ARMCA7PLL_D3, "armca7pll_d3", "armca7pll_502m", 1, 1), |
| 62 | |
| 63 | FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), |
| 64 | FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), |
| 65 | |
| 66 | FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1), |
| 67 | FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2), |
| 68 | FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4), |
| 69 | FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8), |
| 70 | FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16", "clkph_mck_o", 1, 16), |
| 71 | |
| 72 | FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), |
| 73 | FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), |
| 74 | FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), |
| 75 | |
| 76 | FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), |
| 77 | FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), |
| 78 | |
| 79 | FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), |
| 80 | FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), |
| 81 | FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), |
| 82 | FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1), |
| 83 | FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2), |
| 84 | FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4), |
| 85 | |
| 86 | FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1), |
| 87 | FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2), |
| 88 | FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4), |
| 89 | FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8), |
| 90 | FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16), |
| 91 | FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1), |
| 92 | FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2), |
| 93 | FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4), |
| 94 | FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1), |
| 95 | FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2), |
| 96 | FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4), |
| 97 | FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1), |
| 98 | FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2), |
| 99 | FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4), |
| 100 | |
| 101 | FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1), |
| 102 | FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2), |
| 103 | FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4), |
| 104 | FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8), |
| 105 | FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16), |
| 106 | |
| 107 | FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1), |
| 108 | FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2), |
| 109 | FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4), |
| 110 | FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8), |
| 111 | FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1), |
| 112 | FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2), |
| 113 | FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4), |
| 114 | FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8), |
| 115 | FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1), |
| 116 | FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2), |
| 117 | FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4), |
| 118 | FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8), |
| 119 | FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1), |
| 120 | FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1), |
| 121 | FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2), |
| 122 | |
| 123 | FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3), |
| 124 | FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4), |
| 125 | |
| 126 | FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1), |
| 127 | FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll", 1, 2), |
| 128 | FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4), |
| 129 | }; |
| 130 | |
| 131 | static const char * const axi_parents[] __initconst = { |
| 132 | "clk26m", |
| 133 | "syspll1_d2", |
| 134 | "syspll_d5", |
| 135 | "syspll1_d4", |
| 136 | "univpll_d5", |
| 137 | "univpll2_d2", |
| 138 | "dmpll_d2", |
| 139 | "dmpll_d4" |
| 140 | }; |
| 141 | |
| 142 | static const char * const mem_parents[] __initconst = { |
| 143 | "clk26m", |
| 144 | "dmpll_ck" |
| 145 | }; |
| 146 | |
| 147 | static const char * const ddrphycfg_parents[] __initconst = { |
| 148 | "clk26m", |
| 149 | "syspll1_d8" |
| 150 | }; |
| 151 | |
| 152 | static const char * const mm_parents[] __initconst = { |
| 153 | "clk26m", |
| 154 | "vencpll_d2", |
| 155 | "main_h364m", |
| 156 | "syspll1_d2", |
| 157 | "syspll_d5", |
| 158 | "syspll1_d4", |
| 159 | "univpll1_d2", |
| 160 | "univpll2_d2", |
| 161 | "dmpll_d2" |
| 162 | }; |
| 163 | |
| 164 | static const char * const pwm_parents[] __initconst = { |
| 165 | "clk26m", |
| 166 | "univpll2_d4", |
| 167 | "univpll3_d2", |
| 168 | "univpll1_d4" |
| 169 | }; |
| 170 | |
| 171 | static const char * const vdec_parents[] __initconst = { |
| 172 | "clk26m", |
| 173 | "vcodecpll_ck", |
| 174 | "tvdpll_445p5m", |
| 175 | "univpll_d3", |
| 176 | "vencpll_d2", |
| 177 | "syspll_d3", |
| 178 | "univpll1_d2", |
| 179 | "mmpll_d2", |
| 180 | "dmpll_d2", |
| 181 | "dmpll_d4" |
| 182 | }; |
| 183 | |
| 184 | static const char * const venc_parents[] __initconst = { |
| 185 | "clk26m", |
| 186 | "vcodecpll_ck", |
| 187 | "tvdpll_445p5m", |
| 188 | "univpll_d3", |
| 189 | "vencpll_d2", |
| 190 | "syspll_d3", |
| 191 | "univpll1_d2", |
| 192 | "univpll2_d2", |
| 193 | "dmpll_d2", |
| 194 | "dmpll_d4" |
| 195 | }; |
| 196 | |
| 197 | static const char * const mfg_parents[] __initconst = { |
| 198 | "clk26m", |
| 199 | "mmpll_ck", |
| 200 | "dmpll_ck", |
| 201 | "clk26m", |
| 202 | "clk26m", |
| 203 | "clk26m", |
| 204 | "clk26m", |
| 205 | "clk26m", |
| 206 | "clk26m", |
| 207 | "syspll_d3", |
| 208 | "syspll1_d2", |
| 209 | "syspll_d5", |
| 210 | "univpll_d3", |
| 211 | "univpll1_d2", |
| 212 | "univpll_d5", |
| 213 | "univpll2_d2" |
| 214 | }; |
| 215 | |
| 216 | static const char * const camtg_parents[] __initconst = { |
| 217 | "clk26m", |
| 218 | "univpll_d26", |
| 219 | "univpll2_d2", |
| 220 | "syspll3_d2", |
| 221 | "syspll3_d4", |
| 222 | "univpll1_d4" |
| 223 | }; |
| 224 | |
| 225 | static const char * const uart_parents[] __initconst = { |
| 226 | "clk26m", |
| 227 | "univpll2_d8" |
| 228 | }; |
| 229 | |
| 230 | static const char * const spi_parents[] __initconst = { |
| 231 | "clk26m", |
| 232 | "syspll3_d2", |
| 233 | "syspll1_d4", |
| 234 | "syspll4_d2", |
| 235 | "univpll3_d2", |
| 236 | "univpll2_d4", |
| 237 | "univpll1_d8" |
| 238 | }; |
| 239 | |
| 240 | static const char * const usb20_parents[] __initconst = { |
| 241 | "clk26m", |
| 242 | "univpll1_d8", |
| 243 | "univpll3_d4" |
| 244 | }; |
| 245 | |
| 246 | static const char * const usb30_parents[] __initconst = { |
| 247 | "clk26m", |
| 248 | "univpll3_d2", |
| 249 | "usb_syspll_125m", |
| 250 | "univpll2_d4" |
| 251 | }; |
| 252 | |
| 253 | static const char * const msdc50_0_h_parents[] __initconst = { |
| 254 | "clk26m", |
| 255 | "syspll1_d2", |
| 256 | "syspll2_d2", |
| 257 | "syspll4_d2", |
| 258 | "univpll_d5", |
| 259 | "univpll1_d4" |
| 260 | }; |
| 261 | |
| 262 | static const char * const msdc50_0_parents[] __initconst = { |
| 263 | "clk26m", |
| 264 | "msdcpll_ck", |
| 265 | "msdcpll_d2", |
| 266 | "univpll1_d4", |
| 267 | "syspll2_d2", |
| 268 | "syspll_d7", |
| 269 | "msdcpll_d4", |
| 270 | "vencpll_d4", |
| 271 | "tvdpll_ck", |
| 272 | "univpll_d2", |
| 273 | "univpll1_d2", |
| 274 | "mmpll_ck", |
| 275 | "msdcpll2_ck", |
| 276 | "msdcpll2_d2", |
| 277 | "msdcpll2_d4" |
| 278 | }; |
| 279 | |
| 280 | static const char * const msdc30_1_parents[] __initconst = { |
| 281 | "clk26m", |
| 282 | "univpll2_d2", |
| 283 | "msdcpll_d4", |
| 284 | "univpll1_d4", |
| 285 | "syspll2_d2", |
| 286 | "syspll_d7", |
| 287 | "univpll_d7", |
| 288 | "vencpll_d4" |
| 289 | }; |
| 290 | |
| 291 | static const char * const msdc30_2_parents[] __initconst = { |
| 292 | "clk26m", |
| 293 | "univpll2_d2", |
| 294 | "msdcpll_d4", |
| 295 | "univpll1_d4", |
| 296 | "syspll2_d2", |
| 297 | "syspll_d7", |
| 298 | "univpll_d7", |
| 299 | "vencpll_d2" |
| 300 | }; |
| 301 | |
| 302 | static const char * const msdc30_3_parents[] __initconst = { |
| 303 | "clk26m", |
| 304 | "msdcpll2_ck", |
| 305 | "msdcpll2_d2", |
| 306 | "univpll2_d2", |
| 307 | "msdcpll2_d4", |
| 308 | "msdcpll_d4", |
| 309 | "univpll1_d4", |
| 310 | "syspll2_d2", |
| 311 | "syspll_d7", |
| 312 | "univpll_d7", |
| 313 | "vencpll_d4", |
| 314 | "msdcpll_ck", |
| 315 | "msdcpll_d2", |
| 316 | "msdcpll_d4" |
| 317 | }; |
| 318 | |
| 319 | static const char * const audio_parents[] __initconst = { |
| 320 | "clk26m", |
| 321 | "syspll3_d4", |
| 322 | "syspll4_d4", |
| 323 | "syspll1_d16" |
| 324 | }; |
| 325 | |
| 326 | static const char * const aud_intbus_parents[] __initconst = { |
| 327 | "clk26m", |
| 328 | "syspll1_d4", |
| 329 | "syspll4_d2", |
| 330 | "univpll3_d2", |
| 331 | "univpll2_d8", |
| 332 | "dmpll_d4", |
| 333 | "dmpll_d8" |
| 334 | }; |
| 335 | |
| 336 | static const char * const pmicspi_parents[] __initconst = { |
| 337 | "clk26m", |
| 338 | "syspll1_d8", |
| 339 | "syspll3_d4", |
| 340 | "syspll1_d16", |
| 341 | "univpll3_d4", |
| 342 | "univpll_d26", |
| 343 | "dmpll_d8", |
| 344 | "dmpll_d16" |
| 345 | }; |
| 346 | |
| 347 | static const char * const scp_parents[] __initconst = { |
| 348 | "clk26m", |
| 349 | "syspll1_d2", |
| 350 | "univpll_d5", |
| 351 | "syspll_d5", |
| 352 | "dmpll_d2", |
| 353 | "dmpll_d4" |
| 354 | }; |
| 355 | |
| 356 | static const char * const atb_parents[] __initconst = { |
| 357 | "clk26m", |
| 358 | "syspll1_d2", |
| 359 | "univpll_d5", |
| 360 | "dmpll_d2" |
| 361 | }; |
| 362 | |
| 363 | static const char * const venc_lt_parents[] __initconst = { |
| 364 | "clk26m", |
| 365 | "univpll_d3", |
| 366 | "vcodecpll_ck", |
| 367 | "tvdpll_445p5m", |
| 368 | "vencpll_d2", |
| 369 | "syspll_d3", |
| 370 | "univpll1_d2", |
| 371 | "univpll2_d2", |
| 372 | "syspll1_d2", |
| 373 | "univpll_d5", |
| 374 | "vcodecpll_370p5", |
| 375 | "dmpll_ck" |
| 376 | }; |
| 377 | |
| 378 | static const char * const dpi0_parents[] __initconst = { |
| 379 | "clk26m", |
| 380 | "tvdpll_d2", |
| 381 | "tvdpll_d4", |
| 382 | "clk26m", |
| 383 | "clk26m", |
| 384 | "tvdpll_d8", |
| 385 | "tvdpll_d16" |
| 386 | }; |
| 387 | |
| 388 | static const char * const irda_parents[] __initconst = { |
| 389 | "clk26m", |
| 390 | "univpll2_d4", |
| 391 | "syspll2_d4" |
| 392 | }; |
| 393 | |
| 394 | static const char * const cci400_parents[] __initconst = { |
| 395 | "clk26m", |
| 396 | "vencpll_ck", |
| 397 | "armca7pll_754m", |
| 398 | "armca7pll_502m", |
| 399 | "univpll_d2", |
| 400 | "syspll_d2", |
| 401 | "msdcpll_ck", |
| 402 | "dmpll_ck" |
| 403 | }; |
| 404 | |
| 405 | static const char * const aud_1_parents[] __initconst = { |
| 406 | "clk26m", |
| 407 | "apll1_ck", |
| 408 | "univpll2_d4", |
| 409 | "univpll2_d8" |
| 410 | }; |
| 411 | |
| 412 | static const char * const aud_2_parents[] __initconst = { |
| 413 | "clk26m", |
| 414 | "apll2_ck", |
| 415 | "univpll2_d4", |
| 416 | "univpll2_d8" |
| 417 | }; |
| 418 | |
| 419 | static const char * const mem_mfg_in_parents[] __initconst = { |
| 420 | "clk26m", |
| 421 | "mmpll_ck", |
| 422 | "dmpll_ck", |
| 423 | "clk26m" |
| 424 | }; |
| 425 | |
| 426 | static const char * const axi_mfg_in_parents[] __initconst = { |
| 427 | "clk26m", |
| 428 | "axi_sel", |
| 429 | "dmpll_d2" |
| 430 | }; |
| 431 | |
| 432 | static const char * const scam_parents[] __initconst = { |
| 433 | "clk26m", |
| 434 | "syspll3_d2", |
| 435 | "univpll2_d4", |
| 436 | "dmpll_d4" |
| 437 | }; |
| 438 | |
| 439 | static const char * const spinfi_ifr_parents[] __initconst = { |
| 440 | "clk26m", |
| 441 | "univpll2_d8", |
| 442 | "univpll3_d4", |
| 443 | "syspll4_d2", |
| 444 | "univpll2_d4", |
| 445 | "univpll3_d2", |
| 446 | "syspll1_d4", |
| 447 | "univpll1_d4" |
| 448 | }; |
| 449 | |
| 450 | static const char * const hdmi_parents[] __initconst = { |
| 451 | "clk26m", |
| 452 | "hdmitx_dig_cts", |
| 453 | "hdmitxpll_d2", |
| 454 | "hdmitxpll_d3" |
| 455 | }; |
| 456 | |
| 457 | static const char * const dpilvds_parents[] __initconst = { |
| 458 | "clk26m", |
| 459 | "lvdspll", |
| 460 | "lvdspll_d2", |
| 461 | "lvdspll_d4", |
| 462 | "lvdspll_d8", |
| 463 | "fpc_ck" |
| 464 | }; |
| 465 | |
| 466 | static const char * const msdc50_2_h_parents[] __initconst = { |
| 467 | "clk26m", |
| 468 | "syspll1_d2", |
| 469 | "syspll2_d2", |
| 470 | "syspll4_d2", |
| 471 | "univpll_d5", |
| 472 | "univpll1_d4" |
| 473 | }; |
| 474 | |
| 475 | static const char * const hdcp_parents[] __initconst = { |
| 476 | "clk26m", |
| 477 | "syspll4_d2", |
| 478 | "syspll3_d4", |
| 479 | "univpll2_d4" |
| 480 | }; |
| 481 | |
| 482 | static const char * const hdcp_24m_parents[] __initconst = { |
| 483 | "clk26m", |
| 484 | "univpll_d26", |
| 485 | "univpll_d52", |
| 486 | "univpll2_d8" |
| 487 | }; |
| 488 | |
| 489 | static const char * const rtc_parents[] __initconst = { |
| 490 | "clkrtc_int", |
| 491 | "clkrtc_ext", |
| 492 | "clk26m", |
| 493 | "univpll3_d8" |
| 494 | }; |
| 495 | |
| 496 | static const char * const i2s0_m_ck_parents[] __initconst = { |
| 497 | "apll1_div1", |
| 498 | "apll2_div1" |
| 499 | }; |
| 500 | |
| 501 | static const char * const i2s1_m_ck_parents[] __initconst = { |
| 502 | "apll1_div2", |
| 503 | "apll2_div2" |
| 504 | }; |
| 505 | |
| 506 | static const char * const i2s2_m_ck_parents[] __initconst = { |
| 507 | "apll1_div3", |
| 508 | "apll2_div3" |
| 509 | }; |
| 510 | |
| 511 | static const char * const i2s3_m_ck_parents[] __initconst = { |
| 512 | "apll1_div4", |
| 513 | "apll2_div4" |
| 514 | }; |
| 515 | |
| 516 | static const char * const i2s3_b_ck_parents[] __initconst = { |
| 517 | "apll1_div5", |
| 518 | "apll2_div5" |
| 519 | }; |
| 520 | |
| 521 | static const struct mtk_composite top_muxes[] __initconst = { |
| 522 | /* CLK_CFG_0 */ |
| 523 | MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3), |
| 524 | MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1), |
| 525 | MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23), |
| 526 | MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31), |
| 527 | /* CLK_CFG_1 */ |
| 528 | MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7), |
| 529 | MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15), |
| 530 | MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23), |
| 531 | MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31), |
| 532 | /* CLK_CFG_2 */ |
| 533 | MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7), |
| 534 | MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15), |
| 535 | MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23), |
| 536 | MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31), |
| 537 | /* CLK_CFG_3 */ |
| 538 | MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7), |
| 539 | MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 0x0070, 8, 3, 15), |
| 540 | MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x0070, 16, 4, 23), |
| 541 | MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x0070, 24, 3, 31), |
| 542 | /* CLK_CFG_4 */ |
| 543 | MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x0080, 0, 3, 7), |
| 544 | MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 0x0080, 8, 4, 15), |
| 545 | MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0080, 16, 2, 23), |
| 546 | MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x0080, 24, 3, 31), |
| 547 | /* CLK_CFG_5 */ |
| 548 | MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0090, 0, 3, 7 /* 7:5 */), |
| 549 | MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15), |
| 550 | MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23), |
| 551 | MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31), |
| 552 | /* CLK_CFG_6 */ |
| 553 | MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7), |
| 554 | MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15), |
| 555 | MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23), |
| 556 | MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31), |
| 557 | /* CLK_CFG_7 */ |
| 558 | MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7), |
| 559 | MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel", mem_mfg_in_parents, 0x00b0, 8, 2, 15), |
| 560 | MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents, 0x00b0, 16, 2, 23), |
| 561 | MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31), |
| 562 | /* CLK_CFG_12 */ |
| 563 | MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents, 0x00c0, 0, 3, 7), |
| 564 | MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15), |
| 565 | MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0, 24, 3, 31), |
| 566 | /* CLK_CFG_13 */ |
| 567 | MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7), |
| 568 | MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15), |
| 569 | MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 0x00d0, 16, 2, 23), |
| 570 | MUX(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2), |
| 571 | |
| 572 | DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24), |
| 573 | DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0), |
| 574 | DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2", "aud_1_sel", 0x12c, 10, 0x124, 8, 8), |
| 575 | DIV_GATE(CLK_TOP_APLL1_DIV3, "apll1_div3", "aud_1_sel", 0x12c, 11, 0x124, 8, 16), |
| 576 | DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24), |
| 577 | DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5", "apll1_div4", 0x12c, 13, 0x12c, 4, 0), |
| 578 | |
| 579 | DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28), |
| 580 | DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0), |
| 581 | DIV_GATE(CLK_TOP_APLL2_DIV2, "apll2_div2", "aud_2_sel", 0x12c, 18, 0x128, 8, 8), |
| 582 | DIV_GATE(CLK_TOP_APLL2_DIV3, "apll2_div3", "aud_2_sel", 0x12c, 19, 0x128, 8, 16), |
| 583 | DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4", "aud_2_sel", 0x12c, 20, 0x128, 8, 24), |
| 584 | DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c, 4, 4), |
| 585 | |
| 586 | MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x120, 4, 1), |
| 587 | MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 0x120, 5, 1), |
| 588 | MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 0x120, 6, 1), |
| 589 | MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 0x120, 7, 1), |
| 590 | MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1), |
| 591 | }; |
| 592 | |
| 593 | static const struct mtk_gate_regs infra_cg_regs = { |
| 594 | .set_ofs = 0x0040, |
| 595 | .clr_ofs = 0x0044, |
| 596 | .sta_ofs = 0x0048, |
| 597 | }; |
| 598 | |
| 599 | #define GATE_ICG(_id, _name, _parent, _shift) { \ |
| 600 | .id = _id, \ |
| 601 | .name = _name, \ |
| 602 | .parent_name = _parent, \ |
| 603 | .regs = &infra_cg_regs, \ |
| 604 | .shift = _shift, \ |
| 605 | .ops = &mtk_clk_gate_ops_setclr, \ |
| 606 | } |
| 607 | |
| 608 | static const struct mtk_gate infra_clks[] __initconst = { |
| 609 | GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), |
| 610 | GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1), |
| 611 | GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5), |
| 612 | GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6), |
| 613 | GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7), |
| 614 | GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8), |
| 615 | GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "clk_null", 15), |
| 616 | GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16), |
| 617 | GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18), |
| 618 | GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22), |
| 619 | GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23), |
| 620 | }; |
| 621 | |
| 622 | static const struct mtk_gate_regs peri0_cg_regs = { |
| 623 | .set_ofs = 0x0008, |
| 624 | .clr_ofs = 0x0010, |
| 625 | .sta_ofs = 0x0018, |
| 626 | }; |
| 627 | |
| 628 | static const struct mtk_gate_regs peri1_cg_regs = { |
| 629 | .set_ofs = 0x000c, |
| 630 | .clr_ofs = 0x0014, |
| 631 | .sta_ofs = 0x001c, |
| 632 | }; |
| 633 | |
| 634 | #define GATE_PERI0(_id, _name, _parent, _shift) { \ |
| 635 | .id = _id, \ |
| 636 | .name = _name, \ |
| 637 | .parent_name = _parent, \ |
| 638 | .regs = &peri0_cg_regs, \ |
| 639 | .shift = _shift, \ |
| 640 | .ops = &mtk_clk_gate_ops_setclr, \ |
| 641 | } |
| 642 | |
| 643 | #define GATE_PERI1(_id, _name, _parent, _shift) { \ |
| 644 | .id = _id, \ |
| 645 | .name = _name, \ |
| 646 | .parent_name = _parent, \ |
| 647 | .regs = &peri1_cg_regs, \ |
| 648 | .shift = _shift, \ |
| 649 | .ops = &mtk_clk_gate_ops_setclr, \ |
| 650 | } |
| 651 | |
| 652 | static const struct mtk_gate peri_gates[] __initconst = { |
| 653 | /* PERI0 */ |
| 654 | GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0), |
| 655 | GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1), |
| 656 | GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2), |
| 657 | GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3), |
| 658 | GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4), |
| 659 | GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5), |
| 660 | GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6), |
| 661 | GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7), |
| 662 | GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8), |
| 663 | GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9), |
| 664 | GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10), |
| 665 | GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11), |
| 666 | GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12), |
| 667 | GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13), |
| 668 | GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14), |
| 669 | GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15), |
| 670 | GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16), |
| 671 | GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17), |
| 672 | GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18), |
| 673 | GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19), |
| 674 | GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20), |
| 675 | GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21), |
| 676 | GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22), |
| 677 | GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23), |
| 678 | GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24), |
| 679 | GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25), |
| 680 | GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26), |
| 681 | GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27), |
| 682 | GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28), |
| 683 | GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29), |
| 684 | GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30), |
| 685 | GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31), |
| 686 | /* PERI1 */ |
| 687 | GATE_PERI1(CLK_PERI_SPI, "peri_spi", "spi_sel", 0), |
| 688 | GATE_PERI1(CLK_PERI_IRRX, "peri_irrx", "spi_sel", 1), |
| 689 | GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2), |
| 690 | }; |
| 691 | |
| 692 | static const char * const uart_ck_sel_parents[] __initconst = { |
| 693 | "clk26m", |
| 694 | "uart_sel", |
| 695 | }; |
| 696 | |
| 697 | static const struct mtk_composite peri_clks[] __initconst = { |
| 698 | MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1), |
| 699 | MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1), |
| 700 | MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1), |
| 701 | MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), |
| 702 | }; |
| 703 | |
Sascha Hauer | 7b2a463 | 2015-06-30 10:58:44 +0800 | [diff] [blame] | 704 | static struct clk_onecell_data *mt8173_top_clk_data __initdata; |
| 705 | static struct clk_onecell_data *mt8173_pll_clk_data __initdata; |
| 706 | |
| 707 | static void __init mtk_clk_enable_critical(void) |
| 708 | { |
| 709 | if (!mt8173_top_clk_data || !mt8173_pll_clk_data) |
| 710 | return; |
| 711 | |
| 712 | clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA15PLL]); |
| 713 | clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA7PLL]); |
| 714 | clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_MEM_SEL]); |
| 715 | clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); |
| 716 | clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_CCI400_SEL]); |
| 717 | clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_RTC_SEL]); |
| 718 | } |
| 719 | |
James Liao | c1e81a3 | 2015-04-23 10:35:42 +0200 | [diff] [blame] | 720 | static void __init mtk_topckgen_init(struct device_node *node) |
| 721 | { |
| 722 | struct clk_onecell_data *clk_data; |
| 723 | void __iomem *base; |
| 724 | int r; |
| 725 | |
| 726 | base = of_iomap(node, 0); |
| 727 | if (!base) { |
| 728 | pr_err("%s(): ioremap failed\n", __func__); |
| 729 | return; |
| 730 | } |
| 731 | |
Sascha Hauer | 7b2a463 | 2015-06-30 10:58:44 +0800 | [diff] [blame] | 732 | mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); |
James Liao | c1e81a3 | 2015-04-23 10:35:42 +0200 | [diff] [blame] | 733 | |
| 734 | mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data); |
| 735 | mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); |
| 736 | mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, |
| 737 | &mt8173_clk_lock, clk_data); |
| 738 | |
James Liao | c1e81a3 | 2015-04-23 10:35:42 +0200 | [diff] [blame] | 739 | r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| 740 | if (r) |
| 741 | pr_err("%s(): could not register clock provider: %d\n", |
| 742 | __func__, r); |
Sascha Hauer | 7b2a463 | 2015-06-30 10:58:44 +0800 | [diff] [blame] | 743 | |
| 744 | mtk_clk_enable_critical(); |
James Liao | c1e81a3 | 2015-04-23 10:35:42 +0200 | [diff] [blame] | 745 | } |
| 746 | CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init); |
| 747 | |
| 748 | static void __init mtk_infrasys_init(struct device_node *node) |
| 749 | { |
| 750 | struct clk_onecell_data *clk_data; |
| 751 | int r; |
| 752 | |
| 753 | clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); |
| 754 | |
| 755 | mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), |
| 756 | clk_data); |
| 757 | |
| 758 | r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| 759 | if (r) |
| 760 | pr_err("%s(): could not register clock provider: %d\n", |
| 761 | __func__, r); |
| 762 | |
| 763 | mtk_register_reset_controller(node, 2, 0x30); |
| 764 | } |
| 765 | CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init); |
| 766 | |
| 767 | static void __init mtk_pericfg_init(struct device_node *node) |
| 768 | { |
| 769 | struct clk_onecell_data *clk_data; |
| 770 | int r; |
| 771 | void __iomem *base; |
| 772 | |
| 773 | base = of_iomap(node, 0); |
| 774 | if (!base) { |
| 775 | pr_err("%s(): ioremap failed\n", __func__); |
| 776 | return; |
| 777 | } |
| 778 | |
| 779 | clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); |
| 780 | |
| 781 | mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), |
| 782 | clk_data); |
| 783 | mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, |
| 784 | &mt8173_clk_lock, clk_data); |
| 785 | |
| 786 | r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| 787 | if (r) |
| 788 | pr_err("%s(): could not register clock provider: %d\n", |
| 789 | __func__, r); |
| 790 | |
| 791 | mtk_register_reset_controller(node, 2, 0); |
| 792 | } |
| 793 | CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init); |
| 794 | |
| 795 | #define MT8173_PLL_FMAX (3000UL * MHZ) |
| 796 | |
| 797 | #define CON0_MT8173_RST_BAR BIT(24) |
| 798 | |
James Liao | 75ce0cd | 2015-07-10 16:39:34 +0800 | [diff] [blame] | 799 | #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ |
| 800 | _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ |
| 801 | _pcw_shift, _div_table) { \ |
James Liao | c1e81a3 | 2015-04-23 10:35:42 +0200 | [diff] [blame] | 802 | .id = _id, \ |
| 803 | .name = _name, \ |
| 804 | .reg = _reg, \ |
| 805 | .pwr_reg = _pwr_reg, \ |
| 806 | .en_mask = _en_mask, \ |
| 807 | .flags = _flags, \ |
| 808 | .rst_bar_mask = CON0_MT8173_RST_BAR, \ |
| 809 | .fmax = MT8173_PLL_FMAX, \ |
| 810 | .pcwbits = _pcwbits, \ |
| 811 | .pd_reg = _pd_reg, \ |
| 812 | .pd_shift = _pd_shift, \ |
| 813 | .tuner_reg = _tuner_reg, \ |
| 814 | .pcw_reg = _pcw_reg, \ |
| 815 | .pcw_shift = _pcw_shift, \ |
James Liao | 75ce0cd | 2015-07-10 16:39:34 +0800 | [diff] [blame] | 816 | .div_table = _div_table, \ |
James Liao | c1e81a3 | 2015-04-23 10:35:42 +0200 | [diff] [blame] | 817 | } |
| 818 | |
James Liao | 75ce0cd | 2015-07-10 16:39:34 +0800 | [diff] [blame] | 819 | #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ |
| 820 | _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ |
| 821 | _pcw_shift) \ |
| 822 | PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ |
| 823 | _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ |
| 824 | NULL) |
| 825 | |
| 826 | static const struct mtk_pll_div_table mmpll_div_table[] = { |
| 827 | { .div = 0, .freq = MT8173_PLL_FMAX }, |
| 828 | { .div = 1, .freq = 1000000000 }, |
| 829 | { .div = 2, .freq = 702000000 }, |
| 830 | { .div = 3, .freq = 253500000 }, |
| 831 | { .div = 4, .freq = 126750000 }, |
| 832 | { } /* sentinel */ |
| 833 | }; |
| 834 | |
James Liao | c1e81a3 | 2015-04-23 10:35:42 +0200 | [diff] [blame] | 835 | static const struct mtk_pll_data plls[] = { |
| 836 | PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0), |
| 837 | PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0), |
| 838 | PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0), |
| 839 | PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14), |
James Liao | 75ce0cd | 2015-07-10 16:39:34 +0800 | [diff] [blame] | 840 | PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table), |
James Liao | c1e81a3 | 2015-04-23 10:35:42 +0200 | [diff] [blame] | 841 | PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0), |
| 842 | PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0), |
| 843 | PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0), |
| 844 | PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000001, 0, 21, 0x280, 4, 0x0, 0x284, 0), |
| 845 | PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000001, 0, 21, 0x290, 4, 0x0, 0x294, 0), |
| 846 | PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0x00000001, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0), |
| 847 | PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0x00000001, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0), |
| 848 | PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0x00000001, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0), |
| 849 | PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0x00000001, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0), |
| 850 | }; |
| 851 | |
| 852 | static void __init mtk_apmixedsys_init(struct device_node *node) |
| 853 | { |
| 854 | struct clk_onecell_data *clk_data; |
| 855 | |
Sascha Hauer | 7b2a463 | 2015-06-30 10:58:44 +0800 | [diff] [blame] | 856 | mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); |
James Liao | c1e81a3 | 2015-04-23 10:35:42 +0200 | [diff] [blame] | 857 | if (!clk_data) |
| 858 | return; |
| 859 | |
| 860 | mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); |
| 861 | |
Sascha Hauer | 7b2a463 | 2015-06-30 10:58:44 +0800 | [diff] [blame] | 862 | mtk_clk_enable_critical(); |
James Liao | c1e81a3 | 2015-04-23 10:35:42 +0200 | [diff] [blame] | 863 | } |
| 864 | CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys", |
| 865 | mtk_apmixedsys_init); |