Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | */ |
Arkadiusz Hiler | 8c4f24f | 2016-11-25 18:59:33 +0100 | [diff] [blame] | 24 | #ifndef _INTEL_UC_H_ |
| 25 | #define _INTEL_UC_H_ |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 26 | |
| 27 | #include "intel_guc_fwif.h" |
| 28 | #include "i915_guc_reg.h" |
Dave Gordon | 0b63bb1 | 2016-06-20 15:18:07 +0100 | [diff] [blame] | 29 | #include "intel_ringbuffer.h" |
Michal Wajdeczko | f8a58d6 | 2017-05-26 11:13:25 +0000 | [diff] [blame] | 30 | #include "intel_guc_ct.h" |
Chris Wilson | 4741da9 | 2016-12-24 19:31:46 +0000 | [diff] [blame] | 31 | #include "i915_vma.h" |
| 32 | |
Chris Wilson | e73bdd2 | 2016-04-13 17:35:01 +0100 | [diff] [blame] | 33 | struct drm_i915_gem_request; |
| 34 | |
Dave Gordon | 86e06cc | 2016-04-19 16:08:36 +0100 | [diff] [blame] | 35 | /* |
| 36 | * This structure primarily describes the GEM object shared with the GuC. |
Oscar Mateo | 0d76812 | 2017-03-22 10:39:50 -0700 | [diff] [blame] | 37 | * The specs sometimes refer to this object as a "GuC context", but we use |
| 38 | * the term "client" to avoid confusion with hardware contexts. This |
| 39 | * GEM object is held for the entire lifetime of our interaction with |
Dave Gordon | 86e06cc | 2016-04-19 16:08:36 +0100 | [diff] [blame] | 40 | * the GuC, being allocated before the GuC is loaded with its firmware. |
| 41 | * Because there's no way to update the address used by the GuC after |
| 42 | * initialisation, the shared object must stay pinned into the GGTT as |
| 43 | * long as the GuC is in use. We also keep the first page (only) mapped |
| 44 | * into kernel address space, as it includes shared data that must be |
| 45 | * updated on every request submission. |
| 46 | * |
| 47 | * The single GEM object described here is actually made up of several |
| 48 | * separate areas, as far as the GuC is concerned. The first page (kept |
Oscar Mateo | 0d76812 | 2017-03-22 10:39:50 -0700 | [diff] [blame] | 49 | * kmap'd) includes the "process descriptor" which holds sequence data for |
Dave Gordon | 86e06cc | 2016-04-19 16:08:36 +0100 | [diff] [blame] | 50 | * the doorbell, and one cacheline which actually *is* the doorbell; a |
| 51 | * write to this will "ring the doorbell" (i.e. send an interrupt to the |
| 52 | * GuC). The subsequent pages of the client object constitute the work |
| 53 | * queue (a circular array of work items), again described in the process |
| 54 | * descriptor. Work queue pages are mapped momentarily as required. |
| 55 | * |
Dave Gordon | 551aaec | 2016-05-13 15:36:33 +0100 | [diff] [blame] | 56 | * We also keep a few statistics on failures. Ideally, these should all |
| 57 | * be zero! |
| 58 | * no_wq_space: times that the submission pre-check found no space was |
| 59 | * available in the work queue (note, the queue is shared, |
| 60 | * not per-engine). It is OK for this to be nonzero, but |
| 61 | * it should not be huge! |
Dave Gordon | 551aaec | 2016-05-13 15:36:33 +0100 | [diff] [blame] | 62 | * b_fail: failed to ring the doorbell. This should never happen, unless |
| 63 | * somehow the hardware misbehaves, or maybe if the GuC firmware |
| 64 | * crashes? We probably need to reset the GPU to recover. |
| 65 | * retcode: errno from last guc_submit() |
Dave Gordon | 86e06cc | 2016-04-19 16:08:36 +0100 | [diff] [blame] | 66 | */ |
Dave Gordon | 44a28b1 | 2015-08-12 15:43:41 +0100 | [diff] [blame] | 67 | struct i915_guc_client { |
Chris Wilson | 8b797af | 2016-08-15 10:48:51 +0100 | [diff] [blame] | 68 | struct i915_vma *vma; |
Chris Wilson | 72aa0d8 | 2016-11-02 17:50:47 +0000 | [diff] [blame] | 69 | void *vaddr; |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 70 | struct i915_gem_context *owner; |
Dave Gordon | 44a28b1 | 2015-08-12 15:43:41 +0100 | [diff] [blame] | 71 | struct intel_guc *guc; |
Dave Gordon | e02757d | 2016-08-09 15:19:21 +0100 | [diff] [blame] | 72 | |
| 73 | uint32_t engines; /* bitmap of (host) engine ids */ |
Dave Gordon | 44a28b1 | 2015-08-12 15:43:41 +0100 | [diff] [blame] | 74 | uint32_t priority; |
Oscar Mateo | b09935a | 2017-03-22 10:39:53 -0700 | [diff] [blame] | 75 | u32 stage_id; |
Dave Gordon | 44a28b1 | 2015-08-12 15:43:41 +0100 | [diff] [blame] | 76 | uint32_t proc_desc_offset; |
Dave Gordon | 774439e1 | 2016-08-09 15:19:23 +0100 | [diff] [blame] | 77 | |
Joonas Lahtinen | abddffd | 2017-03-22 10:39:44 -0700 | [diff] [blame] | 78 | u16 doorbell_id; |
| 79 | unsigned long doorbell_offset; |
| 80 | u32 doorbell_cookie; |
Dave Gordon | 44a28b1 | 2015-08-12 15:43:41 +0100 | [diff] [blame] | 81 | |
Chris Wilson | dadd481 | 2016-09-09 14:11:57 +0100 | [diff] [blame] | 82 | spinlock_t wq_lock; |
Dave Gordon | 44a28b1 | 2015-08-12 15:43:41 +0100 | [diff] [blame] | 83 | uint32_t wq_offset; |
| 84 | uint32_t wq_size; |
Dave Gordon | 44a28b1 | 2015-08-12 15:43:41 +0100 | [diff] [blame] | 85 | uint32_t wq_tail; |
Chris Wilson | dadd481 | 2016-09-09 14:11:57 +0100 | [diff] [blame] | 86 | uint32_t wq_rsvd; |
Dave Gordon | 551aaec | 2016-05-13 15:36:33 +0100 | [diff] [blame] | 87 | uint32_t no_wq_space; |
Dave Gordon | 551aaec | 2016-05-13 15:36:33 +0100 | [diff] [blame] | 88 | |
| 89 | /* Per-engine counts of GuC submissions */ |
Dave Gordon | 0b63bb1 | 2016-06-20 15:18:07 +0100 | [diff] [blame] | 90 | uint64_t submissions[I915_NUM_ENGINES]; |
Dave Gordon | 44a28b1 | 2015-08-12 15:43:41 +0100 | [diff] [blame] | 91 | }; |
| 92 | |
Anusha Srivatsa | db0a091 | 2017-01-13 17:17:04 -0800 | [diff] [blame] | 93 | enum intel_uc_fw_status { |
| 94 | INTEL_UC_FIRMWARE_FAIL = -1, |
| 95 | INTEL_UC_FIRMWARE_NONE = 0, |
| 96 | INTEL_UC_FIRMWARE_PENDING, |
| 97 | INTEL_UC_FIRMWARE_SUCCESS |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 98 | }; |
| 99 | |
Michal Wajdeczko | 4f1cd3e | 2017-03-30 11:21:11 +0000 | [diff] [blame] | 100 | /* User-friendly representation of an enum */ |
| 101 | static inline |
| 102 | const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status) |
| 103 | { |
| 104 | switch (status) { |
| 105 | case INTEL_UC_FIRMWARE_FAIL: |
| 106 | return "FAIL"; |
| 107 | case INTEL_UC_FIRMWARE_NONE: |
| 108 | return "NONE"; |
| 109 | case INTEL_UC_FIRMWARE_PENDING: |
| 110 | return "PENDING"; |
| 111 | case INTEL_UC_FIRMWARE_SUCCESS: |
| 112 | return "SUCCESS"; |
Michal Wajdeczko | 4f1cd3e | 2017-03-30 11:21:11 +0000 | [diff] [blame] | 113 | } |
Michal Wajdeczko | b9ab1f3 | 2017-03-31 10:26:52 +0000 | [diff] [blame] | 114 | return "<invalid>"; |
Michal Wajdeczko | 4f1cd3e | 2017-03-30 11:21:11 +0000 | [diff] [blame] | 115 | } |
| 116 | |
Anusha Srivatsa | fbbad73 | 2017-01-13 17:17:05 -0800 | [diff] [blame] | 117 | enum intel_uc_fw_type { |
| 118 | INTEL_UC_FW_TYPE_GUC, |
| 119 | INTEL_UC_FW_TYPE_HUC |
| 120 | }; |
| 121 | |
Michal Wajdeczko | 5e065f1 | 2017-03-30 11:21:12 +0000 | [diff] [blame] | 122 | /* User-friendly representation of an enum */ |
| 123 | static inline const char *intel_uc_fw_type_repr(enum intel_uc_fw_type type) |
| 124 | { |
| 125 | switch (type) { |
| 126 | case INTEL_UC_FW_TYPE_GUC: |
| 127 | return "GuC"; |
| 128 | case INTEL_UC_FW_TYPE_HUC: |
| 129 | return "HuC"; |
Michal Wajdeczko | 5e065f1 | 2017-03-30 11:21:12 +0000 | [diff] [blame] | 130 | } |
Michal Wajdeczko | b9ab1f3 | 2017-03-31 10:26:52 +0000 | [diff] [blame] | 131 | return "uC"; |
Michal Wajdeczko | 5e065f1 | 2017-03-30 11:21:12 +0000 | [diff] [blame] | 132 | } |
| 133 | |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 134 | /* |
| 135 | * This structure encapsulates all the data needed during the process |
| 136 | * of fetching, caching, and loading the firmware image into the GuC. |
| 137 | */ |
Anusha Srivatsa | db0a091 | 2017-01-13 17:17:04 -0800 | [diff] [blame] | 138 | struct intel_uc_fw { |
| 139 | const char *path; |
| 140 | size_t size; |
| 141 | struct drm_i915_gem_object *obj; |
| 142 | enum intel_uc_fw_status fetch_status; |
| 143 | enum intel_uc_fw_status load_status; |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 144 | |
Anusha Srivatsa | db0a091 | 2017-01-13 17:17:04 -0800 | [diff] [blame] | 145 | uint16_t major_ver_wanted; |
| 146 | uint16_t minor_ver_wanted; |
| 147 | uint16_t major_ver_found; |
| 148 | uint16_t minor_ver_found; |
Alex Dai | feda33e | 2015-10-19 16:10:54 -0700 | [diff] [blame] | 149 | |
Arkadiusz Hiler | 6833b82e | 2017-03-15 14:34:15 +0100 | [diff] [blame] | 150 | enum intel_uc_fw_type type; |
Alex Dai | feda33e | 2015-10-19 16:10:54 -0700 | [diff] [blame] | 151 | uint32_t header_size; |
| 152 | uint32_t header_offset; |
| 153 | uint32_t rsa_size; |
| 154 | uint32_t rsa_offset; |
| 155 | uint32_t ucode_size; |
| 156 | uint32_t ucode_offset; |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 157 | }; |
| 158 | |
Akash Goel | d6b40b4 | 2016-10-12 21:54:29 +0530 | [diff] [blame] | 159 | struct intel_guc_log { |
| 160 | uint32_t flags; |
| 161 | struct i915_vma *vma; |
Oscar Mateo | e746547 | 2017-03-22 10:39:48 -0700 | [diff] [blame] | 162 | /* The runtime stuff gets created only when GuC logging gets enabled */ |
| 163 | struct { |
| 164 | void *buf_addr; |
| 165 | struct workqueue_struct *flush_wq; |
| 166 | struct work_struct flush_work; |
| 167 | struct rchan *relay_chan; |
| 168 | } runtime; |
Akash Goel | 5aa1ee4 | 2016-10-12 21:54:36 +0530 | [diff] [blame] | 169 | /* logging related stats */ |
| 170 | u32 capture_miss_count; |
| 171 | u32 flush_interrupt_count; |
| 172 | u32 prev_overflow_count[GUC_MAX_LOG_BUFFER]; |
| 173 | u32 total_overflow_count[GUC_MAX_LOG_BUFFER]; |
| 174 | u32 flush_count[GUC_MAX_LOG_BUFFER]; |
Akash Goel | d6b40b4 | 2016-10-12 21:54:29 +0530 | [diff] [blame] | 175 | }; |
| 176 | |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 177 | struct intel_guc { |
Anusha Srivatsa | db0a091 | 2017-01-13 17:17:04 -0800 | [diff] [blame] | 178 | struct intel_uc_fw fw; |
Akash Goel | d6b40b4 | 2016-10-12 21:54:29 +0530 | [diff] [blame] | 179 | struct intel_guc_log log; |
Michal Wajdeczko | f8a58d6 | 2017-05-26 11:13:25 +0000 | [diff] [blame] | 180 | struct intel_guc_ct ct; |
Alex Dai | bac427f | 2015-08-12 15:43:39 +0100 | [diff] [blame] | 181 | |
Daniele Ceraolo Spurio | ac58d2a | 2017-05-22 10:50:28 -0700 | [diff] [blame] | 182 | /* Log snapshot if GuC errors during load */ |
| 183 | struct drm_i915_gem_object *load_err_log; |
| 184 | |
Arkadiusz Hiler | a80bc45 | 2016-11-25 18:59:34 +0100 | [diff] [blame] | 185 | /* intel_guc_recv interrupt related state */ |
Sagar Arun Kamble | 26705e2 | 2016-10-12 21:54:31 +0530 | [diff] [blame] | 186 | bool interrupts_enabled; |
| 187 | |
Chris Wilson | 8b797af | 2016-08-15 10:48:51 +0100 | [diff] [blame] | 188 | struct i915_vma *ads_vma; |
Oscar Mateo | b09935a | 2017-03-22 10:39:53 -0700 | [diff] [blame] | 189 | struct i915_vma *stage_desc_pool; |
| 190 | void *stage_desc_pool_vaddr; |
| 191 | struct ida stage_ids; |
Dave Gordon | 44a28b1 | 2015-08-12 15:43:41 +0100 | [diff] [blame] | 192 | |
| 193 | struct i915_guc_client *execbuf_client; |
| 194 | |
Joonas Lahtinen | abddffd | 2017-03-22 10:39:44 -0700 | [diff] [blame] | 195 | DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS); |
Dave Gordon | 44a28b1 | 2015-08-12 15:43:41 +0100 | [diff] [blame] | 196 | uint32_t db_cacheline; /* Cyclic counter mod pagesize */ |
| 197 | |
Michal Wajdeczko | a0c1fe2 | 2017-05-10 12:59:27 +0000 | [diff] [blame] | 198 | /* GuC's FW specific registers used in MMIO send */ |
| 199 | struct { |
| 200 | u32 base; |
| 201 | unsigned int count; |
| 202 | enum forcewake_domains fw_domains; |
| 203 | } send_regs; |
| 204 | |
Arkadiusz Hiler | a80bc45 | 2016-11-25 18:59:34 +0100 | [diff] [blame] | 205 | /* To serialize the intel_guc_send actions */ |
| 206 | struct mutex send_mutex; |
Oscar Mateo | 5e7cd37 | 2017-03-22 10:39:49 -0700 | [diff] [blame] | 207 | |
| 208 | /* GuC's FW specific send function */ |
| 209 | int (*send)(struct intel_guc *guc, const u32 *data, u32 len); |
Michal Wajdeczko | a03aac4 | 2017-05-10 12:59:26 +0000 | [diff] [blame] | 210 | |
| 211 | /* GuC's FW specific notify function */ |
| 212 | void (*notify)(struct intel_guc *guc); |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 213 | }; |
| 214 | |
Anusha Srivatsa | bd13285 | 2017-01-18 08:05:53 -0800 | [diff] [blame] | 215 | struct intel_huc { |
| 216 | /* Generic uC firmware management */ |
| 217 | struct intel_uc_fw fw; |
| 218 | |
| 219 | /* HuC-specific additions */ |
| 220 | }; |
| 221 | |
Arkadiusz Hiler | 2d803c2 | 2016-11-25 18:59:35 +0100 | [diff] [blame] | 222 | /* intel_uc.c */ |
Arkadiusz Hiler | d2be9f2 | 2017-03-14 15:28:10 +0100 | [diff] [blame] | 223 | void intel_uc_sanitize_options(struct drm_i915_private *dev_priv); |
Arkadiusz Hiler | 413e8fd | 2016-11-25 18:59:36 +0100 | [diff] [blame] | 224 | void intel_uc_init_early(struct drm_i915_private *dev_priv); |
Arkadiusz Hiler | 29ad6a3 | 2017-03-14 15:28:09 +0100 | [diff] [blame] | 225 | void intel_uc_init_fw(struct drm_i915_private *dev_priv); |
Oscar Mateo | 3950bf3 | 2017-03-22 10:39:46 -0700 | [diff] [blame] | 226 | void intel_uc_fini_fw(struct drm_i915_private *dev_priv); |
Arkadiusz Hiler | 6cd5a72 | 2017-03-14 15:28:11 +0100 | [diff] [blame] | 227 | int intel_uc_init_hw(struct drm_i915_private *dev_priv); |
Oscar Mateo | 3950bf3 | 2017-03-22 10:39:46 -0700 | [diff] [blame] | 228 | void intel_uc_fini_hw(struct drm_i915_private *dev_priv); |
Arkadiusz Hiler | 2d803c2 | 2016-11-25 18:59:35 +0100 | [diff] [blame] | 229 | int intel_guc_sample_forcewake(struct intel_guc *guc); |
Michal Wajdeczko | 789a625 | 2017-05-02 10:32:42 +0000 | [diff] [blame] | 230 | int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len); |
Oscar Mateo | 5e7cd37 | 2017-03-22 10:39:49 -0700 | [diff] [blame] | 231 | int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len); |
Michal Wajdeczko | a03aac4 | 2017-05-10 12:59:26 +0000 | [diff] [blame] | 232 | |
Oscar Mateo | 5e7cd37 | 2017-03-22 10:39:49 -0700 | [diff] [blame] | 233 | static inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) |
| 234 | { |
| 235 | return guc->send(guc, action, len); |
| 236 | } |
Arkadiusz Hiler | 2d803c2 | 2016-11-25 18:59:35 +0100 | [diff] [blame] | 237 | |
Michal Wajdeczko | a03aac4 | 2017-05-10 12:59:26 +0000 | [diff] [blame] | 238 | static inline void intel_guc_notify(struct intel_guc *guc) |
| 239 | { |
| 240 | guc->notify(guc); |
| 241 | } |
| 242 | |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 243 | /* intel_guc_loader.c */ |
Arkadiusz Hiler | b551f61 | 2017-03-14 15:28:13 +0100 | [diff] [blame] | 244 | int intel_guc_select_fw(struct intel_guc *guc); |
Arkadiusz Hiler | 882d1db | 2017-03-14 15:28:07 +0100 | [diff] [blame] | 245 | int intel_guc_init_hw(struct intel_guc *guc); |
Arkadiusz Hiler | 0417a2b | 2017-03-14 15:28:05 +0100 | [diff] [blame] | 246 | int intel_guc_suspend(struct drm_i915_private *dev_priv); |
| 247 | int intel_guc_resume(struct drm_i915_private *dev_priv); |
Anusha Srivatsa | db0a091 | 2017-01-13 17:17:04 -0800 | [diff] [blame] | 248 | u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv); |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 249 | |
Alex Dai | bac427f | 2015-08-12 15:43:39 +0100 | [diff] [blame] | 250 | /* i915_guc_submission.c */ |
Dave Gordon | beffa51 | 2016-06-10 18:29:26 +0100 | [diff] [blame] | 251 | int i915_guc_submission_init(struct drm_i915_private *dev_priv); |
| 252 | int i915_guc_submission_enable(struct drm_i915_private *dev_priv); |
Dave Gordon | 7a9347f | 2016-09-12 21:19:37 +0100 | [diff] [blame] | 253 | int i915_guc_wq_reserve(struct drm_i915_gem_request *rq); |
Chris Wilson | 5ba8990 | 2016-10-07 07:53:27 +0100 | [diff] [blame] | 254 | void i915_guc_wq_unreserve(struct drm_i915_gem_request *request); |
Dave Gordon | beffa51 | 2016-06-10 18:29:26 +0100 | [diff] [blame] | 255 | void i915_guc_submission_disable(struct drm_i915_private *dev_priv); |
| 256 | void i915_guc_submission_fini(struct drm_i915_private *dev_priv); |
Michal Wajdeczko | f9cda04 | 2017-01-13 17:41:57 +0000 | [diff] [blame] | 257 | struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size); |
| 258 | |
| 259 | /* intel_guc_log.c */ |
Oscar Mateo | 3950bf3 | 2017-03-22 10:39:46 -0700 | [diff] [blame] | 260 | int intel_guc_log_create(struct intel_guc *guc); |
| 261 | void intel_guc_log_destroy(struct intel_guc *guc); |
| 262 | int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val); |
Michal Wajdeczko | f9cda04 | 2017-01-13 17:41:57 +0000 | [diff] [blame] | 263 | void i915_guc_log_register(struct drm_i915_private *dev_priv); |
| 264 | void i915_guc_log_unregister(struct drm_i915_private *dev_priv); |
Alex Dai | bac427f | 2015-08-12 15:43:39 +0100 | [diff] [blame] | 265 | |
Chris Wilson | 4741da9 | 2016-12-24 19:31:46 +0000 | [diff] [blame] | 266 | static inline u32 guc_ggtt_offset(struct i915_vma *vma) |
| 267 | { |
| 268 | u32 offset = i915_ggtt_offset(vma); |
| 269 | GEM_BUG_ON(offset < GUC_WOPCM_TOP); |
Chris Wilson | db9309a | 2017-01-05 15:30:23 +0000 | [diff] [blame] | 270 | GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP)); |
Chris Wilson | 4741da9 | 2016-12-24 19:31:46 +0000 | [diff] [blame] | 271 | return offset; |
| 272 | } |
| 273 | |
Anusha Srivatsa | bd13285 | 2017-01-18 08:05:53 -0800 | [diff] [blame] | 274 | /* intel_huc.c */ |
Arkadiusz Hiler | b551f61 | 2017-03-14 15:28:13 +0100 | [diff] [blame] | 275 | void intel_huc_select_fw(struct intel_huc *huc); |
Michal Wajdeczko | 01a9ca0 | 2017-03-31 11:57:09 +0000 | [diff] [blame] | 276 | void intel_huc_init_hw(struct intel_huc *huc); |
Anusha Srivatsa | dac84a3 | 2017-01-18 08:05:57 -0800 | [diff] [blame] | 277 | void intel_guc_auth_huc(struct drm_i915_private *dev_priv); |
Anusha Srivatsa | bd13285 | 2017-01-18 08:05:53 -0800 | [diff] [blame] | 278 | |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 279 | #endif |