blob: 22ae52b17b0fa5b10979e56e8e04a9d477ee64c4 [file] [log] [blame]
Alex Dai33a732f2015-08-12 15:43:36 +01001/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
Arkadiusz Hiler8c4f24f2016-11-25 18:59:33 +010024#ifndef _INTEL_UC_H_
25#define _INTEL_UC_H_
Alex Dai33a732f2015-08-12 15:43:36 +010026
27#include "intel_guc_fwif.h"
28#include "i915_guc_reg.h"
Dave Gordon0b63bb12016-06-20 15:18:07 +010029#include "intel_ringbuffer.h"
Michal Wajdeczkof8a58d62017-05-26 11:13:25 +000030#include "intel_guc_ct.h"
Chris Wilson4741da92016-12-24 19:31:46 +000031#include "i915_vma.h"
32
Chris Wilsone73bdd22016-04-13 17:35:01 +010033struct drm_i915_gem_request;
34
Dave Gordon86e06cc2016-04-19 16:08:36 +010035/*
36 * This structure primarily describes the GEM object shared with the GuC.
Oscar Mateo0d768122017-03-22 10:39:50 -070037 * The specs sometimes refer to this object as a "GuC context", but we use
38 * the term "client" to avoid confusion with hardware contexts. This
39 * GEM object is held for the entire lifetime of our interaction with
Dave Gordon86e06cc2016-04-19 16:08:36 +010040 * the GuC, being allocated before the GuC is loaded with its firmware.
41 * Because there's no way to update the address used by the GuC after
42 * initialisation, the shared object must stay pinned into the GGTT as
43 * long as the GuC is in use. We also keep the first page (only) mapped
44 * into kernel address space, as it includes shared data that must be
45 * updated on every request submission.
46 *
47 * The single GEM object described here is actually made up of several
48 * separate areas, as far as the GuC is concerned. The first page (kept
Oscar Mateo0d768122017-03-22 10:39:50 -070049 * kmap'd) includes the "process descriptor" which holds sequence data for
Dave Gordon86e06cc2016-04-19 16:08:36 +010050 * the doorbell, and one cacheline which actually *is* the doorbell; a
51 * write to this will "ring the doorbell" (i.e. send an interrupt to the
52 * GuC). The subsequent pages of the client object constitute the work
53 * queue (a circular array of work items), again described in the process
54 * descriptor. Work queue pages are mapped momentarily as required.
55 *
Dave Gordon551aaec2016-05-13 15:36:33 +010056 * We also keep a few statistics on failures. Ideally, these should all
57 * be zero!
58 * no_wq_space: times that the submission pre-check found no space was
59 * available in the work queue (note, the queue is shared,
60 * not per-engine). It is OK for this to be nonzero, but
61 * it should not be huge!
Dave Gordon551aaec2016-05-13 15:36:33 +010062 * b_fail: failed to ring the doorbell. This should never happen, unless
63 * somehow the hardware misbehaves, or maybe if the GuC firmware
64 * crashes? We probably need to reset the GPU to recover.
65 * retcode: errno from last guc_submit()
Dave Gordon86e06cc2016-04-19 16:08:36 +010066 */
Dave Gordon44a28b12015-08-12 15:43:41 +010067struct i915_guc_client {
Chris Wilson8b797af2016-08-15 10:48:51 +010068 struct i915_vma *vma;
Chris Wilson72aa0d82016-11-02 17:50:47 +000069 void *vaddr;
Chris Wilsone2efd132016-05-24 14:53:34 +010070 struct i915_gem_context *owner;
Dave Gordon44a28b12015-08-12 15:43:41 +010071 struct intel_guc *guc;
Dave Gordone02757d2016-08-09 15:19:21 +010072
73 uint32_t engines; /* bitmap of (host) engine ids */
Dave Gordon44a28b12015-08-12 15:43:41 +010074 uint32_t priority;
Oscar Mateob09935a2017-03-22 10:39:53 -070075 u32 stage_id;
Dave Gordon44a28b12015-08-12 15:43:41 +010076 uint32_t proc_desc_offset;
Dave Gordon774439e12016-08-09 15:19:23 +010077
Joonas Lahtinenabddffd2017-03-22 10:39:44 -070078 u16 doorbell_id;
79 unsigned long doorbell_offset;
80 u32 doorbell_cookie;
Dave Gordon44a28b12015-08-12 15:43:41 +010081
Chris Wilsondadd4812016-09-09 14:11:57 +010082 spinlock_t wq_lock;
Dave Gordon44a28b12015-08-12 15:43:41 +010083 uint32_t wq_offset;
84 uint32_t wq_size;
Dave Gordon44a28b12015-08-12 15:43:41 +010085 uint32_t wq_tail;
Chris Wilsondadd4812016-09-09 14:11:57 +010086 uint32_t wq_rsvd;
Dave Gordon551aaec2016-05-13 15:36:33 +010087 uint32_t no_wq_space;
Dave Gordon551aaec2016-05-13 15:36:33 +010088
89 /* Per-engine counts of GuC submissions */
Dave Gordon0b63bb12016-06-20 15:18:07 +010090 uint64_t submissions[I915_NUM_ENGINES];
Dave Gordon44a28b12015-08-12 15:43:41 +010091};
92
Anusha Srivatsadb0a0912017-01-13 17:17:04 -080093enum intel_uc_fw_status {
94 INTEL_UC_FIRMWARE_FAIL = -1,
95 INTEL_UC_FIRMWARE_NONE = 0,
96 INTEL_UC_FIRMWARE_PENDING,
97 INTEL_UC_FIRMWARE_SUCCESS
Alex Dai33a732f2015-08-12 15:43:36 +010098};
99
Michal Wajdeczko4f1cd3e2017-03-30 11:21:11 +0000100/* User-friendly representation of an enum */
101static inline
102const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
103{
104 switch (status) {
105 case INTEL_UC_FIRMWARE_FAIL:
106 return "FAIL";
107 case INTEL_UC_FIRMWARE_NONE:
108 return "NONE";
109 case INTEL_UC_FIRMWARE_PENDING:
110 return "PENDING";
111 case INTEL_UC_FIRMWARE_SUCCESS:
112 return "SUCCESS";
Michal Wajdeczko4f1cd3e2017-03-30 11:21:11 +0000113 }
Michal Wajdeczkob9ab1f32017-03-31 10:26:52 +0000114 return "<invalid>";
Michal Wajdeczko4f1cd3e2017-03-30 11:21:11 +0000115}
116
Anusha Srivatsafbbad732017-01-13 17:17:05 -0800117enum intel_uc_fw_type {
118 INTEL_UC_FW_TYPE_GUC,
119 INTEL_UC_FW_TYPE_HUC
120};
121
Michal Wajdeczko5e065f12017-03-30 11:21:12 +0000122/* User-friendly representation of an enum */
123static inline const char *intel_uc_fw_type_repr(enum intel_uc_fw_type type)
124{
125 switch (type) {
126 case INTEL_UC_FW_TYPE_GUC:
127 return "GuC";
128 case INTEL_UC_FW_TYPE_HUC:
129 return "HuC";
Michal Wajdeczko5e065f12017-03-30 11:21:12 +0000130 }
Michal Wajdeczkob9ab1f32017-03-31 10:26:52 +0000131 return "uC";
Michal Wajdeczko5e065f12017-03-30 11:21:12 +0000132}
133
Alex Dai33a732f2015-08-12 15:43:36 +0100134/*
135 * This structure encapsulates all the data needed during the process
136 * of fetching, caching, and loading the firmware image into the GuC.
137 */
Anusha Srivatsadb0a0912017-01-13 17:17:04 -0800138struct intel_uc_fw {
139 const char *path;
140 size_t size;
141 struct drm_i915_gem_object *obj;
142 enum intel_uc_fw_status fetch_status;
143 enum intel_uc_fw_status load_status;
Alex Dai33a732f2015-08-12 15:43:36 +0100144
Anusha Srivatsadb0a0912017-01-13 17:17:04 -0800145 uint16_t major_ver_wanted;
146 uint16_t minor_ver_wanted;
147 uint16_t major_ver_found;
148 uint16_t minor_ver_found;
Alex Daifeda33e2015-10-19 16:10:54 -0700149
Arkadiusz Hiler6833b82e2017-03-15 14:34:15 +0100150 enum intel_uc_fw_type type;
Alex Daifeda33e2015-10-19 16:10:54 -0700151 uint32_t header_size;
152 uint32_t header_offset;
153 uint32_t rsa_size;
154 uint32_t rsa_offset;
155 uint32_t ucode_size;
156 uint32_t ucode_offset;
Alex Dai33a732f2015-08-12 15:43:36 +0100157};
158
Akash Goeld6b40b42016-10-12 21:54:29 +0530159struct intel_guc_log {
160 uint32_t flags;
161 struct i915_vma *vma;
Oscar Mateoe7465472017-03-22 10:39:48 -0700162 /* The runtime stuff gets created only when GuC logging gets enabled */
163 struct {
164 void *buf_addr;
165 struct workqueue_struct *flush_wq;
166 struct work_struct flush_work;
167 struct rchan *relay_chan;
168 } runtime;
Akash Goel5aa1ee42016-10-12 21:54:36 +0530169 /* logging related stats */
170 u32 capture_miss_count;
171 u32 flush_interrupt_count;
172 u32 prev_overflow_count[GUC_MAX_LOG_BUFFER];
173 u32 total_overflow_count[GUC_MAX_LOG_BUFFER];
174 u32 flush_count[GUC_MAX_LOG_BUFFER];
Akash Goeld6b40b42016-10-12 21:54:29 +0530175};
176
Alex Dai33a732f2015-08-12 15:43:36 +0100177struct intel_guc {
Anusha Srivatsadb0a0912017-01-13 17:17:04 -0800178 struct intel_uc_fw fw;
Akash Goeld6b40b42016-10-12 21:54:29 +0530179 struct intel_guc_log log;
Michal Wajdeczkof8a58d62017-05-26 11:13:25 +0000180 struct intel_guc_ct ct;
Alex Daibac427f2015-08-12 15:43:39 +0100181
Daniele Ceraolo Spurioac58d2a2017-05-22 10:50:28 -0700182 /* Log snapshot if GuC errors during load */
183 struct drm_i915_gem_object *load_err_log;
184
Arkadiusz Hilera80bc452016-11-25 18:59:34 +0100185 /* intel_guc_recv interrupt related state */
Sagar Arun Kamble26705e22016-10-12 21:54:31 +0530186 bool interrupts_enabled;
187
Chris Wilson8b797af2016-08-15 10:48:51 +0100188 struct i915_vma *ads_vma;
Oscar Mateob09935a2017-03-22 10:39:53 -0700189 struct i915_vma *stage_desc_pool;
190 void *stage_desc_pool_vaddr;
191 struct ida stage_ids;
Dave Gordon44a28b12015-08-12 15:43:41 +0100192
193 struct i915_guc_client *execbuf_client;
194
Joonas Lahtinenabddffd2017-03-22 10:39:44 -0700195 DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
Dave Gordon44a28b12015-08-12 15:43:41 +0100196 uint32_t db_cacheline; /* Cyclic counter mod pagesize */
197
Michal Wajdeczkoa0c1fe22017-05-10 12:59:27 +0000198 /* GuC's FW specific registers used in MMIO send */
199 struct {
200 u32 base;
201 unsigned int count;
202 enum forcewake_domains fw_domains;
203 } send_regs;
204
Arkadiusz Hilera80bc452016-11-25 18:59:34 +0100205 /* To serialize the intel_guc_send actions */
206 struct mutex send_mutex;
Oscar Mateo5e7cd372017-03-22 10:39:49 -0700207
208 /* GuC's FW specific send function */
209 int (*send)(struct intel_guc *guc, const u32 *data, u32 len);
Michal Wajdeczkoa03aac42017-05-10 12:59:26 +0000210
211 /* GuC's FW specific notify function */
212 void (*notify)(struct intel_guc *guc);
Alex Dai33a732f2015-08-12 15:43:36 +0100213};
214
Anusha Srivatsabd132852017-01-18 08:05:53 -0800215struct intel_huc {
216 /* Generic uC firmware management */
217 struct intel_uc_fw fw;
218
219 /* HuC-specific additions */
220};
221
Arkadiusz Hiler2d803c22016-11-25 18:59:35 +0100222/* intel_uc.c */
Arkadiusz Hilerd2be9f22017-03-14 15:28:10 +0100223void intel_uc_sanitize_options(struct drm_i915_private *dev_priv);
Arkadiusz Hiler413e8fd2016-11-25 18:59:36 +0100224void intel_uc_init_early(struct drm_i915_private *dev_priv);
Arkadiusz Hiler29ad6a32017-03-14 15:28:09 +0100225void intel_uc_init_fw(struct drm_i915_private *dev_priv);
Oscar Mateo3950bf32017-03-22 10:39:46 -0700226void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
Arkadiusz Hiler6cd5a722017-03-14 15:28:11 +0100227int intel_uc_init_hw(struct drm_i915_private *dev_priv);
Oscar Mateo3950bf32017-03-22 10:39:46 -0700228void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
Arkadiusz Hiler2d803c22016-11-25 18:59:35 +0100229int intel_guc_sample_forcewake(struct intel_guc *guc);
Michal Wajdeczko789a6252017-05-02 10:32:42 +0000230int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
Oscar Mateo5e7cd372017-03-22 10:39:49 -0700231int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
Michal Wajdeczkoa03aac42017-05-10 12:59:26 +0000232
Oscar Mateo5e7cd372017-03-22 10:39:49 -0700233static inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
234{
235 return guc->send(guc, action, len);
236}
Arkadiusz Hiler2d803c22016-11-25 18:59:35 +0100237
Michal Wajdeczkoa03aac42017-05-10 12:59:26 +0000238static inline void intel_guc_notify(struct intel_guc *guc)
239{
240 guc->notify(guc);
241}
242
Alex Dai33a732f2015-08-12 15:43:36 +0100243/* intel_guc_loader.c */
Arkadiusz Hilerb551f612017-03-14 15:28:13 +0100244int intel_guc_select_fw(struct intel_guc *guc);
Arkadiusz Hiler882d1db2017-03-14 15:28:07 +0100245int intel_guc_init_hw(struct intel_guc *guc);
Arkadiusz Hiler0417a2b2017-03-14 15:28:05 +0100246int intel_guc_suspend(struct drm_i915_private *dev_priv);
247int intel_guc_resume(struct drm_i915_private *dev_priv);
Anusha Srivatsadb0a0912017-01-13 17:17:04 -0800248u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
Alex Dai33a732f2015-08-12 15:43:36 +0100249
Alex Daibac427f2015-08-12 15:43:39 +0100250/* i915_guc_submission.c */
Dave Gordonbeffa512016-06-10 18:29:26 +0100251int i915_guc_submission_init(struct drm_i915_private *dev_priv);
252int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
Dave Gordon7a9347f2016-09-12 21:19:37 +0100253int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
Chris Wilson5ba89902016-10-07 07:53:27 +0100254void i915_guc_wq_unreserve(struct drm_i915_gem_request *request);
Dave Gordonbeffa512016-06-10 18:29:26 +0100255void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
256void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
Michal Wajdeczkof9cda042017-01-13 17:41:57 +0000257struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
258
259/* intel_guc_log.c */
Oscar Mateo3950bf32017-03-22 10:39:46 -0700260int intel_guc_log_create(struct intel_guc *guc);
261void intel_guc_log_destroy(struct intel_guc *guc);
262int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
Michal Wajdeczkof9cda042017-01-13 17:41:57 +0000263void i915_guc_log_register(struct drm_i915_private *dev_priv);
264void i915_guc_log_unregister(struct drm_i915_private *dev_priv);
Alex Daibac427f2015-08-12 15:43:39 +0100265
Chris Wilson4741da92016-12-24 19:31:46 +0000266static inline u32 guc_ggtt_offset(struct i915_vma *vma)
267{
268 u32 offset = i915_ggtt_offset(vma);
269 GEM_BUG_ON(offset < GUC_WOPCM_TOP);
Chris Wilsondb9309a2017-01-05 15:30:23 +0000270 GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
Chris Wilson4741da92016-12-24 19:31:46 +0000271 return offset;
272}
273
Anusha Srivatsabd132852017-01-18 08:05:53 -0800274/* intel_huc.c */
Arkadiusz Hilerb551f612017-03-14 15:28:13 +0100275void intel_huc_select_fw(struct intel_huc *huc);
Michal Wajdeczko01a9ca02017-03-31 11:57:09 +0000276void intel_huc_init_hw(struct intel_huc *huc);
Anusha Srivatsadac84a32017-01-18 08:05:57 -0800277void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
Anusha Srivatsabd132852017-01-18 08:05:53 -0800278
Alex Dai33a732f2015-08-12 15:43:36 +0100279#endif