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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2*
3* 3780i.c -- helper routines for the 3780i DSP
4*
5*
6* Written By: Mike Sullivan IBM Corporation
7*
8* Copyright (C) 1999 IBM Corporation
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; either version 2 of the License, or
13* (at your option) any later version.
14*
15* This program is distributed in the hope that it will be useful,
16* but WITHOUT ANY WARRANTY; without even the implied warranty of
17* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18* GNU General Public License for more details.
19*
20* NO WARRANTY
21* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25* solely responsible for determining the appropriateness of using and
26* distributing the Program and assumes all risks associated with its
27* exercise of rights under this Agreement, including but not limited to
28* the risks and costs of program errors, damage to or loss of data,
29* programs or equipment, and unavailability or interruption of operations.
30*
31* DISCLAIMER OF LIABILITY
32* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39*
40* You should have received a copy of the GNU General Public License
41* along with this program; if not, write to the Free Software
42* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
43*
44*
45* 10/23/2000 - Alpha Release
46* First release to the public
47*/
48
49#include <linux/config.h>
50#include <linux/kernel.h>
51#include <linux/unistd.h>
52#include <linux/delay.h>
53#include <linux/ioport.h>
54#include <linux/init.h>
55#include <linux/bitops.h>
56#include <asm/io.h>
57#include <asm/uaccess.h>
58#include <asm/system.h>
59#include <asm/irq.h>
60#include "smapi.h"
61#include "mwavedd.h"
62#include "3780i.h"
63
64static DEFINE_SPINLOCK(dsp_lock);
65static unsigned long flags;
66
67
68static void PaceMsaAccess(unsigned short usDspBaseIO)
69{
70 cond_resched();
71 udelay(100);
72 cond_resched();
73}
74
75unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO,
76 unsigned long ulMsaAddr)
77{
78 unsigned short val;
79
80 PRINTK_3(TRACE_3780I,
81 "3780i::dsp3780I_ReadMsaCfg entry usDspBaseIO %x ulMsaAddr %lx\n",
82 usDspBaseIO, ulMsaAddr);
83
84 spin_lock_irqsave(&dsp_lock, flags);
85 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr);
86 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16));
87 val = InWordDsp(DSP_MsaDataDSISHigh);
88 spin_unlock_irqrestore(&dsp_lock, flags);
89
90 PRINTK_2(TRACE_3780I, "3780i::dsp3780I_ReadMsaCfg exit val %x\n", val);
91
92 return val;
93}
94
95void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO,
96 unsigned long ulMsaAddr, unsigned short usValue)
97{
98
99 PRINTK_4(TRACE_3780I,
100 "3780i::dsp3780i_WriteMsaCfg entry usDspBaseIO %x ulMsaAddr %lx usValue %x\n",
101 usDspBaseIO, ulMsaAddr, usValue);
102
103 spin_lock_irqsave(&dsp_lock, flags);
104 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr);
105 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16));
106 OutWordDsp(DSP_MsaDataDSISHigh, usValue);
107 spin_unlock_irqrestore(&dsp_lock, flags);
108}
109
Adrian Bunk3b01b472005-06-25 14:59:03 -0700110static void dsp3780I_WriteGenCfg(unsigned short usDspBaseIO, unsigned uIndex,
111 unsigned char ucValue)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112{
113 DSP_ISA_SLAVE_CONTROL rSlaveControl;
114 DSP_ISA_SLAVE_CONTROL rSlaveControl_Save;
115
116
117 PRINTK_4(TRACE_3780I,
118 "3780i::dsp3780i_WriteGenCfg entry usDspBaseIO %x uIndex %x ucValue %x\n",
119 usDspBaseIO, uIndex, ucValue);
120
121 MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl);
122
123 PRINTK_2(TRACE_3780I,
124 "3780i::dsp3780i_WriteGenCfg rSlaveControl %x\n",
125 MKBYTE(rSlaveControl));
126
127 rSlaveControl_Save = rSlaveControl;
128 rSlaveControl.ConfigMode = TRUE;
129
130 PRINTK_2(TRACE_3780I,
131 "3780i::dsp3780i_WriteGenCfg entry rSlaveControl+ConfigMode %x\n",
132 MKBYTE(rSlaveControl));
133
134 OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl));
135 OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex);
136 OutByteDsp(DSP_ConfigData, ucValue);
137 OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save));
138
139 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_WriteGenCfg exit\n");
140
141
142}
143
Adrian Bunk3b01b472005-06-25 14:59:03 -0700144#if 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145unsigned char dsp3780I_ReadGenCfg(unsigned short usDspBaseIO,
146 unsigned uIndex)
147{
148 DSP_ISA_SLAVE_CONTROL rSlaveControl;
149 DSP_ISA_SLAVE_CONTROL rSlaveControl_Save;
150 unsigned char ucValue;
151
152
153 PRINTK_3(TRACE_3780I,
154 "3780i::dsp3780i_ReadGenCfg entry usDspBaseIO %x uIndex %x\n",
155 usDspBaseIO, uIndex);
156
157 MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl);
158 rSlaveControl_Save = rSlaveControl;
159 rSlaveControl.ConfigMode = TRUE;
160 OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl));
161 OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex);
162 ucValue = InByteDsp(DSP_ConfigData);
163 OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save));
164
165 PRINTK_2(TRACE_3780I,
166 "3780i::dsp3780i_ReadGenCfg exit ucValue %x\n", ucValue);
167
168
169 return ucValue;
170}
Adrian Bunk3b01b472005-06-25 14:59:03 -0700171#endif /* 0 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172
173int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings,
174 unsigned short *pIrqMap,
175 unsigned short *pDmaMap)
176{
177 unsigned short usDspBaseIO = pSettings->usDspBaseIO;
178 int i;
179 DSP_UART_CFG_1 rUartCfg1;
180 DSP_UART_CFG_2 rUartCfg2;
181 DSP_HBRIDGE_CFG_1 rHBridgeCfg1;
182 DSP_HBRIDGE_CFG_2 rHBridgeCfg2;
183 DSP_BUSMASTER_CFG_1 rBusmasterCfg1;
184 DSP_BUSMASTER_CFG_2 rBusmasterCfg2;
185 DSP_ISA_PROT_CFG rIsaProtCfg;
186 DSP_POWER_MGMT_CFG rPowerMgmtCfg;
187 DSP_HBUS_TIMER_CFG rHBusTimerCfg;
188 DSP_LBUS_TIMEOUT_DISABLE rLBusTimeoutDisable;
189 DSP_CHIP_RESET rChipReset;
190 DSP_CLOCK_CONTROL_1 rClockControl1;
191 DSP_CLOCK_CONTROL_2 rClockControl2;
192 DSP_ISA_SLAVE_CONTROL rSlaveControl;
193 DSP_HBRIDGE_CONTROL rHBridgeControl;
194 unsigned short ChipID = 0;
195 unsigned short tval;
196
197
198 PRINTK_2(TRACE_3780I,
199 "3780i::dsp3780I_EnableDSP entry pSettings->bDSPEnabled %x\n",
200 pSettings->bDSPEnabled);
201
202
203 if (!pSettings->bDSPEnabled) {
204 PRINTK_ERROR( KERN_ERR "3780i::dsp3780I_EnableDSP: Error: DSP not enabled. Aborting.\n" );
205 return -EIO;
206 }
207
208
209 PRINTK_2(TRACE_3780I,
210 "3780i::dsp3780i_EnableDSP entry pSettings->bModemEnabled %x\n",
211 pSettings->bModemEnabled);
212
213 if (pSettings->bModemEnabled) {
214 rUartCfg1.Reserved = rUartCfg2.Reserved = 0;
215 rUartCfg1.IrqActiveLow = pSettings->bUartIrqActiveLow;
216 rUartCfg1.IrqPulse = pSettings->bUartIrqPulse;
217 rUartCfg1.Irq =
218 (unsigned char) pIrqMap[pSettings->usUartIrq];
219 switch (pSettings->usUartBaseIO) {
220 case 0x03F8:
221 rUartCfg1.BaseIO = 0;
222 break;
223 case 0x02F8:
224 rUartCfg1.BaseIO = 1;
225 break;
226 case 0x03E8:
227 rUartCfg1.BaseIO = 2;
228 break;
229 case 0x02E8:
230 rUartCfg1.BaseIO = 3;
231 break;
232 }
233 rUartCfg2.Enable = TRUE;
234 }
235
236 rHBridgeCfg1.Reserved = rHBridgeCfg2.Reserved = 0;
237 rHBridgeCfg1.IrqActiveLow = pSettings->bDspIrqActiveLow;
238 rHBridgeCfg1.IrqPulse = pSettings->bDspIrqPulse;
239 rHBridgeCfg1.Irq = (unsigned char) pIrqMap[pSettings->usDspIrq];
240 rHBridgeCfg1.AccessMode = 1;
241 rHBridgeCfg2.Enable = TRUE;
242
243
244 rBusmasterCfg2.Reserved = 0;
245 rBusmasterCfg1.Dma = (unsigned char) pDmaMap[pSettings->usDspDma];
246 rBusmasterCfg1.NumTransfers =
247 (unsigned char) pSettings->usNumTransfers;
248 rBusmasterCfg1.ReRequest = (unsigned char) pSettings->usReRequest;
249 rBusmasterCfg1.MEMCS16 = pSettings->bEnableMEMCS16;
250 rBusmasterCfg2.IsaMemCmdWidth =
251 (unsigned char) pSettings->usIsaMemCmdWidth;
252
253
254 rIsaProtCfg.Reserved = 0;
255 rIsaProtCfg.GateIOCHRDY = pSettings->bGateIOCHRDY;
256
257 rPowerMgmtCfg.Reserved = 0;
258 rPowerMgmtCfg.Enable = pSettings->bEnablePwrMgmt;
259
260 rHBusTimerCfg.LoadValue =
261 (unsigned char) pSettings->usHBusTimerLoadValue;
262
263 rLBusTimeoutDisable.Reserved = 0;
264 rLBusTimeoutDisable.DisableTimeout =
265 pSettings->bDisableLBusTimeout;
266
267 MKWORD(rChipReset) = ~pSettings->usChipletEnable;
268
269 rClockControl1.Reserved1 = rClockControl1.Reserved2 = 0;
270 rClockControl1.N_Divisor = pSettings->usN_Divisor;
271 rClockControl1.M_Multiplier = pSettings->usM_Multiplier;
272
273 rClockControl2.Reserved = 0;
274 rClockControl2.PllBypass = pSettings->bPllBypass;
275
276 /* Issue a soft reset to the chip */
277 /* Note: Since we may be coming in with 3780i clocks suspended, we must keep
278 * soft-reset active for 10ms.
279 */
280 rSlaveControl.ClockControl = 0;
281 rSlaveControl.SoftReset = TRUE;
282 rSlaveControl.ConfigMode = FALSE;
283 rSlaveControl.Reserved = 0;
284
285 PRINTK_4(TRACE_3780I,
286 "3780i::dsp3780i_EnableDSP usDspBaseIO %x index %x taddr %x\n",
287 usDspBaseIO, DSP_IsaSlaveControl,
288 usDspBaseIO + DSP_IsaSlaveControl);
289
290 PRINTK_2(TRACE_3780I,
291 "3780i::dsp3780i_EnableDSP rSlaveContrl %x\n",
292 MKWORD(rSlaveControl));
293
294 spin_lock_irqsave(&dsp_lock, flags);
295 OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
296 MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl);
297
298 PRINTK_2(TRACE_3780I,
299 "3780i::dsp3780i_EnableDSP rSlaveControl 2 %x\n", tval);
300
301
302 for (i = 0; i < 11; i++)
303 udelay(2000);
304
305 rSlaveControl.SoftReset = FALSE;
306 OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
307
308 MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl);
309
310 PRINTK_2(TRACE_3780I,
311 "3780i::dsp3780i_EnableDSP rSlaveControl 3 %x\n", tval);
312
313
314 /* Program our general configuration registers */
315 WriteGenCfg(DSP_HBridgeCfg1Index, MKBYTE(rHBridgeCfg1));
316 WriteGenCfg(DSP_HBridgeCfg2Index, MKBYTE(rHBridgeCfg2));
317 WriteGenCfg(DSP_BusMasterCfg1Index, MKBYTE(rBusmasterCfg1));
318 WriteGenCfg(DSP_BusMasterCfg2Index, MKBYTE(rBusmasterCfg2));
319 WriteGenCfg(DSP_IsaProtCfgIndex, MKBYTE(rIsaProtCfg));
320 WriteGenCfg(DSP_PowerMgCfgIndex, MKBYTE(rPowerMgmtCfg));
321 WriteGenCfg(DSP_HBusTimerCfgIndex, MKBYTE(rHBusTimerCfg));
322
323 if (pSettings->bModemEnabled) {
324 WriteGenCfg(DSP_UartCfg1Index, MKBYTE(rUartCfg1));
325 WriteGenCfg(DSP_UartCfg2Index, MKBYTE(rUartCfg2));
326 }
327
328
329 rHBridgeControl.EnableDspInt = FALSE;
330 rHBridgeControl.MemAutoInc = TRUE;
331 rHBridgeControl.IoAutoInc = FALSE;
332 rHBridgeControl.DiagnosticMode = FALSE;
333
334 PRINTK_3(TRACE_3780I,
335 "3780i::dsp3780i_EnableDSP DSP_HBridgeControl %x rHBridgeControl %x\n",
336 DSP_HBridgeControl, MKWORD(rHBridgeControl));
337
338 OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
339 spin_unlock_irqrestore(&dsp_lock, flags);
340 WriteMsaCfg(DSP_LBusTimeoutDisable, MKWORD(rLBusTimeoutDisable));
341 WriteMsaCfg(DSP_ClockControl_1, MKWORD(rClockControl1));
342 WriteMsaCfg(DSP_ClockControl_2, MKWORD(rClockControl2));
343 WriteMsaCfg(DSP_ChipReset, MKWORD(rChipReset));
344
345 ChipID = ReadMsaCfg(DSP_ChipID);
346
347 PRINTK_2(TRACE_3780I,
348 "3780i::dsp3780I_EnableDSP exiting bRC=TRUE, ChipID %x\n",
349 ChipID);
350
351 return 0;
352}
353
354int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings)
355{
356 unsigned short usDspBaseIO = pSettings->usDspBaseIO;
357 DSP_ISA_SLAVE_CONTROL rSlaveControl;
358
359
360 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP entry\n");
361
362 rSlaveControl.ClockControl = 0;
363 rSlaveControl.SoftReset = TRUE;
364 rSlaveControl.ConfigMode = FALSE;
365 rSlaveControl.Reserved = 0;
366 spin_lock_irqsave(&dsp_lock, flags);
367 OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
368
369 udelay(5);
370
371 rSlaveControl.ClockControl = 1;
372 OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
373 spin_unlock_irqrestore(&dsp_lock, flags);
374
375 udelay(5);
376
377
378 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP exit\n");
379
380 return 0;
381}
382
383int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings)
384{
385 unsigned short usDspBaseIO = pSettings->usDspBaseIO;
386 DSP_BOOT_DOMAIN rBootDomain;
387 DSP_HBRIDGE_CONTROL rHBridgeControl;
388
389
390 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset entry\n");
391
392 spin_lock_irqsave(&dsp_lock, flags);
393 /* Mask DSP to PC interrupt */
394 MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
395
396 PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rHBridgeControl %x\n",
397 MKWORD(rHBridgeControl));
398
399 rHBridgeControl.EnableDspInt = FALSE;
400 OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
401 spin_unlock_irqrestore(&dsp_lock, flags);
402
403 /* Reset the core via the boot domain register */
404 rBootDomain.ResetCore = TRUE;
405 rBootDomain.Halt = TRUE;
406 rBootDomain.NMI = TRUE;
407 rBootDomain.Reserved = 0;
408
409 PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rBootDomain %x\n",
410 MKWORD(rBootDomain));
411
412 WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
413
414 /* Reset all the chiplets and then reactivate them */
415 WriteMsaCfg(DSP_ChipReset, 0xFFFF);
416 udelay(5);
417 WriteMsaCfg(DSP_ChipReset,
418 (unsigned short) (~pSettings->usChipletEnable));
419
420
421 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset exit bRC=0\n");
422
423 return 0;
424}
425
426
427int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings)
428{
429 unsigned short usDspBaseIO = pSettings->usDspBaseIO;
430 DSP_BOOT_DOMAIN rBootDomain;
431 DSP_HBRIDGE_CONTROL rHBridgeControl;
432
433
434 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run entry\n");
435
436
437 /* Transition the core to a running state */
438 rBootDomain.ResetCore = TRUE;
439 rBootDomain.Halt = FALSE;
440 rBootDomain.NMI = TRUE;
441 rBootDomain.Reserved = 0;
442 WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
443
444 udelay(5);
445
446 rBootDomain.ResetCore = FALSE;
447 WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
448 udelay(5);
449
450 rBootDomain.NMI = FALSE;
451 WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
452 udelay(5);
453
454 /* Enable DSP to PC interrupt */
455 spin_lock_irqsave(&dsp_lock, flags);
456 MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
457 rHBridgeControl.EnableDspInt = TRUE;
458
459 PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Run rHBridgeControl %x\n",
460 MKWORD(rHBridgeControl));
461
462 OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
463 spin_unlock_irqrestore(&dsp_lock, flags);
464
465
466 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run exit bRC=TRUE\n");
467
468 return 0;
469}
470
471
472int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
473 unsigned uCount, unsigned long ulDSPAddr)
474{
475 unsigned short __user *pusBuffer = pvBuffer;
476 unsigned short val;
477
478
479 PRINTK_5(TRACE_3780I,
480 "3780i::dsp3780I_ReadDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
481 usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
482
483
484 /* Set the initial MSA address. No adjustments need to be made to data store addresses */
485 spin_lock_irqsave(&dsp_lock, flags);
486 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
487 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
488 spin_unlock_irqrestore(&dsp_lock, flags);
489
490 /* Transfer the memory block */
491 while (uCount-- != 0) {
492 spin_lock_irqsave(&dsp_lock, flags);
493 val = InWordDsp(DSP_MsaDataDSISHigh);
494 spin_unlock_irqrestore(&dsp_lock, flags);
495 if(put_user(val, pusBuffer++))
496 return -EFAULT;
497
498 PRINTK_3(TRACE_3780I,
499 "3780I::dsp3780I_ReadDStore uCount %x val %x\n",
500 uCount, val);
501
502 PaceMsaAccess(usDspBaseIO);
503 }
504
505
506 PRINTK_1(TRACE_3780I,
507 "3780I::dsp3780I_ReadDStore exit bRC=TRUE\n");
508
509 return 0;
510}
511
512int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO,
513 void __user *pvBuffer, unsigned uCount,
514 unsigned long ulDSPAddr)
515{
516 unsigned short __user *pusBuffer = pvBuffer;
517 unsigned short val;
518
519
520 PRINTK_5(TRACE_3780I,
521 "3780i::dsp3780I_ReadAndDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
522 usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
523
524
525 /* Set the initial MSA address. No adjustments need to be made to data store addresses */
526 spin_lock_irqsave(&dsp_lock, flags);
527 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
528 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
529 spin_unlock_irqrestore(&dsp_lock, flags);
530
531 /* Transfer the memory block */
532 while (uCount-- != 0) {
533 spin_lock_irqsave(&dsp_lock, flags);
534 val = InWordDsp(DSP_ReadAndClear);
535 spin_unlock_irqrestore(&dsp_lock, flags);
536 if(put_user(val, pusBuffer++))
537 return -EFAULT;
538
539 PRINTK_3(TRACE_3780I,
540 "3780I::dsp3780I_ReadAndCleanDStore uCount %x val %x\n",
541 uCount, val);
542
543 PaceMsaAccess(usDspBaseIO);
544 }
545
546
547 PRINTK_1(TRACE_3780I,
548 "3780I::dsp3780I_ReadAndClearDStore exit bRC=TRUE\n");
549
550 return 0;
551}
552
553
554int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
555 unsigned uCount, unsigned long ulDSPAddr)
556{
557 unsigned short __user *pusBuffer = pvBuffer;
558
559
560 PRINTK_5(TRACE_3780I,
561 "3780i::dsp3780D_WriteDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
562 usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
563
564
565 /* Set the initial MSA address. No adjustments need to be made to data store addresses */
566 spin_lock_irqsave(&dsp_lock, flags);
567 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
568 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
569 spin_unlock_irqrestore(&dsp_lock, flags);
570
571 /* Transfer the memory block */
572 while (uCount-- != 0) {
573 unsigned short val;
574 if(get_user(val, pusBuffer++))
575 return -EFAULT;
576 spin_lock_irqsave(&dsp_lock, flags);
577 OutWordDsp(DSP_MsaDataDSISHigh, val);
578 spin_unlock_irqrestore(&dsp_lock, flags);
579
580 PRINTK_3(TRACE_3780I,
581 "3780I::dsp3780I_WriteDStore uCount %x val %x\n",
582 uCount, val);
583
584 PaceMsaAccess(usDspBaseIO);
585 }
586
587
588 PRINTK_1(TRACE_3780I,
589 "3780I::dsp3780D_WriteDStore exit bRC=TRUE\n");
590
591 return 0;
592}
593
594
595int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
596 unsigned uCount, unsigned long ulDSPAddr)
597{
598 unsigned short __user *pusBuffer = pvBuffer;
599
600 PRINTK_5(TRACE_3780I,
601 "3780i::dsp3780I_ReadIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
602 usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
603
604 /*
605 * Set the initial MSA address. To convert from an instruction store
606 * address to an MSA address
607 * shift the address two bits to the left and set bit 22
608 */
609 ulDSPAddr = (ulDSPAddr << 2) | (1 << 22);
610 spin_lock_irqsave(&dsp_lock, flags);
611 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
612 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
613 spin_unlock_irqrestore(&dsp_lock, flags);
614
615 /* Transfer the memory block */
616 while (uCount-- != 0) {
617 unsigned short val_lo, val_hi;
618 spin_lock_irqsave(&dsp_lock, flags);
619 val_lo = InWordDsp(DSP_MsaDataISLow);
620 val_hi = InWordDsp(DSP_MsaDataDSISHigh);
621 spin_unlock_irqrestore(&dsp_lock, flags);
622 if(put_user(val_lo, pusBuffer++))
623 return -EFAULT;
624 if(put_user(val_hi, pusBuffer++))
625 return -EFAULT;
626
627 PRINTK_4(TRACE_3780I,
628 "3780I::dsp3780I_ReadIStore uCount %x val_lo %x val_hi %x\n",
629 uCount, val_lo, val_hi);
630
631 PaceMsaAccess(usDspBaseIO);
632
633 }
634
635 PRINTK_1(TRACE_3780I,
636 "3780I::dsp3780I_ReadIStore exit bRC=TRUE\n");
637
638 return 0;
639}
640
641
642int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
643 unsigned uCount, unsigned long ulDSPAddr)
644{
645 unsigned short __user *pusBuffer = pvBuffer;
646
647 PRINTK_5(TRACE_3780I,
648 "3780i::dsp3780I_WriteIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
649 usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
650
651
652 /*
653 * Set the initial MSA address. To convert from an instruction store
654 * address to an MSA address
655 * shift the address two bits to the left and set bit 22
656 */
657 ulDSPAddr = (ulDSPAddr << 2) | (1 << 22);
658 spin_lock_irqsave(&dsp_lock, flags);
659 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
660 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
661 spin_unlock_irqrestore(&dsp_lock, flags);
662
663 /* Transfer the memory block */
664 while (uCount-- != 0) {
665 unsigned short val_lo, val_hi;
666 if(get_user(val_lo, pusBuffer++))
667 return -EFAULT;
668 if(get_user(val_hi, pusBuffer++))
669 return -EFAULT;
670 spin_lock_irqsave(&dsp_lock, flags);
671 OutWordDsp(DSP_MsaDataISLow, val_lo);
672 OutWordDsp(DSP_MsaDataDSISHigh, val_hi);
673 spin_unlock_irqrestore(&dsp_lock, flags);
674
675 PRINTK_4(TRACE_3780I,
676 "3780I::dsp3780I_WriteIStore uCount %x val_lo %x val_hi %x\n",
677 uCount, val_lo, val_hi);
678
679 PaceMsaAccess(usDspBaseIO);
680
681 }
682
683 PRINTK_1(TRACE_3780I,
684 "3780I::dsp3780I_WriteIStore exit bRC=TRUE\n");
685
686 return 0;
687}
688
689
690int dsp3780I_GetIPCSource(unsigned short usDspBaseIO,
691 unsigned short *pusIPCSource)
692{
693 DSP_HBRIDGE_CONTROL rHBridgeControl;
694 unsigned short temp;
695
696
697 PRINTK_3(TRACE_3780I,
698 "3780i::dsp3780I_GetIPCSource entry usDspBaseIO %x pusIPCSource %p\n",
699 usDspBaseIO, pusIPCSource);
700
701 /*
702 * Disable DSP to PC interrupts, read the interrupt register,
703 * clear the pending IPC bits, and reenable DSP to PC interrupts
704 */
705 spin_lock_irqsave(&dsp_lock, flags);
706 MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
707 rHBridgeControl.EnableDspInt = FALSE;
708 OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
709
710 *pusIPCSource = InWordDsp(DSP_Interrupt);
711 temp = (unsigned short) ~(*pusIPCSource);
712
713 PRINTK_3(TRACE_3780I,
714 "3780i::dsp3780I_GetIPCSource, usIPCSource %x ~ %x\n",
715 *pusIPCSource, temp);
716
717 OutWordDsp(DSP_Interrupt, (unsigned short) ~(*pusIPCSource));
718
719 rHBridgeControl.EnableDspInt = TRUE;
720 OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
721 spin_unlock_irqrestore(&dsp_lock, flags);
722
723
724 PRINTK_2(TRACE_3780I,
725 "3780i::dsp3780I_GetIPCSource exit usIPCSource %x\n",
726 *pusIPCSource);
727
728 return 0;
729}