Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* head-uc-fr401.S: FR401/3/5 uc-linux specific bits of initialisation |
| 2 | * |
| 3 | * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. |
| 4 | * Written by David Howells (dhowells@redhat.com) |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the License, or (at your option) any later version. |
| 10 | */ |
| 11 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | #include <linux/threads.h> |
| 13 | #include <linux/linkage.h> |
| 14 | #include <asm/ptrace.h> |
| 15 | #include <asm/page.h> |
| 16 | #include <asm/spr-regs.h> |
| 17 | #include <asm/mb86943a.h> |
| 18 | #include "head.inc" |
| 19 | |
| 20 | |
| 21 | #define __400_DBR0 0xfe000e00 |
| 22 | #define __400_DBR1 0xfe000e08 |
| 23 | #define __400_DBR2 0xfe000e10 /* not on FR401 */ |
| 24 | #define __400_DBR3 0xfe000e18 /* not on FR401 */ |
| 25 | #define __400_DAM0 0xfe000f00 |
| 26 | #define __400_DAM1 0xfe000f08 |
| 27 | #define __400_DAM2 0xfe000f10 /* not on FR401 */ |
| 28 | #define __400_DAM3 0xfe000f18 /* not on FR401 */ |
| 29 | #define __400_LGCR 0xfe000010 |
| 30 | #define __400_LCR 0xfe000100 |
| 31 | #define __400_LSBR 0xfe000c00 |
| 32 | |
| 33 | .section .text.init,"ax" |
| 34 | .balign 4 |
| 35 | |
| 36 | ############################################################################### |
| 37 | # |
| 38 | # describe the position and layout of the SDRAM controller registers |
| 39 | # |
| 40 | # ENTRY: EXIT: |
| 41 | # GR5 - cacheline size |
| 42 | # GR11 - displacement of 2nd SDRAM addr reg from GR14 |
| 43 | # GR12 - displacement of 3rd SDRAM addr reg from GR14 |
| 44 | # GR13 - displacement of 4th SDRAM addr reg from GR14 |
| 45 | # GR14 - address of 1st SDRAM addr reg |
| 46 | # GR15 - amount to shift address by to match SDRAM addr reg |
| 47 | # GR26 &__head_reference [saved] |
| 48 | # GR30 LED address [saved] |
| 49 | # CC0 - T if DBR0 is present |
| 50 | # CC1 - T if DBR1 is present |
| 51 | # CC2 - T if DBR2 is present (not FR401/FR401A) |
| 52 | # CC3 - T if DBR3 is present (not FR401/FR401A) |
| 53 | # |
| 54 | ############################################################################### |
| 55 | .globl __head_fr401_describe_sdram |
| 56 | __head_fr401_describe_sdram: |
| 57 | sethi.p %hi(__400_DBR0),gr14 |
| 58 | setlo %lo(__400_DBR0),gr14 |
| 59 | setlos.p #__400_DBR1-__400_DBR0,gr11 |
| 60 | setlos #__400_DBR2-__400_DBR0,gr12 |
| 61 | setlos.p #__400_DBR3-__400_DBR0,gr13 |
| 62 | setlos #32,gr5 ; cacheline size |
| 63 | setlos.p #0,gr15 ; amount to shift addr reg by |
| 64 | |
| 65 | # specify which DBR regs are present |
| 66 | setlos #0x00ff,gr4 |
| 67 | movgs gr4,cccr |
| 68 | movsg psr,gr3 ; check for FR401/FR401A |
| 69 | srli gr3,#25,gr3 |
| 70 | subicc gr3,#0x20>>1,gr0,icc0 |
| 71 | bnelr icc0,#1 |
| 72 | setlos #0x000f,gr4 |
| 73 | movgs gr4,cccr |
| 74 | bralr |
| 75 | |
| 76 | ############################################################################### |
| 77 | # |
| 78 | # rearrange the bus controller registers |
| 79 | # |
| 80 | # ENTRY: EXIT: |
| 81 | # GR26 &__head_reference [saved] |
| 82 | # GR30 LED address revised LED address |
| 83 | # |
| 84 | ############################################################################### |
| 85 | .globl __head_fr401_set_busctl |
| 86 | __head_fr401_set_busctl: |
| 87 | sethi.p %hi(__400_LGCR),gr4 |
| 88 | setlo %lo(__400_LGCR),gr4 |
| 89 | sethi.p %hi(__400_LSBR),gr10 |
| 90 | setlo %lo(__400_LSBR),gr10 |
| 91 | sethi.p %hi(__400_LCR),gr11 |
| 92 | setlo %lo(__400_LCR),gr11 |
| 93 | |
| 94 | # set the bus controller |
| 95 | ldi @(gr4,#0),gr5 |
| 96 | ori gr5,#0xff,gr5 ; make sure all chip-selects are enabled |
| 97 | sti gr5,@(gr4,#0) |
| 98 | |
| 99 | sethi.p %hi(__region_CS1),gr4 |
| 100 | setlo %lo(__region_CS1),gr4 |
| 101 | sethi.p %hi(__region_CS1_M),gr5 |
| 102 | setlo %lo(__region_CS1_M),gr5 |
| 103 | sethi.p %hi(__region_CS1_C),gr6 |
| 104 | setlo %lo(__region_CS1_C),gr6 |
| 105 | sti gr4,@(gr10,#1*0x08) |
| 106 | sti gr5,@(gr10,#1*0x08+0x100) |
| 107 | sti gr6,@(gr11,#1*0x08) |
| 108 | sethi.p %hi(__region_CS2),gr4 |
| 109 | setlo %lo(__region_CS2),gr4 |
| 110 | sethi.p %hi(__region_CS2_M),gr5 |
| 111 | setlo %lo(__region_CS2_M),gr5 |
| 112 | sethi.p %hi(__region_CS2_C),gr6 |
| 113 | setlo %lo(__region_CS2_C),gr6 |
| 114 | sti gr4,@(gr10,#2*0x08) |
| 115 | sti gr5,@(gr10,#2*0x08+0x100) |
| 116 | sti gr6,@(gr11,#2*0x08) |
| 117 | sethi.p %hi(__region_CS3),gr4 |
| 118 | setlo %lo(__region_CS3),gr4 |
| 119 | sethi.p %hi(__region_CS3_M),gr5 |
| 120 | setlo %lo(__region_CS3_M),gr5 |
| 121 | sethi.p %hi(__region_CS3_C),gr6 |
| 122 | setlo %lo(__region_CS3_C),gr6 |
| 123 | sti gr4,@(gr10,#3*0x08) |
| 124 | sti gr5,@(gr10,#3*0x08+0x100) |
| 125 | sti gr6,@(gr11,#3*0x08) |
| 126 | sethi.p %hi(__region_CS4),gr4 |
| 127 | setlo %lo(__region_CS4),gr4 |
| 128 | sethi.p %hi(__region_CS4_M),gr5 |
| 129 | setlo %lo(__region_CS4_M),gr5 |
| 130 | sethi.p %hi(__region_CS4_C),gr6 |
| 131 | setlo %lo(__region_CS4_C),gr6 |
| 132 | sti gr4,@(gr10,#4*0x08) |
| 133 | sti gr5,@(gr10,#4*0x08+0x100) |
| 134 | sti gr6,@(gr11,#4*0x08) |
| 135 | sethi.p %hi(__region_CS5),gr4 |
| 136 | setlo %lo(__region_CS5),gr4 |
| 137 | sethi.p %hi(__region_CS5_M),gr5 |
| 138 | setlo %lo(__region_CS5_M),gr5 |
| 139 | sethi.p %hi(__region_CS5_C),gr6 |
| 140 | setlo %lo(__region_CS5_C),gr6 |
| 141 | sti gr4,@(gr10,#5*0x08) |
| 142 | sti gr5,@(gr10,#5*0x08+0x100) |
| 143 | sti gr6,@(gr11,#5*0x08) |
| 144 | sethi.p %hi(__region_CS6),gr4 |
| 145 | setlo %lo(__region_CS6),gr4 |
| 146 | sethi.p %hi(__region_CS6_M),gr5 |
| 147 | setlo %lo(__region_CS6_M),gr5 |
| 148 | sethi.p %hi(__region_CS6_C),gr6 |
| 149 | setlo %lo(__region_CS6_C),gr6 |
| 150 | sti gr4,@(gr10,#6*0x08) |
| 151 | sti gr5,@(gr10,#6*0x08+0x100) |
| 152 | sti gr6,@(gr11,#6*0x08) |
| 153 | sethi.p %hi(__region_CS7),gr4 |
| 154 | setlo %lo(__region_CS7),gr4 |
| 155 | sethi.p %hi(__region_CS7_M),gr5 |
| 156 | setlo %lo(__region_CS7_M),gr5 |
| 157 | sethi.p %hi(__region_CS7_C),gr6 |
| 158 | setlo %lo(__region_CS7_C),gr6 |
| 159 | sti gr4,@(gr10,#7*0x08) |
| 160 | sti gr5,@(gr10,#7*0x08+0x100) |
| 161 | sti gr6,@(gr11,#7*0x08) |
| 162 | membar |
| 163 | bar |
| 164 | |
| 165 | # adjust LED bank address |
| 166 | sethi.p %hi(LED_ADDR - 0x20000000 +__region_CS2),gr30 |
| 167 | setlo %lo(LED_ADDR - 0x20000000 +__region_CS2),gr30 |
| 168 | bralr |
| 169 | |
| 170 | ############################################################################### |
| 171 | # |
| 172 | # determine the total SDRAM size |
| 173 | # |
| 174 | # ENTRY: EXIT: |
| 175 | # GR25 - SDRAM size |
| 176 | # GR26 &__head_reference [saved] |
| 177 | # GR30 LED address [saved] |
| 178 | # |
| 179 | ############################################################################### |
| 180 | .globl __head_fr401_survey_sdram |
| 181 | __head_fr401_survey_sdram: |
| 182 | sethi.p %hi(__400_DAM0),gr11 |
| 183 | setlo %lo(__400_DAM0),gr11 |
| 184 | sethi.p %hi(__400_DBR0),gr12 |
| 185 | setlo %lo(__400_DBR0),gr12 |
| 186 | |
| 187 | sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value |
| 188 | setlo %lo(0xfe000000),gr17 |
| 189 | setlos #0,gr25 |
| 190 | |
| 191 | ldi @(gr12,#0x00),gr4 ; DAR0 |
| 192 | subcc gr4,gr17,gr0,icc0 |
| 193 | beq icc0,#0,__head_no_DCS0 |
| 194 | ldi @(gr11,#0x00),gr6 ; DAM0: bits 31:20 match addr 31:20 |
| 195 | add gr25,gr6,gr25 |
| 196 | addi gr25,#1,gr25 |
| 197 | __head_no_DCS0: |
| 198 | |
| 199 | ldi @(gr12,#0x08),gr4 ; DAR1 |
| 200 | subcc gr4,gr17,gr0,icc0 |
| 201 | beq icc0,#0,__head_no_DCS1 |
| 202 | ldi @(gr11,#0x08),gr6 ; DAM1: bits 31:20 match addr 31:20 |
| 203 | add gr25,gr6,gr25 |
| 204 | addi gr25,#1,gr25 |
| 205 | __head_no_DCS1: |
| 206 | |
| 207 | # FR401/FR401A does not have DCS2/3 |
| 208 | movsg psr,gr3 |
| 209 | srli gr3,#25,gr3 |
| 210 | subicc gr3,#0x20>>1,gr0,icc0 |
| 211 | beq icc0,#0,__head_no_DCS3 |
| 212 | |
| 213 | ldi @(gr12,#0x10),gr4 ; DAR2 |
| 214 | subcc gr4,gr17,gr0,icc0 |
| 215 | beq icc0,#0,__head_no_DCS2 |
| 216 | ldi @(gr11,#0x10),gr6 ; DAM2: bits 31:20 match addr 31:20 |
| 217 | add gr25,gr6,gr25 |
| 218 | addi gr25,#1,gr25 |
| 219 | __head_no_DCS2: |
| 220 | |
| 221 | ldi @(gr12,#0x18),gr4 ; DAR3 |
| 222 | subcc gr4,gr17,gr0,icc0 |
| 223 | beq icc0,#0,__head_no_DCS3 |
| 224 | ldi @(gr11,#0x18),gr6 ; DAM3: bits 31:20 match addr 31:20 |
| 225 | add gr25,gr6,gr25 |
| 226 | addi gr25,#1,gr25 |
| 227 | __head_no_DCS3: |
| 228 | bralr |
| 229 | |
| 230 | ############################################################################### |
| 231 | # |
| 232 | # set the protection map with the I/DAMPR registers |
| 233 | # |
| 234 | # ENTRY: EXIT: |
| 235 | # GR25 SDRAM size [saved] |
| 236 | # GR26 &__head_reference [saved] |
| 237 | # GR30 LED address [saved] |
| 238 | # |
| 239 | ############################################################################### |
| 240 | .globl __head_fr401_set_protection |
| 241 | __head_fr401_set_protection: |
| 242 | movsg lr,gr27 |
| 243 | |
| 244 | # set the I/O region protection registers for FR401/3/5 |
| 245 | sethi.p %hi(__region_IO),gr5 |
| 246 | setlo %lo(__region_IO),gr5 |
| 247 | ori gr5,#xAMPRx_SS_512Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr5 |
| 248 | movgs gr0,iampr7 |
| 249 | movgs gr5,dampr7 ; General I/O tile |
| 250 | |
| 251 | # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible |
| 252 | # - start with the highest numbered registers |
| 253 | sethi.p %hi(__kernel_image_end),gr8 |
| 254 | setlo %lo(__kernel_image_end),gr8 |
| 255 | sethi.p %hi(32768),gr4 ; allow for a maximal allocator bitmap |
| 256 | setlo %lo(32768),gr4 |
| 257 | add gr8,gr4,gr8 |
| 258 | sethi.p %hi(1024*2048-1),gr4 ; round up to nearest 2MiB |
| 259 | setlo %lo(1024*2048-1),gr4 |
| 260 | add.p gr8,gr4,gr8 |
| 261 | not gr4,gr4 |
| 262 | and gr8,gr4,gr8 |
| 263 | |
| 264 | sethi.p %hi(__page_offset),gr9 |
| 265 | setlo %lo(__page_offset),gr9 |
| 266 | add gr9,gr25,gr9 |
| 267 | |
| 268 | # GR8 = base of uncovered RAM |
| 269 | # GR9 = top of uncovered RAM |
| 270 | |
| 271 | #ifdef CONFIG_MB93093_PDK |
| 272 | sethi.p %hi(__region_CS2),gr4 |
| 273 | setlo %lo(__region_CS2),gr4 |
| 274 | ori gr4,#xAMPRx_SS_1Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr4 |
| 275 | movgs gr4,dampr6 |
| 276 | movgs gr0,iampr6 |
| 277 | #else |
| 278 | call __head_split_region |
| 279 | movgs gr4,iampr6 |
| 280 | movgs gr5,dampr6 |
| 281 | #endif |
| 282 | call __head_split_region |
| 283 | movgs gr4,iampr5 |
| 284 | movgs gr5,dampr5 |
| 285 | call __head_split_region |
| 286 | movgs gr4,iampr4 |
| 287 | movgs gr5,dampr4 |
| 288 | call __head_split_region |
| 289 | movgs gr4,iampr3 |
| 290 | movgs gr5,dampr3 |
| 291 | call __head_split_region |
| 292 | movgs gr4,iampr2 |
| 293 | movgs gr5,dampr2 |
| 294 | call __head_split_region |
| 295 | movgs gr4,iampr1 |
| 296 | movgs gr5,dampr1 |
| 297 | |
| 298 | # cover kernel core image with kernel-only segment |
| 299 | sethi.p %hi(__page_offset),gr8 |
| 300 | setlo %lo(__page_offset),gr8 |
| 301 | call __head_split_region |
| 302 | |
| 303 | #ifdef CONFIG_PROTECT_KERNEL |
| 304 | ori.p gr4,#xAMPRx_S_KERNEL,gr4 |
| 305 | ori gr5,#xAMPRx_S_KERNEL,gr5 |
| 306 | #endif |
| 307 | |
| 308 | movgs gr4,iampr0 |
| 309 | movgs gr5,dampr0 |
| 310 | jmpl @(gr27,gr0) |