Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * net/dsa/mv88e6123_61_65.c - Marvell 88e6123/6161/6165 switch chip support |
| 3 | * Copyright (c) 2008 Marvell Semiconductor |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/list.h> |
| 12 | #include <linux/netdevice.h> |
| 13 | #include <linux/phy.h> |
| 14 | #include "dsa_priv.h" |
| 15 | #include "mv88e6xxx.h" |
| 16 | |
| 17 | static char *mv88e6123_61_65_probe(struct mii_bus *bus, int sw_addr) |
| 18 | { |
| 19 | int ret; |
| 20 | |
| 21 | ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03); |
| 22 | if (ret >= 0) { |
| 23 | ret &= 0xfff0; |
| 24 | if (ret == 0x1210) |
| 25 | return "Marvell 88E6123"; |
| 26 | if (ret == 0x1610) |
| 27 | return "Marvell 88E6161"; |
| 28 | if (ret == 0x1650) |
| 29 | return "Marvell 88E6165"; |
| 30 | } |
| 31 | |
| 32 | return NULL; |
| 33 | } |
| 34 | |
| 35 | static int mv88e6123_61_65_switch_reset(struct dsa_switch *ds) |
| 36 | { |
| 37 | int i; |
| 38 | int ret; |
| 39 | |
| 40 | /* |
| 41 | * Set all ports to the disabled state. |
| 42 | */ |
| 43 | for (i = 0; i < 8; i++) { |
| 44 | ret = REG_READ(REG_PORT(i), 0x04); |
| 45 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); |
| 46 | } |
| 47 | |
| 48 | /* |
| 49 | * Wait for transmit queues to drain. |
| 50 | */ |
| 51 | msleep(2); |
| 52 | |
| 53 | /* |
| 54 | * Reset the switch. |
| 55 | */ |
| 56 | REG_WRITE(REG_GLOBAL, 0x04, 0xc400); |
| 57 | |
| 58 | /* |
| 59 | * Wait up to one second for reset to complete. |
| 60 | */ |
| 61 | for (i = 0; i < 1000; i++) { |
| 62 | ret = REG_READ(REG_GLOBAL, 0x00); |
| 63 | if ((ret & 0xc800) == 0xc800) |
| 64 | break; |
| 65 | |
| 66 | msleep(1); |
| 67 | } |
| 68 | if (i == 1000) |
| 69 | return -ETIMEDOUT; |
| 70 | |
| 71 | return 0; |
| 72 | } |
| 73 | |
| 74 | static int mv88e6123_61_65_setup_global(struct dsa_switch *ds) |
| 75 | { |
| 76 | int ret; |
| 77 | int i; |
| 78 | |
| 79 | /* |
| 80 | * Disable the PHY polling unit (since there won't be any |
| 81 | * external PHYs to poll), don't discard packets with |
| 82 | * excessive collisions, and mask all interrupt sources. |
| 83 | */ |
| 84 | REG_WRITE(REG_GLOBAL, 0x04, 0x0000); |
| 85 | |
| 86 | /* |
| 87 | * Set the default address aging time to 5 minutes, and |
| 88 | * enable address learn messages to be sent to all message |
| 89 | * ports. |
| 90 | */ |
| 91 | REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); |
| 92 | |
| 93 | /* |
| 94 | * Configure the priority mapping registers. |
| 95 | */ |
| 96 | ret = mv88e6xxx_config_prio(ds); |
| 97 | if (ret < 0) |
| 98 | return ret; |
| 99 | |
| 100 | /* |
| 101 | * Configure the cpu port, and configure the cpu port as the |
| 102 | * port to which ingress and egress monitor frames are to be |
| 103 | * sent. |
| 104 | */ |
| 105 | REG_WRITE(REG_GLOBAL, 0x1a, (ds->cpu_port * 0x1110)); |
| 106 | |
| 107 | /* |
| 108 | * Disable remote management for now, and set the switch's |
| 109 | * DSA device number to zero. |
| 110 | */ |
| 111 | REG_WRITE(REG_GLOBAL, 0x1c, 0x0000); |
| 112 | |
| 113 | /* |
| 114 | * Send all frames with destination addresses matching |
| 115 | * 01:80:c2:00:00:2x to the CPU port. |
| 116 | */ |
| 117 | REG_WRITE(REG_GLOBAL2, 0x02, 0xffff); |
| 118 | |
| 119 | /* |
| 120 | * Send all frames with destination addresses matching |
| 121 | * 01:80:c2:00:00:0x to the CPU port. |
| 122 | */ |
| 123 | REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); |
| 124 | |
| 125 | /* |
| 126 | * Disable the loopback filter, disable flow control |
| 127 | * messages, disable flood broadcast override, disable |
| 128 | * removing of provider tags, disable ATU age violation |
| 129 | * interrupts, disable tag flow control, force flow |
| 130 | * control priority to the highest, and send all special |
| 131 | * multicast frames to the CPU at the highest priority. |
| 132 | */ |
| 133 | REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); |
| 134 | |
| 135 | /* |
| 136 | * Map all DSA device IDs to the CPU port. |
| 137 | */ |
| 138 | for (i = 0; i < 32; i++) |
| 139 | REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | ds->cpu_port); |
| 140 | |
| 141 | /* |
| 142 | * Clear all trunk masks. |
| 143 | */ |
| 144 | for (i = 0; i < 8; i++) |
| 145 | REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff); |
| 146 | |
| 147 | /* |
| 148 | * Clear all trunk mappings. |
| 149 | */ |
| 150 | for (i = 0; i < 16; i++) |
| 151 | REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11)); |
| 152 | |
| 153 | /* |
| 154 | * Disable ingress rate limiting by resetting all ingress |
| 155 | * rate limit registers to their initial state. |
| 156 | */ |
| 157 | for (i = 0; i < 6; i++) |
| 158 | REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8)); |
| 159 | |
| 160 | /* |
| 161 | * Initialise cross-chip port VLAN table to reset defaults. |
| 162 | */ |
| 163 | REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000); |
| 164 | |
| 165 | /* |
| 166 | * Clear the priority override table. |
| 167 | */ |
| 168 | for (i = 0; i < 16; i++) |
| 169 | REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8)); |
| 170 | |
| 171 | /* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */ |
| 172 | |
| 173 | return 0; |
| 174 | } |
| 175 | |
| 176 | static int mv88e6123_61_65_setup_port(struct dsa_switch *ds, int p) |
| 177 | { |
| 178 | int addr = REG_PORT(p); |
| 179 | |
| 180 | /* |
| 181 | * MAC Forcing register: don't force link, speed, duplex |
| 182 | * or flow control state to any particular values. |
| 183 | */ |
| 184 | REG_WRITE(addr, 0x01, 0x0003); |
| 185 | |
| 186 | /* |
| 187 | * Do not limit the period of time that this port can be |
| 188 | * paused for by the remote end or the period of time that |
| 189 | * this port can pause the remote end. |
| 190 | */ |
| 191 | REG_WRITE(addr, 0x02, 0x0000); |
| 192 | |
| 193 | /* |
| 194 | * Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, |
Lennert Buytenhek | cf85d08 | 2008-10-07 13:45:02 +0000 | [diff] [blame] | 195 | * configure the requested (DSA/EDSA) tagging mode if this is |
| 196 | * the CPU port, disable Header mode, enable IGMP/MLD snooping, |
| 197 | * disable VLAN tunneling, determine priority by looking at |
| 198 | * 802.1p and IP priority fields (IP prio has precedence), and |
| 199 | * set STP state to Forwarding. Finally, if this is the CPU |
| 200 | * port, additionally enable forwarding of unknown unicast and |
| 201 | * multicast addresses. |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 202 | */ |
| 203 | REG_WRITE(addr, 0x04, |
Lennert Buytenhek | cf85d08 | 2008-10-07 13:45:02 +0000 | [diff] [blame] | 204 | (p == ds->cpu_port) ? |
| 205 | (ds->tag_protocol == htons(ETH_P_DSA)) ? |
| 206 | 0x053f : 0x373f : |
| 207 | 0x0433); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 208 | |
| 209 | /* |
| 210 | * Port Control 1: disable trunking. Also, if this is the |
| 211 | * CPU port, enable learn messages to be sent to this port. |
| 212 | */ |
| 213 | REG_WRITE(addr, 0x05, (p == ds->cpu_port) ? 0x8000 : 0x0000); |
| 214 | |
| 215 | /* |
| 216 | * Port based VLAN map: give each port its own address |
| 217 | * database, allow the CPU port to talk to each of the 'real' |
| 218 | * ports, and allow each of the 'real' ports to only talk to |
| 219 | * the CPU port. |
| 220 | */ |
| 221 | REG_WRITE(addr, 0x06, |
| 222 | ((p & 0xf) << 12) | |
| 223 | ((p == ds->cpu_port) ? |
| 224 | ds->valid_port_mask : |
| 225 | (1 << ds->cpu_port))); |
| 226 | |
| 227 | /* |
| 228 | * Default VLAN ID and priority: don't set a default VLAN |
| 229 | * ID, and set the default packet priority to zero. |
| 230 | */ |
| 231 | REG_WRITE(addr, 0x07, 0x0000); |
| 232 | |
| 233 | /* |
| 234 | * Port Control 2: don't force a good FCS, set the maximum |
| 235 | * frame size to 10240 bytes, don't let the switch add or |
| 236 | * strip 802.1q tags, don't discard tagged or untagged frames |
| 237 | * on this port, do a destination address lookup on all |
| 238 | * received packets as usual, disable ARP mirroring and don't |
| 239 | * send a copy of all transmitted/received frames on this port |
| 240 | * to the CPU. |
| 241 | */ |
| 242 | REG_WRITE(addr, 0x08, 0x2080); |
| 243 | |
| 244 | /* |
| 245 | * Egress rate control: disable egress rate control. |
| 246 | */ |
| 247 | REG_WRITE(addr, 0x09, 0x0001); |
| 248 | |
| 249 | /* |
| 250 | * Egress rate control 2: disable egress rate control. |
| 251 | */ |
| 252 | REG_WRITE(addr, 0x0a, 0x0000); |
| 253 | |
| 254 | /* |
| 255 | * Port Association Vector: when learning source addresses |
| 256 | * of packets, add the address to the address database using |
| 257 | * a port bitmap that has only the bit for this port set and |
| 258 | * the other bits clear. |
| 259 | */ |
| 260 | REG_WRITE(addr, 0x0b, 1 << p); |
| 261 | |
| 262 | /* |
| 263 | * Port ATU control: disable limiting the number of address |
| 264 | * database entries that this port is allowed to use. |
| 265 | */ |
| 266 | REG_WRITE(addr, 0x0c, 0x0000); |
| 267 | |
| 268 | /* |
| 269 | * Priorit Override: disable DA, SA and VTU priority override. |
| 270 | */ |
| 271 | REG_WRITE(addr, 0x0d, 0x0000); |
| 272 | |
| 273 | /* |
| 274 | * Port Ethertype: use the Ethertype DSA Ethertype value. |
| 275 | */ |
| 276 | REG_WRITE(addr, 0x0f, ETH_P_EDSA); |
| 277 | |
| 278 | /* |
| 279 | * Tag Remap: use an identity 802.1p prio -> switch prio |
| 280 | * mapping. |
| 281 | */ |
| 282 | REG_WRITE(addr, 0x18, 0x3210); |
| 283 | |
| 284 | /* |
| 285 | * Tag Remap 2: use an identity 802.1p prio -> switch prio |
| 286 | * mapping. |
| 287 | */ |
| 288 | REG_WRITE(addr, 0x19, 0x7654); |
| 289 | |
| 290 | return 0; |
| 291 | } |
| 292 | |
| 293 | static int mv88e6123_61_65_setup(struct dsa_switch *ds) |
| 294 | { |
| 295 | struct mv88e6xxx_priv_state *ps = (void *)(ds + 1); |
| 296 | int i; |
| 297 | int ret; |
| 298 | |
| 299 | mutex_init(&ps->smi_mutex); |
| 300 | mutex_init(&ps->stats_mutex); |
| 301 | |
| 302 | ret = mv88e6123_61_65_switch_reset(ds); |
| 303 | if (ret < 0) |
| 304 | return ret; |
| 305 | |
| 306 | /* @@@ initialise vtu and atu */ |
| 307 | |
| 308 | ret = mv88e6123_61_65_setup_global(ds); |
| 309 | if (ret < 0) |
| 310 | return ret; |
| 311 | |
| 312 | for (i = 0; i < 6; i++) { |
| 313 | ret = mv88e6123_61_65_setup_port(ds, i); |
| 314 | if (ret < 0) |
| 315 | return ret; |
| 316 | } |
| 317 | |
| 318 | return 0; |
| 319 | } |
| 320 | |
| 321 | static int mv88e6123_61_65_port_to_phy_addr(int port) |
| 322 | { |
| 323 | if (port >= 0 && port <= 4) |
| 324 | return port; |
| 325 | return -1; |
| 326 | } |
| 327 | |
| 328 | static int |
| 329 | mv88e6123_61_65_phy_read(struct dsa_switch *ds, int port, int regnum) |
| 330 | { |
| 331 | int addr = mv88e6123_61_65_port_to_phy_addr(port); |
| 332 | return mv88e6xxx_phy_read(ds, addr, regnum); |
| 333 | } |
| 334 | |
| 335 | static int |
| 336 | mv88e6123_61_65_phy_write(struct dsa_switch *ds, |
| 337 | int port, int regnum, u16 val) |
| 338 | { |
| 339 | int addr = mv88e6123_61_65_port_to_phy_addr(port); |
| 340 | return mv88e6xxx_phy_write(ds, addr, regnum, val); |
| 341 | } |
| 342 | |
| 343 | static struct mv88e6xxx_hw_stat mv88e6123_61_65_hw_stats[] = { |
| 344 | { "in_good_octets", 8, 0x00, }, |
| 345 | { "in_bad_octets", 4, 0x02, }, |
| 346 | { "in_unicast", 4, 0x04, }, |
| 347 | { "in_broadcasts", 4, 0x06, }, |
| 348 | { "in_multicasts", 4, 0x07, }, |
| 349 | { "in_pause", 4, 0x16, }, |
| 350 | { "in_undersize", 4, 0x18, }, |
| 351 | { "in_fragments", 4, 0x19, }, |
| 352 | { "in_oversize", 4, 0x1a, }, |
| 353 | { "in_jabber", 4, 0x1b, }, |
| 354 | { "in_rx_error", 4, 0x1c, }, |
| 355 | { "in_fcs_error", 4, 0x1d, }, |
| 356 | { "out_octets", 8, 0x0e, }, |
| 357 | { "out_unicast", 4, 0x10, }, |
| 358 | { "out_broadcasts", 4, 0x13, }, |
| 359 | { "out_multicasts", 4, 0x12, }, |
| 360 | { "out_pause", 4, 0x15, }, |
| 361 | { "excessive", 4, 0x11, }, |
| 362 | { "collisions", 4, 0x1e, }, |
| 363 | { "deferred", 4, 0x05, }, |
| 364 | { "single", 4, 0x14, }, |
| 365 | { "multiple", 4, 0x17, }, |
| 366 | { "out_fcs_error", 4, 0x03, }, |
| 367 | { "late", 4, 0x1f, }, |
| 368 | { "hist_64bytes", 4, 0x08, }, |
| 369 | { "hist_65_127bytes", 4, 0x09, }, |
| 370 | { "hist_128_255bytes", 4, 0x0a, }, |
| 371 | { "hist_256_511bytes", 4, 0x0b, }, |
| 372 | { "hist_512_1023bytes", 4, 0x0c, }, |
| 373 | { "hist_1024_max_bytes", 4, 0x0d, }, |
| 374 | }; |
| 375 | |
| 376 | static void |
| 377 | mv88e6123_61_65_get_strings(struct dsa_switch *ds, int port, uint8_t *data) |
| 378 | { |
| 379 | mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6123_61_65_hw_stats), |
| 380 | mv88e6123_61_65_hw_stats, port, data); |
| 381 | } |
| 382 | |
| 383 | static void |
| 384 | mv88e6123_61_65_get_ethtool_stats(struct dsa_switch *ds, |
| 385 | int port, uint64_t *data) |
| 386 | { |
| 387 | mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6123_61_65_hw_stats), |
| 388 | mv88e6123_61_65_hw_stats, port, data); |
| 389 | } |
| 390 | |
| 391 | static int mv88e6123_61_65_get_sset_count(struct dsa_switch *ds) |
| 392 | { |
| 393 | return ARRAY_SIZE(mv88e6123_61_65_hw_stats); |
| 394 | } |
| 395 | |
| 396 | static struct dsa_switch_driver mv88e6123_61_65_switch_driver = { |
| 397 | .tag_protocol = __constant_htons(ETH_P_EDSA), |
| 398 | .priv_size = sizeof(struct mv88e6xxx_priv_state), |
| 399 | .probe = mv88e6123_61_65_probe, |
| 400 | .setup = mv88e6123_61_65_setup, |
| 401 | .set_addr = mv88e6xxx_set_addr_indirect, |
| 402 | .phy_read = mv88e6123_61_65_phy_read, |
| 403 | .phy_write = mv88e6123_61_65_phy_write, |
| 404 | .poll_link = mv88e6xxx_poll_link, |
| 405 | .get_strings = mv88e6123_61_65_get_strings, |
| 406 | .get_ethtool_stats = mv88e6123_61_65_get_ethtool_stats, |
| 407 | .get_sset_count = mv88e6123_61_65_get_sset_count, |
| 408 | }; |
| 409 | |
Roel Kluin | 5eaa65b | 2008-12-10 15:18:31 -0800 | [diff] [blame] | 410 | static int __init mv88e6123_61_65_init(void) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 411 | { |
| 412 | register_switch_driver(&mv88e6123_61_65_switch_driver); |
| 413 | return 0; |
| 414 | } |
| 415 | module_init(mv88e6123_61_65_init); |
| 416 | |
Roel Kluin | 5eaa65b | 2008-12-10 15:18:31 -0800 | [diff] [blame] | 417 | static void __exit mv88e6123_61_65_cleanup(void) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 418 | { |
| 419 | unregister_switch_driver(&mv88e6123_61_65_switch_driver); |
| 420 | } |
| 421 | module_exit(mv88e6123_61_65_cleanup); |