blob: 3849eef0d3a7641820f0dacbd54b838351804dcc [file] [log] [blame]
Kuninori Morimoto6c01ba42011-11-10 18:45:52 -08001/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Kuninori Morimoto6c01ba42011-11-10 18:45:52 -080015 */
16#include <linux/kernel.h>
17#include <linux/init.h>
Kuninori Morimoto6831f3a2011-11-10 18:46:23 -080018#include <linux/io.h>
Kuninori Morimoto70e3f3d2013-08-01 23:39:44 -070019#include <linux/irqchip.h>
20#include <linux/irqchip/arm-gic.h>
Geert Uytterhoeven9e38b842014-06-20 18:53:03 +020021
Magnus Dammd3ab7222012-02-29 21:37:35 +090022#include <asm/mach/map.h>
Kuninori Morimoto6c01ba42011-11-10 18:45:52 -080023#include <asm/mach/arch.h>
Magnus Damm23e5bc02012-03-06 17:36:53 +090024#include <asm/mach/time.h>
Geert Uytterhoeven9e38b842014-06-20 18:53:03 +020025
Magnus Dammfd44aa52014-06-17 16:47:37 +090026#include "common.h"
Kuninori Morimoto6c01ba42011-11-10 18:45:52 -080027
Kuninori Morimotod49679e2012-06-12 02:36:21 -070028/*
29 * r8a7740 chip has lasting errata on MERAM buffer.
30 * this is work-around for it.
31 * see
32 * "Media RAM (MERAM)" on r8a7740 documentation
33 */
34#define MEBUFCNTR 0xFE950098
Geert Uytterhoeven44d88c72015-06-17 11:31:24 +020035static void __init r8a7740_meram_workaround(void)
Kuninori Morimotod49679e2012-06-12 02:36:21 -070036{
37 void __iomem *reg;
38
39 reg = ioremap_nocache(MEBUFCNTR, 4);
40 if (reg) {
41 iowrite32(0x01600164, reg);
42 iounmap(reg);
43 }
44}
45
Geert Uytterhoeven44d88c72015-06-17 11:31:24 +020046static void __init r8a7740_init_irq_of(void)
Kuninori Morimoto70e3f3d2013-08-01 23:39:44 -070047{
48 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
49 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
50 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
51
52 irqchip_init();
53
54 /* route signals to GIC */
55 iowrite32(0x0, pfc_inta_ctrl);
56
57 /*
58 * To mask the shared interrupt to SPI 149 we must ensure to set
59 * PRIO *and* MASK. Else we run into IRQ floods when registering
60 * the intc_irqpin devices
61 */
62 iowrite32(0x0, intc_prio_base + 0x0);
63 iowrite32(0x0, intc_prio_base + 0x4);
64 iowrite32(0x0, intc_prio_base + 0x8);
65 iowrite32(0x0, intc_prio_base + 0xc);
66 iowrite8(0xff, intc_msk_base + 0x0);
67 iowrite8(0xff, intc_msk_base + 0x4);
68 iowrite8(0xff, intc_msk_base + 0x8);
69 iowrite8(0xff, intc_msk_base + 0xc);
70
71 iounmap(intc_prio_base);
72 iounmap(intc_msk_base);
73 iounmap(pfc_inta_ctrl);
74}
75
Bastian Hecht744fdc82013-04-17 12:34:05 +020076static void __init r8a7740_generic_init(void)
77{
Magnus Dammc41215b2014-08-25 12:36:53 +090078 r8a7740_meram_workaround();
Bastian Hecht744fdc82013-04-17 12:34:05 +020079}
80
Nicolas Pitre19c233b2015-07-27 18:27:52 -040081static const char *const r8a7740_boards_compat_dt[] __initconst = {
Magnus Damm755d57b2012-07-06 17:08:07 +090082 "renesas,r8a7740",
83 NULL,
84};
85
Kuninori Morimotoa41acc42012-10-21 22:15:13 -070086DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
Geert Uytterhoeven4a6cc502015-11-23 14:56:01 +010087 .l2c_aux_val = 0,
88 .l2c_aux_mask = ~0,
Magnus Damma0c1fb02014-05-08 08:32:38 +090089 .init_early = shmobile_init_delay,
Bastian Hecht744fdc82013-04-17 12:34:05 +020090 .init_irq = r8a7740_init_irq_of,
91 .init_machine = r8a7740_generic_init,
Magnus Damm34b9fa42014-05-12 08:10:50 +090092 .init_late = shmobile_init_late,
Magnus Damm755d57b2012-07-06 17:08:07 +090093 .dt_compat = r8a7740_boards_compat_dt,
94MACHINE_END