Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/alpha/kernel/sys_rx164.c |
| 3 | * |
| 4 | * Copyright (C) 1995 David A Rusling |
| 5 | * Copyright (C) 1996 Jay A Estabrook |
| 6 | * Copyright (C) 1998, 1999 Richard Henderson |
| 7 | * |
| 8 | * Code supporting the RX164 (PCA56+POLARIS). |
| 9 | */ |
| 10 | |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/types.h> |
| 13 | #include <linux/mm.h> |
| 14 | #include <linux/sched.h> |
| 15 | #include <linux/pci.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/bitops.h> |
| 18 | |
| 19 | #include <asm/ptrace.h> |
| 20 | #include <asm/system.h> |
| 21 | #include <asm/dma.h> |
| 22 | #include <asm/irq.h> |
| 23 | #include <asm/mmu_context.h> |
| 24 | #include <asm/io.h> |
| 25 | #include <asm/pgtable.h> |
| 26 | #include <asm/core_polaris.h> |
| 27 | #include <asm/tlbflush.h> |
| 28 | |
| 29 | #include "proto.h" |
| 30 | #include "irq_impl.h" |
| 31 | #include "pci_impl.h" |
| 32 | #include "machvec_impl.h" |
| 33 | |
| 34 | |
| 35 | /* Note mask bit is true for ENABLED irqs. */ |
| 36 | static unsigned long cached_irq_mask; |
| 37 | |
| 38 | static inline void |
| 39 | rx164_update_irq_hw(unsigned long mask) |
| 40 | { |
| 41 | volatile unsigned int *irq_mask; |
| 42 | |
| 43 | irq_mask = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x74); |
| 44 | *irq_mask = mask; |
| 45 | mb(); |
| 46 | *irq_mask; |
| 47 | } |
| 48 | |
| 49 | static inline void |
| 50 | rx164_enable_irq(unsigned int irq) |
| 51 | { |
| 52 | rx164_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16)); |
| 53 | } |
| 54 | |
| 55 | static void |
| 56 | rx164_disable_irq(unsigned int irq) |
| 57 | { |
| 58 | rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16))); |
| 59 | } |
| 60 | |
Thomas Gleixner | 44377f6 | 2009-06-16 15:33:25 -0700 | [diff] [blame] | 61 | static struct irq_chip rx164_irq_type = { |
Thomas Gleixner | 8ab1221 | 2009-11-30 22:51:31 -0500 | [diff] [blame] | 62 | .name = "RX164", |
Kyle McMartin | 7d209c8 | 2010-10-14 22:31:34 -0400 | [diff] [blame] | 63 | .unmask = rx164_enable_irq, |
| 64 | .mask = rx164_disable_irq, |
| 65 | .mask_ack = rx164_disable_irq, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 66 | }; |
| 67 | |
| 68 | static void |
Al Viro | 7ca5605 | 2006-10-08 14:36:08 +0100 | [diff] [blame] | 69 | rx164_device_interrupt(unsigned long vector) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | { |
| 71 | unsigned long pld; |
| 72 | volatile unsigned int *dirr; |
| 73 | long i; |
| 74 | |
| 75 | /* Read the interrupt summary register. On Polaris, this is |
| 76 | the DIRR register in PCI config space (offset 0x84). */ |
| 77 | dirr = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x84); |
| 78 | pld = *dirr; |
| 79 | |
| 80 | /* |
| 81 | * Now for every possible bit set, work through them and call |
| 82 | * the appropriate interrupt handler. |
| 83 | */ |
| 84 | while (pld) { |
| 85 | i = ffz(~pld); |
| 86 | pld &= pld - 1; /* clear least bit set */ |
| 87 | if (i == 20) { |
Al Viro | 3dbb8c6 | 2006-10-08 14:37:32 +0100 | [diff] [blame] | 88 | isa_no_iack_sc_device_interrupt(vector); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | } else { |
Al Viro | 3dbb8c6 | 2006-10-08 14:37:32 +0100 | [diff] [blame] | 90 | handle_irq(16+i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | } |
| 92 | } |
| 93 | } |
| 94 | |
| 95 | static void __init |
| 96 | rx164_init_irq(void) |
| 97 | { |
| 98 | long i; |
| 99 | |
| 100 | rx164_update_irq_hw(0); |
| 101 | for (i = 16; i < 40; ++i) { |
Kyle McMartin | a891b39 | 2010-10-14 22:31:25 -0400 | [diff] [blame] | 102 | irq_to_desc(i)->status |= IRQ_LEVEL; |
Kyle McMartin | 7d209c8 | 2010-10-14 22:31:34 -0400 | [diff] [blame] | 103 | set_irq_chip_and_handler(i, &rx164_irq_type, handle_level_irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | init_i8259a_irqs(); |
| 107 | common_init_isa_dma(); |
| 108 | |
| 109 | setup_irq(16+20, &isa_cascade_irqaction); |
| 110 | } |
| 111 | |
| 112 | |
| 113 | /* |
| 114 | * The RX164 changed its interrupt routing between pass1 and pass2... |
| 115 | * |
| 116 | * PASS1: |
| 117 | * |
| 118 | * Slot IDSEL INTA INTB INTC INTD |
| 119 | * 0 6 5 10 15 20 |
| 120 | * 1 7 4 9 14 19 |
| 121 | * 2 5 3 8 13 18 |
| 122 | * 3 9 2 7 12 17 |
| 123 | * 4 10 1 6 11 16 |
| 124 | * |
| 125 | * PASS2: |
| 126 | * Slot IDSEL INTA INTB INTC INTD |
| 127 | * 0 5 1 7 12 17 |
| 128 | * 1 6 2 8 13 18 |
| 129 | * 2 8 3 9 14 19 |
| 130 | * 3 9 4 10 15 20 |
| 131 | * 4 10 5 11 16 6 |
| 132 | * |
| 133 | */ |
| 134 | |
| 135 | /* |
| 136 | * IdSel |
| 137 | * 5 32 bit PCI option slot 0 |
| 138 | * 6 64 bit PCI option slot 1 |
| 139 | * 7 PCI-ISA bridge |
| 140 | * 7 64 bit PCI option slot 2 |
| 141 | * 9 32 bit PCI option slot 3 |
| 142 | * 10 PCI-PCI bridge |
| 143 | * |
| 144 | */ |
| 145 | |
| 146 | static int __init |
| 147 | rx164_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
| 148 | { |
| 149 | #if 0 |
| 150 | static char irq_tab_pass1[6][5] __initdata = { |
| 151 | /*INT INTA INTB INTC INTD */ |
| 152 | { 16+3, 16+3, 16+8, 16+13, 16+18}, /* IdSel 5, slot 2 */ |
| 153 | { 16+5, 16+5, 16+10, 16+15, 16+20}, /* IdSel 6, slot 0 */ |
| 154 | { 16+4, 16+4, 16+9, 16+14, 16+19}, /* IdSel 7, slot 1 */ |
| 155 | { -1, -1, -1, -1, -1}, /* IdSel 8, PCI/ISA bridge */ |
| 156 | { 16+2, 16+2, 16+7, 16+12, 16+17}, /* IdSel 9, slot 3 */ |
| 157 | { 16+1, 16+1, 16+6, 16+11, 16+16}, /* IdSel 10, slot 4 */ |
| 158 | }; |
| 159 | #else |
| 160 | static char irq_tab[6][5] __initdata = { |
| 161 | /*INT INTA INTB INTC INTD */ |
| 162 | { 16+0, 16+0, 16+6, 16+11, 16+16}, /* IdSel 5, slot 0 */ |
| 163 | { 16+1, 16+1, 16+7, 16+12, 16+17}, /* IdSel 6, slot 1 */ |
| 164 | { -1, -1, -1, -1, -1}, /* IdSel 7, PCI/ISA bridge */ |
| 165 | { 16+2, 16+2, 16+8, 16+13, 16+18}, /* IdSel 8, slot 2 */ |
| 166 | { 16+3, 16+3, 16+9, 16+14, 16+19}, /* IdSel 9, slot 3 */ |
| 167 | { 16+4, 16+4, 16+10, 16+15, 16+5}, /* IdSel 10, PCI-PCI */ |
| 168 | }; |
| 169 | #endif |
| 170 | const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5; |
| 171 | |
| 172 | /* JRP - Need to figure out how to distinguish pass1 from pass2, |
| 173 | and use the correct table. */ |
| 174 | return COMMON_TABLE_LOOKUP; |
| 175 | } |
| 176 | |
| 177 | |
| 178 | /* |
| 179 | * The System Vector |
| 180 | */ |
| 181 | |
| 182 | struct alpha_machine_vector rx164_mv __initmv = { |
| 183 | .vector_name = "RX164", |
| 184 | DO_EV5_MMU, |
| 185 | DO_DEFAULT_RTC, |
| 186 | DO_POLARIS_IO, |
| 187 | .machine_check = polaris_machine_check, |
| 188 | .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
| 189 | .min_io_address = DEFAULT_IO_BASE, |
| 190 | .min_mem_address = DEFAULT_MEM_BASE, |
| 191 | |
| 192 | .nr_irqs = 40, |
| 193 | .device_interrupt = rx164_device_interrupt, |
| 194 | |
| 195 | .init_arch = polaris_init_arch, |
| 196 | .init_irq = rx164_init_irq, |
| 197 | .init_rtc = common_init_rtc, |
| 198 | .init_pci = common_init_pci, |
| 199 | .kill_arch = NULL, |
| 200 | .pci_map_irq = rx164_map_irq, |
| 201 | .pci_swizzle = common_swizzle, |
| 202 | }; |
| 203 | ALIAS_MV(rx164) |