SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 1 | /* |
Andrew Victor | 9d04126 | 2007-02-05 11:42:07 +0100 | [diff] [blame] | 2 | * linux/arch/arm/mach-at91/clock.c |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2005 David Brownell |
| 5 | * Copyright (C) 2005 Ivan Kokshaysky |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/fs.h> |
| 17 | #include <linux/debugfs.h> |
| 18 | #include <linux/seq_file.h> |
| 19 | #include <linux/list.h> |
| 20 | #include <linux/errno.h> |
| 21 | #include <linux/err.h> |
| 22 | #include <linux/spinlock.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/clk.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 25 | #include <linux/io.h> |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 26 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 27 | #include <mach/hardware.h> |
| 28 | #include <mach/at91_pmc.h> |
| 29 | #include <mach/cpu.h> |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 30 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 31 | #include "clock.h" |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 32 | |
Andrew Victor | 55c20c0 | 2006-06-20 19:31:39 +0100 | [diff] [blame] | 33 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 34 | /* |
| 35 | * There's a lot more which can be done with clocks, including cpufreq |
| 36 | * integration, slow clock mode support (for system suspend), letting |
| 37 | * PLLB be used at other rates (on boards that don't need USB), etc. |
| 38 | */ |
| 39 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 40 | #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY) |
| 41 | #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE) |
| 42 | #define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL) |
Andrew Victor | d481f86 | 2006-12-01 11:27:31 +0100 | [diff] [blame] | 43 | #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 44 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 45 | |
| 46 | static LIST_HEAD(clocks); |
| 47 | static DEFINE_SPINLOCK(clk_lock); |
| 48 | |
| 49 | static u32 at91_pllb_usb_init; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 50 | |
| 51 | /* |
| 52 | * Four primary clock sources: two crystal oscillators (32K, main), and |
| 53 | * two PLLs. PLLA usually runs the master clock; and PLLB must run at |
| 54 | * 48 MHz (unless no USB function clocks are needed). The main clock and |
| 55 | * both PLLs are turned off to run in "slow clock mode" (system suspend). |
| 56 | */ |
| 57 | static struct clk clk32k = { |
| 58 | .name = "clk32k", |
| 59 | .rate_hz = AT91_SLOW_CLOCK, |
| 60 | .users = 1, /* always on */ |
| 61 | .id = 0, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 62 | .type = CLK_TYPE_PRIMARY, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 63 | }; |
| 64 | static struct clk main_clk = { |
| 65 | .name = "main", |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 66 | .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 67 | .id = 1, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 68 | .type = CLK_TYPE_PRIMARY, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 69 | }; |
| 70 | static struct clk plla = { |
| 71 | .name = "plla", |
| 72 | .parent = &main_clk, |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 73 | .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 74 | .id = 2, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 75 | .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 76 | }; |
| 77 | |
| 78 | static void pllb_mode(struct clk *clk, int is_on) |
| 79 | { |
| 80 | u32 value; |
| 81 | |
| 82 | if (is_on) { |
| 83 | is_on = AT91_PMC_LOCKB; |
| 84 | value = at91_pllb_usb_init; |
| 85 | } else |
| 86 | value = 0; |
| 87 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 88 | // REVISIT: Add work-around for AT91RM9200 Errata #26 ? |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 89 | at91_sys_write(AT91_CKGR_PLLBR, value); |
| 90 | |
| 91 | do { |
| 92 | cpu_relax(); |
| 93 | } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on); |
| 94 | } |
| 95 | |
| 96 | static struct clk pllb = { |
| 97 | .name = "pllb", |
| 98 | .parent = &main_clk, |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 99 | .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 100 | .mode = pllb_mode, |
| 101 | .id = 3, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 102 | .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 103 | }; |
| 104 | |
| 105 | static void pmc_sys_mode(struct clk *clk, int is_on) |
| 106 | { |
| 107 | if (is_on) |
| 108 | at91_sys_write(AT91_PMC_SCER, clk->pmc_mask); |
| 109 | else |
| 110 | at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask); |
| 111 | } |
| 112 | |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 113 | static void pmc_uckr_mode(struct clk *clk, int is_on) |
| 114 | { |
| 115 | unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR); |
| 116 | |
| 117 | if (is_on) { |
| 118 | is_on = AT91_PMC_LOCKU; |
| 119 | at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); |
| 120 | } else |
| 121 | at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask)); |
| 122 | |
| 123 | do { |
| 124 | cpu_relax(); |
| 125 | } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on); |
| 126 | } |
| 127 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 128 | /* USB function clocks (PLLB must be 48 MHz) */ |
| 129 | static struct clk udpck = { |
| 130 | .name = "udpck", |
| 131 | .parent = &pllb, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 132 | .mode = pmc_sys_mode, |
| 133 | }; |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 134 | static struct clk utmi_clk = { |
| 135 | .name = "utmi_clk", |
| 136 | .parent = &main_clk, |
| 137 | .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */ |
| 138 | .mode = pmc_uckr_mode, |
| 139 | .type = CLK_TYPE_PLL, |
| 140 | }; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 141 | static struct clk uhpck = { |
| 142 | .name = "uhpck", |
| 143 | .parent = &pllb, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 144 | .mode = pmc_sys_mode, |
| 145 | }; |
| 146 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 147 | |
| 148 | /* |
| 149 | * The master clock is divided from the CPU clock (by 1-4). It's used for |
| 150 | * memory, interfaces to on-chip peripherals, the AIC, and sometimes more |
| 151 | * (e.g baud rate generation). It's sourced from one of the primary clocks. |
| 152 | */ |
| 153 | static struct clk mck = { |
| 154 | .name = "mck", |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 155 | .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 156 | }; |
| 157 | |
| 158 | static void pmc_periph_mode(struct clk *clk, int is_on) |
| 159 | { |
| 160 | if (is_on) |
| 161 | at91_sys_write(AT91_PMC_PCER, clk->pmc_mask); |
| 162 | else |
| 163 | at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask); |
| 164 | } |
| 165 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 166 | static struct clk __init *at91_css_to_clk(unsigned long css) |
| 167 | { |
| 168 | switch (css) { |
| 169 | case AT91_PMC_CSS_SLOW: |
| 170 | return &clk32k; |
| 171 | case AT91_PMC_CSS_MAIN: |
| 172 | return &main_clk; |
| 173 | case AT91_PMC_CSS_PLLA: |
| 174 | return &plla; |
| 175 | case AT91_PMC_CSS_PLLB: |
| 176 | return &pllb; |
| 177 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 178 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 179 | return NULL; |
| 180 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 181 | |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 182 | /* |
| 183 | * Associate a particular clock with a function (eg, "uart") and device. |
| 184 | * The drivers can then request the same 'function' with several different |
| 185 | * devices and not care about which clock name to use. |
| 186 | */ |
| 187 | void __init at91_clock_associate(const char *id, struct device *dev, const char *func) |
| 188 | { |
| 189 | struct clk *clk = clk_get(NULL, id); |
| 190 | |
| 191 | if (!dev || !clk || !IS_ERR(clk_get(dev, func))) |
| 192 | return; |
| 193 | |
| 194 | clk->function = func; |
| 195 | clk->dev = dev; |
| 196 | } |
| 197 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 198 | /* clocks cannot be de-registered no refcounting necessary */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 199 | struct clk *clk_get(struct device *dev, const char *id) |
| 200 | { |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 201 | struct clk *clk; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 202 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 203 | list_for_each_entry(clk, &clocks, node) { |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 204 | if (strcmp(id, clk->name) == 0) |
| 205 | return clk; |
| 206 | if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0) |
| 207 | return clk; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 208 | } |
| 209 | |
| 210 | return ERR_PTR(-ENOENT); |
| 211 | } |
| 212 | EXPORT_SYMBOL(clk_get); |
| 213 | |
| 214 | void clk_put(struct clk *clk) |
| 215 | { |
| 216 | } |
| 217 | EXPORT_SYMBOL(clk_put); |
| 218 | |
| 219 | static void __clk_enable(struct clk *clk) |
| 220 | { |
| 221 | if (clk->parent) |
| 222 | __clk_enable(clk->parent); |
| 223 | if (clk->users++ == 0 && clk->mode) |
| 224 | clk->mode(clk, 1); |
| 225 | } |
| 226 | |
| 227 | int clk_enable(struct clk *clk) |
| 228 | { |
| 229 | unsigned long flags; |
| 230 | |
| 231 | spin_lock_irqsave(&clk_lock, flags); |
| 232 | __clk_enable(clk); |
| 233 | spin_unlock_irqrestore(&clk_lock, flags); |
| 234 | return 0; |
| 235 | } |
| 236 | EXPORT_SYMBOL(clk_enable); |
| 237 | |
| 238 | static void __clk_disable(struct clk *clk) |
| 239 | { |
| 240 | BUG_ON(clk->users == 0); |
| 241 | if (--clk->users == 0 && clk->mode) |
| 242 | clk->mode(clk, 0); |
| 243 | if (clk->parent) |
| 244 | __clk_disable(clk->parent); |
| 245 | } |
| 246 | |
| 247 | void clk_disable(struct clk *clk) |
| 248 | { |
| 249 | unsigned long flags; |
| 250 | |
| 251 | spin_lock_irqsave(&clk_lock, flags); |
| 252 | __clk_disable(clk); |
| 253 | spin_unlock_irqrestore(&clk_lock, flags); |
| 254 | } |
| 255 | EXPORT_SYMBOL(clk_disable); |
| 256 | |
| 257 | unsigned long clk_get_rate(struct clk *clk) |
| 258 | { |
| 259 | unsigned long flags; |
| 260 | unsigned long rate; |
| 261 | |
| 262 | spin_lock_irqsave(&clk_lock, flags); |
| 263 | for (;;) { |
| 264 | rate = clk->rate_hz; |
| 265 | if (rate || !clk->parent) |
| 266 | break; |
| 267 | clk = clk->parent; |
| 268 | } |
| 269 | spin_unlock_irqrestore(&clk_lock, flags); |
| 270 | return rate; |
| 271 | } |
| 272 | EXPORT_SYMBOL(clk_get_rate); |
| 273 | |
| 274 | /*------------------------------------------------------------------------*/ |
| 275 | |
| 276 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS |
| 277 | |
| 278 | /* |
| 279 | * For now, only the programmable clocks support reparenting (MCK could |
| 280 | * do this too, with care) or rate changing (the PLLs could do this too, |
| 281 | * ditto MCK but that's more for cpufreq). Drivers may reparent to get |
| 282 | * a better rate match; we don't. |
| 283 | */ |
| 284 | |
| 285 | long clk_round_rate(struct clk *clk, unsigned long rate) |
| 286 | { |
| 287 | unsigned long flags; |
| 288 | unsigned prescale; |
| 289 | unsigned long actual; |
| 290 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 291 | if (!clk_is_programmable(clk)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 292 | return -EINVAL; |
| 293 | spin_lock_irqsave(&clk_lock, flags); |
| 294 | |
| 295 | actual = clk->parent->rate_hz; |
| 296 | for (prescale = 0; prescale < 7; prescale++) { |
| 297 | if (actual && actual <= rate) |
| 298 | break; |
| 299 | actual >>= 1; |
| 300 | } |
| 301 | |
| 302 | spin_unlock_irqrestore(&clk_lock, flags); |
| 303 | return (prescale < 7) ? actual : -ENOENT; |
| 304 | } |
| 305 | EXPORT_SYMBOL(clk_round_rate); |
| 306 | |
| 307 | int clk_set_rate(struct clk *clk, unsigned long rate) |
| 308 | { |
| 309 | unsigned long flags; |
| 310 | unsigned prescale; |
| 311 | unsigned long actual; |
| 312 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 313 | if (!clk_is_programmable(clk)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 314 | return -EINVAL; |
| 315 | if (clk->users) |
| 316 | return -EBUSY; |
| 317 | spin_lock_irqsave(&clk_lock, flags); |
| 318 | |
| 319 | actual = clk->parent->rate_hz; |
| 320 | for (prescale = 0; prescale < 7; prescale++) { |
| 321 | if (actual && actual <= rate) { |
| 322 | u32 pckr; |
| 323 | |
| 324 | pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 325 | pckr &= AT91_PMC_CSS_PLLB; /* clock selection */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 326 | pckr |= prescale << 2; |
| 327 | at91_sys_write(AT91_PMC_PCKR(clk->id), pckr); |
| 328 | clk->rate_hz = actual; |
| 329 | break; |
| 330 | } |
| 331 | actual >>= 1; |
| 332 | } |
| 333 | |
| 334 | spin_unlock_irqrestore(&clk_lock, flags); |
| 335 | return (prescale < 7) ? actual : -ENOENT; |
| 336 | } |
| 337 | EXPORT_SYMBOL(clk_set_rate); |
| 338 | |
| 339 | struct clk *clk_get_parent(struct clk *clk) |
| 340 | { |
| 341 | return clk->parent; |
| 342 | } |
| 343 | EXPORT_SYMBOL(clk_get_parent); |
| 344 | |
| 345 | int clk_set_parent(struct clk *clk, struct clk *parent) |
| 346 | { |
| 347 | unsigned long flags; |
| 348 | |
| 349 | if (clk->users) |
| 350 | return -EBUSY; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 351 | if (!clk_is_primary(parent) || !clk_is_programmable(clk)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 352 | return -EINVAL; |
| 353 | spin_lock_irqsave(&clk_lock, flags); |
| 354 | |
| 355 | clk->rate_hz = parent->rate_hz; |
| 356 | clk->parent = parent; |
| 357 | at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id); |
| 358 | |
| 359 | spin_unlock_irqrestore(&clk_lock, flags); |
| 360 | return 0; |
| 361 | } |
| 362 | EXPORT_SYMBOL(clk_set_parent); |
| 363 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 364 | /* establish PCK0..PCK3 parentage and rate */ |
David Brownell | 72e7ae8 | 2008-02-06 22:03:42 +0100 | [diff] [blame] | 365 | static void __init init_programmable_clock(struct clk *clk) |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 366 | { |
| 367 | struct clk *parent; |
| 368 | u32 pckr; |
| 369 | |
| 370 | pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); |
| 371 | parent = at91_css_to_clk(pckr & AT91_PMC_CSS); |
| 372 | clk->parent = parent; |
Andrew Victor | a95c729 | 2007-11-19 11:52:09 +0100 | [diff] [blame] | 373 | clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2)); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 374 | } |
| 375 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 376 | #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ |
| 377 | |
| 378 | /*------------------------------------------------------------------------*/ |
| 379 | |
| 380 | #ifdef CONFIG_DEBUG_FS |
| 381 | |
| 382 | static int at91_clk_show(struct seq_file *s, void *unused) |
| 383 | { |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 384 | u32 scsr, pcsr, uckr = 0, sr; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 385 | struct clk *clk; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 386 | |
| 387 | seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR)); |
| 388 | seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR)); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 389 | seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR)); |
| 390 | seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); |
| 391 | seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); |
Nicolas Ferre | ba45ca4 | 2008-04-08 13:59:18 +0100 | [diff] [blame] | 392 | if (!cpu_is_at91sam9rl()) |
| 393 | seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); |
| 394 | if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 395 | seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR)); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 396 | seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 397 | seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); |
| 398 | |
| 399 | seq_printf(s, "\n"); |
| 400 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 401 | list_for_each_entry(clk, &clocks, node) { |
| 402 | char *state; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 403 | |
| 404 | if (clk->mode == pmc_sys_mode) |
| 405 | state = (scsr & clk->pmc_mask) ? "on" : "off"; |
| 406 | else if (clk->mode == pmc_periph_mode) |
| 407 | state = (pcsr & clk->pmc_mask) ? "on" : "off"; |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 408 | else if (clk->mode == pmc_uckr_mode) |
| 409 | state = (uckr & clk->pmc_mask) ? "on" : "off"; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 410 | else if (clk->pmc_mask) |
| 411 | state = (sr & clk->pmc_mask) ? "on" : "off"; |
| 412 | else if (clk == &clk32k || clk == &main_clk) |
| 413 | state = "on"; |
| 414 | else |
| 415 | state = ""; |
| 416 | |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 417 | seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n", |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 418 | clk->name, clk->users, state, clk_get_rate(clk), |
| 419 | clk->parent ? clk->parent->name : ""); |
| 420 | } |
| 421 | return 0; |
| 422 | } |
| 423 | |
| 424 | static int at91_clk_open(struct inode *inode, struct file *file) |
| 425 | { |
| 426 | return single_open(file, at91_clk_show, NULL); |
| 427 | } |
| 428 | |
Arjan van de Ven | 5dfe4c9 | 2007-02-12 00:55:31 -0800 | [diff] [blame] | 429 | static const struct file_operations at91_clk_operations = { |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 430 | .open = at91_clk_open, |
| 431 | .read = seq_read, |
| 432 | .llseek = seq_lseek, |
| 433 | .release = single_release, |
| 434 | }; |
| 435 | |
| 436 | static int __init at91_clk_debugfs_init(void) |
| 437 | { |
| 438 | /* /sys/kernel/debug/at91_clk */ |
| 439 | (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations); |
| 440 | |
| 441 | return 0; |
| 442 | } |
| 443 | postcore_initcall(at91_clk_debugfs_init); |
| 444 | |
| 445 | #endif |
| 446 | |
| 447 | /*------------------------------------------------------------------------*/ |
| 448 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 449 | /* Register a new clock */ |
| 450 | int __init clk_register(struct clk *clk) |
| 451 | { |
| 452 | if (clk_is_peripheral(clk)) { |
| 453 | clk->parent = &mck; |
| 454 | clk->mode = pmc_periph_mode; |
| 455 | list_add_tail(&clk->node, &clocks); |
| 456 | } |
Andrew Victor | d481f86 | 2006-12-01 11:27:31 +0100 | [diff] [blame] | 457 | else if (clk_is_sys(clk)) { |
| 458 | clk->parent = &mck; |
| 459 | clk->mode = pmc_sys_mode; |
| 460 | |
| 461 | list_add_tail(&clk->node, &clocks); |
| 462 | } |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 463 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS |
| 464 | else if (clk_is_programmable(clk)) { |
| 465 | clk->mode = pmc_sys_mode; |
| 466 | init_programmable_clock(clk); |
| 467 | list_add_tail(&clk->node, &clocks); |
| 468 | } |
| 469 | #endif |
| 470 | |
| 471 | return 0; |
| 472 | } |
| 473 | |
| 474 | |
| 475 | /*------------------------------------------------------------------------*/ |
| 476 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 477 | static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg) |
| 478 | { |
| 479 | unsigned mul, div; |
| 480 | |
| 481 | div = reg & 0xff; |
| 482 | mul = (reg >> 16) & 0x7ff; |
| 483 | if (div && mul) { |
| 484 | freq /= div; |
| 485 | freq *= mul + 1; |
| 486 | } else |
| 487 | freq = 0; |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 488 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 489 | return freq; |
| 490 | } |
| 491 | |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 492 | static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg) |
| 493 | { |
| 494 | if (pll == &pllb && (reg & AT91_PMC_USB96M)) |
| 495 | return freq / 2; |
| 496 | else |
| 497 | return freq; |
| 498 | } |
| 499 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 500 | static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq) |
| 501 | { |
| 502 | unsigned i, div = 0, mul = 0, diff = 1 << 30; |
| 503 | unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; |
| 504 | |
| 505 | /* PLL output max 240 MHz (or 180 MHz per errata) */ |
| 506 | if (out_freq > 240000000) |
| 507 | goto fail; |
| 508 | |
| 509 | for (i = 1; i < 256; i++) { |
| 510 | int diff1; |
| 511 | unsigned input, mul1; |
| 512 | |
| 513 | /* |
| 514 | * PLL input between 1MHz and 32MHz per spec, but lower |
| 515 | * frequences seem necessary in some cases so allow 100K. |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 516 | * Warning: some newer products need 2MHz min. |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 517 | */ |
| 518 | input = main_freq / i; |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 519 | if (cpu_is_at91sam9g20() && input < 2000000) |
| 520 | continue; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 521 | if (input < 100000) |
| 522 | continue; |
| 523 | if (input > 32000000) |
| 524 | continue; |
| 525 | |
| 526 | mul1 = out_freq / input; |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 527 | if (cpu_is_at91sam9g20() && mul > 63) |
| 528 | continue; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 529 | if (mul1 > 2048) |
| 530 | continue; |
| 531 | if (mul1 < 2) |
| 532 | goto fail; |
| 533 | |
| 534 | diff1 = out_freq - input * mul1; |
| 535 | if (diff1 < 0) |
| 536 | diff1 = -diff1; |
| 537 | if (diff > diff1) { |
| 538 | diff = diff1; |
| 539 | div = i; |
| 540 | mul = mul1; |
| 541 | if (diff == 0) |
| 542 | break; |
| 543 | } |
| 544 | } |
| 545 | if (i == 256 && diff > (out_freq >> 5)) |
| 546 | goto fail; |
| 547 | return ret | ((mul - 1) << 16) | div; |
| 548 | fail: |
| 549 | return 0; |
| 550 | } |
| 551 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 552 | static struct clk *const standard_pmc_clocks[] __initdata = { |
| 553 | /* four primary clocks */ |
| 554 | &clk32k, |
| 555 | &main_clk, |
| 556 | &plla, |
| 557 | &pllb, |
| 558 | |
| 559 | /* PLLB children (USB) */ |
| 560 | &udpck, |
| 561 | &uhpck, |
| 562 | |
| 563 | /* MCK */ |
| 564 | &mck |
| 565 | }; |
| 566 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 567 | int __init at91_clock_init(unsigned long main_clock) |
| 568 | { |
| 569 | unsigned tmp, freq, mckr; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 570 | int i; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 571 | |
| 572 | /* |
| 573 | * When the bootloader initialized the main oscillator correctly, |
| 574 | * there's no problem using the cycle counter. But if it didn't, |
| 575 | * or when using oscillator bypass mode, we must be told the speed |
| 576 | * of the main clock. |
| 577 | */ |
| 578 | if (!main_clock) { |
| 579 | do { |
| 580 | tmp = at91_sys_read(AT91_CKGR_MCFR); |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 581 | } while (!(tmp & AT91_PMC_MAINRDY)); |
| 582 | main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 583 | } |
| 584 | main_clk.rate_hz = main_clock; |
| 585 | |
| 586 | /* report if PLLA is more than mildly overclocked */ |
| 587 | plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 588 | if ((!cpu_is_at91sam9g20() && plla.rate_hz > 209000000) |
| 589 | || (cpu_is_at91sam9g20() && plla.rate_hz > 800000000)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 590 | pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); |
| 591 | |
| 592 | /* |
Andrew Victor | c9b75d1 | 2007-02-08 17:36:34 +0100 | [diff] [blame] | 593 | * USB clock init: choose 48 MHz PLLB value, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 594 | * disable 48MHz clock during usb peripheral suspend. |
| 595 | * |
| 596 | * REVISIT: assumes MCK doesn't derive from PLLB! |
| 597 | */ |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 598 | at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 599 | pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); |
Andrew Victor | d481f86 | 2006-12-01 11:27:31 +0100 | [diff] [blame] | 600 | if (cpu_is_at91rm9200()) { |
| 601 | uhpck.pmc_mask = AT91RM9200_PMC_UHP; |
| 602 | udpck.pmc_mask = AT91RM9200_PMC_UDP; |
Andrew Victor | d481f86 | 2006-12-01 11:27:31 +0100 | [diff] [blame] | 603 | at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 604 | } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { |
Andrew Victor | d481f86 | 2006-12-01 11:27:31 +0100 | [diff] [blame] | 605 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; |
| 606 | udpck.pmc_mask = AT91SAM926x_PMC_UDP; |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 607 | } else if (cpu_is_at91cap9()) { |
| 608 | uhpck.pmc_mask = AT91CAP9_PMC_UHP; |
Andrew Victor | d481f86 | 2006-12-01 11:27:31 +0100 | [diff] [blame] | 609 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 610 | at91_sys_write(AT91_CKGR_PLLBR, 0); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 611 | |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 612 | udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); |
| 613 | uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); |
| 614 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 615 | /* |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 616 | * USB HS clock init |
| 617 | */ |
Nicolas Ferre | ba45ca4 | 2008-04-08 13:59:18 +0100 | [diff] [blame] | 618 | if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) { |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 619 | /* |
| 620 | * multiplier is hard-wired to 40 |
| 621 | * (obtain the USB High Speed 480 MHz when input is 12 MHz) |
| 622 | */ |
| 623 | utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; |
| 624 | } |
| 625 | |
| 626 | /* |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 627 | * MCK and CPU derive from one of those primary clocks. |
| 628 | * For now, assume this parentage won't change. |
| 629 | */ |
| 630 | mckr = at91_sys_read(AT91_PMC_MCKR); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 631 | mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 632 | freq = mck.parent->rate_hz; |
Andrew Victor | a95c729 | 2007-11-19 11:52:09 +0100 | [diff] [blame] | 633 | freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ |
| 634 | if (cpu_is_at91rm9200()) |
| 635 | mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 636 | else if (cpu_is_at91sam9g20()) { |
| 637 | mck.rate_hz = (mckr & AT91_PMC_MDIV) ? |
| 638 | freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ |
| 639 | if (mckr & AT91_PMC_PDIV) |
| 640 | freq /= 2; /* processor clock division */ |
| 641 | } else |
| 642 | mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 643 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 644 | /* Register the PMC's standard clocks */ |
| 645 | for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) |
| 646 | list_add_tail(&standard_pmc_clocks[i]->node, &clocks); |
| 647 | |
Nicolas Ferre | ba45ca4 | 2008-04-08 13:59:18 +0100 | [diff] [blame] | 648 | if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 649 | list_add_tail(&utmi_clk.node, &clocks); |
| 650 | |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 651 | /* MCK and CPU clock are "always on" */ |
| 652 | clk_enable(&mck); |
| 653 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 654 | printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", |
| 655 | freq / 1000000, (unsigned) mck.rate_hz / 1000000, |
| 656 | (unsigned) main_clock / 1000000, |
| 657 | ((unsigned) main_clock % 1000000) / 1000); |
| 658 | |
Andrew Victor | c9b75d1 | 2007-02-08 17:36:34 +0100 | [diff] [blame] | 659 | return 0; |
| 660 | } |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 661 | |
Andrew Victor | c9b75d1 | 2007-02-08 17:36:34 +0100 | [diff] [blame] | 662 | /* |
| 663 | * Several unused clocks may be active. Turn them off. |
| 664 | */ |
| 665 | static int __init at91_clock_reset(void) |
| 666 | { |
| 667 | unsigned long pcdr = 0; |
| 668 | unsigned long scdr = 0; |
| 669 | struct clk *clk; |
| 670 | |
| 671 | list_for_each_entry(clk, &clocks, node) { |
| 672 | if (clk->users > 0) |
| 673 | continue; |
| 674 | |
| 675 | if (clk->mode == pmc_periph_mode) |
| 676 | pcdr |= clk->pmc_mask; |
| 677 | |
| 678 | if (clk->mode == pmc_sys_mode) |
| 679 | scdr |= clk->pmc_mask; |
| 680 | |
| 681 | pr_debug("Clocks: disable unused %s\n", clk->name); |
| 682 | } |
| 683 | |
| 684 | at91_sys_write(AT91_PMC_PCDR, pcdr); |
| 685 | at91_sys_write(AT91_PMC_SCDR, scdr); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 686 | |
| 687 | return 0; |
| 688 | } |
Andrew Victor | c9b75d1 | 2007-02-08 17:36:34 +0100 | [diff] [blame] | 689 | late_initcall(at91_clock_reset); |