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Linus Walleij8d318a52010-03-30 15:33:42 +02001/*
Jonas Aaberg767a9672010-08-09 12:08:34 +00002 * Copyright (C) ST-Ericsson SA 2007-2010
Per Forlin661385f2010-10-06 09:05:28 +00003 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
Jonas Aaberg767a9672010-08-09 12:08:34 +00004 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
Linus Walleij8d318a52010-03-30 15:33:42 +02005 * License terms: GNU General Public License (GPL) version 2
Linus Walleij8d318a52010-03-30 15:33:42 +02006 */
7
8
9#ifndef STE_DMA40_H
10#define STE_DMA40_H
11
12#include <linux/dmaengine.h>
Alexey Dobriyanb7f080c2011-06-16 11:01:34 +000013#include <linux/scatterlist.h>
Linus Walleij8d318a52010-03-30 15:33:42 +020014#include <linux/workqueue.h>
15#include <linux/interrupt.h>
Linus Walleij8d318a52010-03-30 15:33:42 +020016
Per Forlind49278e2010-12-20 18:31:38 +010017/*
18 * Maxium size for a single dma descriptor
19 * Size is limited to 16 bits.
20 * Size is in the units of addr-widths (1,2,4,8 bytes)
21 * Larger transfers will be split up to multiple linked desc
22 */
23#define STEDMA40_MAX_SEG_SIZE 0xFFFF
24
Linus Walleij8d318a52010-03-30 15:33:42 +020025/* dev types for memcpy */
26#define STEDMA40_DEV_DST_MEMORY (-1)
27#define STEDMA40_DEV_SRC_MEMORY (-1)
28
Rabin Vincent38bdbf02010-10-12 13:00:51 +000029enum stedma40_mode {
30 STEDMA40_MODE_LOGICAL = 0,
31 STEDMA40_MODE_PHYSICAL,
32 STEDMA40_MODE_OPERATION,
33};
Linus Walleij8d318a52010-03-30 15:33:42 +020034
Rabin Vincent20a5b6d2010-10-12 13:00:52 +000035enum stedma40_mode_opt {
36 STEDMA40_PCHAN_BASIC_MODE = 0,
37 STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
38 STEDMA40_PCHAN_MODULO_MODE,
39 STEDMA40_PCHAN_DOUBLE_DST_MODE,
40 STEDMA40_LCHAN_SRC_PHY_DST_LOG,
41 STEDMA40_LCHAN_SRC_LOG_DST_PHY,
42};
Linus Walleij8d318a52010-03-30 15:33:42 +020043
44#define STEDMA40_ESIZE_8_BIT 0x0
45#define STEDMA40_ESIZE_16_BIT 0x1
46#define STEDMA40_ESIZE_32_BIT 0x2
47#define STEDMA40_ESIZE_64_BIT 0x3
48
49/* The value 4 indicates that PEN-reg shall be set to 0 */
50#define STEDMA40_PSIZE_PHY_1 0x4
51#define STEDMA40_PSIZE_PHY_2 0x0
52#define STEDMA40_PSIZE_PHY_4 0x1
53#define STEDMA40_PSIZE_PHY_8 0x2
54#define STEDMA40_PSIZE_PHY_16 0x3
55
56/*
57 * The number of elements differ in logical and
58 * physical mode
59 */
60#define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2
61#define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4
62#define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8
63#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
64
Jonas Aaberg767a9672010-08-09 12:08:34 +000065/* Maximum number of possible physical channels */
66#define STEDMA40_MAX_PHYS 32
67
Linus Walleij8d318a52010-03-30 15:33:42 +020068enum stedma40_flow_ctrl {
69 STEDMA40_NO_FLOW_CTRL,
70 STEDMA40_FLOW_CTRL,
71};
72
Linus Walleij8d318a52010-03-30 15:33:42 +020073enum stedma40_periph_data_width {
74 STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
75 STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
76 STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
77 STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
78};
79
Linus Walleij8d318a52010-03-30 15:33:42 +020080enum stedma40_xfer_dir {
Linus Walleij0747c7ba2010-08-09 12:07:36 +000081 STEDMA40_MEM_TO_MEM = 1,
Linus Walleij8d318a52010-03-30 15:33:42 +020082 STEDMA40_MEM_TO_PERIPH,
83 STEDMA40_PERIPH_TO_MEM,
84 STEDMA40_PERIPH_TO_PERIPH
85};
86
87
88/**
Jonas Aaberg3c0f2402010-08-09 12:09:21 +000089 * struct stedma40_chan_cfg - dst/src channel configuration
90 *
Rabin Vincent51f5d742010-10-12 13:00:54 +000091 * @big_endian: true if the src/dst should be read as big endian
Jonas Aaberg3c0f2402010-08-09 12:09:21 +000092 * @data_width: Data width of the src/dst hardware
93 * @p_size: Burst size
94 * @flow_ctrl: Flow control on/off.
95 */
96struct stedma40_half_channel_info {
Rabin Vincent51f5d742010-10-12 13:00:54 +000097 bool big_endian;
Jonas Aaberg3c0f2402010-08-09 12:09:21 +000098 enum stedma40_periph_data_width data_width;
99 int psize;
100 enum stedma40_flow_ctrl flow_ctrl;
101};
102
103/**
Linus Walleij8d318a52010-03-30 15:33:42 +0200104 * struct stedma40_chan_cfg - Structure to be filled by client drivers.
105 *
106 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
Rabin Vincent730c1872010-10-12 13:00:50 +0000107 * @high_priority: true if high-priority
Rabin Vincentac2c0a32011-01-25 11:18:11 +0100108 * @realtime: true if realtime mode is to be enabled. Only available on DMA40
109 * version 3+, i.e DB8500v2+
Rabin Vincent38bdbf02010-10-12 13:00:51 +0000110 * @mode: channel mode: physical, logical, or operation
Rabin Vincent20a5b6d2010-10-12 13:00:52 +0000111 * @mode_opt: options for the chosen channel mode
Linus Walleij8d318a52010-03-30 15:33:42 +0200112 * @src_dev_type: Src device type
113 * @dst_dev_type: Dst device type
114 * @src_info: Parameters for dst half channel
115 * @dst_info: Parameters for dst half channel
Narayanan G5cd326f2011-11-30 19:20:42 +0530116 * @use_fixed_channel: if true, use physical channel specified by phy_channel
117 * @phy_channel: physical channel to use, only if use_fixed_channel is true
Linus Walleij8d318a52010-03-30 15:33:42 +0200118 *
119 * This structure has to be filled by the client drivers.
120 * It is recommended to do all dma configurations for clients in the machine.
121 *
122 */
123struct stedma40_chan_cfg {
124 enum stedma40_xfer_dir dir;
Rabin Vincent730c1872010-10-12 13:00:50 +0000125 bool high_priority;
Rabin Vincentac2c0a32011-01-25 11:18:11 +0100126 bool realtime;
Rabin Vincent38bdbf02010-10-12 13:00:51 +0000127 enum stedma40_mode mode;
Rabin Vincent20a5b6d2010-10-12 13:00:52 +0000128 enum stedma40_mode_opt mode_opt;
Linus Walleij8d318a52010-03-30 15:33:42 +0200129 int src_dev_type;
130 int dst_dev_type;
131 struct stedma40_half_channel_info src_info;
132 struct stedma40_half_channel_info dst_info;
Narayanan G5cd326f2011-11-30 19:20:42 +0530133
134 bool use_fixed_channel;
135 int phy_channel;
Linus Walleij8d318a52010-03-30 15:33:42 +0200136};
137
138/**
139 * struct stedma40_platform_data - Configuration struct for the dma device.
140 *
141 * @dev_len: length of dev_tx and dev_rx
142 * @dev_tx: mapping between destination event line and io address
143 * @dev_rx: mapping between source event line and io address
144 * @memcpy: list of memcpy event lines
145 * @memcpy_len: length of memcpy
146 * @memcpy_conf_phy: default configuration of physical channel memcpy
147 * @memcpy_conf_log: default configuration of logical channel memcpy
Jonas Aaberg59516722010-06-20 21:26:45 +0000148 * @disabled_channels: A vector, ending with -1, that marks physical channels
149 * that are for different reasons not available for the driver.
Linus Walleij8d318a52010-03-30 15:33:42 +0200150 */
151struct stedma40_platform_data {
152 u32 dev_len;
153 const dma_addr_t *dev_tx;
154 const dma_addr_t *dev_rx;
155 int *memcpy;
156 u32 memcpy_len;
157 struct stedma40_chan_cfg *memcpy_conf_phy;
158 struct stedma40_chan_cfg *memcpy_conf_log;
Jonas Aaberg767a9672010-08-09 12:08:34 +0000159 int disabled_channels[STEDMA40_MAX_PHYS];
Narayanan G28c7a192011-11-22 13:56:55 +0530160 bool use_esram_lcla;
Linus Walleij8d318a52010-03-30 15:33:42 +0200161};
162
Linus Walleij9646b792010-10-06 09:05:29 +0000163#ifdef CONFIG_STE_DMA40
Linus Walleij8d318a52010-03-30 15:33:42 +0200164
165/**
166 * stedma40_filter() - Provides stedma40_chan_cfg to the
167 * ste_dma40 dma driver via the dmaengine framework.
168 * does some checking of what's provided.
169 *
170 * Never directly called by client. It used by dmaengine.
171 * @chan: dmaengine handle.
172 * @data: Must be of type: struct stedma40_chan_cfg and is
173 * the configuration of the framework.
174 *
175 *
176 */
177
178bool stedma40_filter(struct dma_chan *chan, void *data);
179
180/**
Linus Walleij8d318a52010-03-30 15:33:42 +0200181 * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
182 * (=device)
183 *
184 * @chan: dmaengine handle
185 * @addr: source or destination physicall address.
186 * @size: bytes to transfer
187 * @direction: direction of transfer
188 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
189 */
190
191static inline struct
192dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
193 dma_addr_t addr,
194 unsigned int size,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530195 enum dma_transfer_direction direction,
Linus Walleij8d318a52010-03-30 15:33:42 +0200196 unsigned long flags)
197{
198 struct scatterlist sg;
199 sg_init_table(&sg, 1);
200 sg.dma_address = addr;
201 sg.length = size;
202
Alexandre Bounine16052822012-03-08 16:11:18 -0500203 return dmaengine_prep_slave_sg(chan, &sg, 1, direction, flags);
Linus Walleij8d318a52010-03-30 15:33:42 +0200204}
205
Linus Walleij9646b792010-10-06 09:05:29 +0000206#else
207static inline bool stedma40_filter(struct dma_chan *chan, void *data)
208{
209 return false;
210}
211
212static inline struct
213dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
214 dma_addr_t addr,
215 unsigned int size,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530216 enum dma_transfer_direction direction,
Linus Walleij9646b792010-10-06 09:05:29 +0000217 unsigned long flags)
218{
219 return NULL;
220}
221#endif
222
Linus Walleij8d318a52010-03-30 15:33:42 +0200223#endif