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LeafOS / LeafOS-Devices / android_kernel_samsung_gta4xl / 7fadcd3a859b218fa27c399db0aa8d6d62ad84a9 / . / arch / m68k / coldfire / m54xx.c
blob: c552851ec61762fa3e476fdc2a547b396a4e62f4 [file] [log] [blame]
Philippe De Muyterea49f8ff2010-09-20 13:11:11 +0200[diff] [blame]1/***************************************************************************/
2
3/*
Greg Ungererece9ae62014-08-19 11:55:24 +1000[diff] [blame]4 * m54xx.c -- platform support for ColdFire 54xx based boards
Philippe De Muyterea49f8ff2010-09-20 13:11:11 +0200[diff] [blame]5 *
6 * Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
Greg Ungerer88be3512011-10-14 15:06:22 +1000[diff] [blame]16#include <linux/mm.h>
Greg Ungerer98122d72012-07-13 16:07:15 +1000[diff] [blame]17#include <linux/clk.h>
Greg Ungerer88be3512011-10-14 15:06:22 +1000[diff] [blame]18#include <linux/bootmem.h>
19#include <asm/pgalloc.h>
Philippe De Muyterea49f8ff2010-09-20 13:11:11 +0200[diff] [blame]20#include <asm/machdep.h>
21#include <asm/coldfire.h>
Greg Ungerer5b2e6552010-11-02 12:05:29 +1000[diff] [blame]22#include <asm/m54xxsim.h>
Philippe De Muyterea49f8ff2010-09-20 13:11:11 +0200[diff] [blame]23#include <asm/mcfuart.h>
Greg Ungerer98122d72012-07-13 16:07:15 +1000[diff] [blame]24#include <asm/mcfclk.h>
Greg Ungerer5b2e6552010-11-02 12:05:29 +1000[diff] [blame]25#include <asm/m54xxgpt.h>
Greg Ungerer88be3512011-10-14 15:06:22 +1000[diff] [blame]26#ifdef CONFIG_MMU
27#include <asm/mmu_context.h>
28#endif
Philippe De Muyterea49f8ff2010-09-20 13:11:11 +0200[diff] [blame]29
30/***************************************************************************/
31
Greg Ungerer98122d72012-07-13 16:07:15 +1000[diff] [blame]32DEFINE_CLK(pll, "pll.0", MCF_CLK);
33DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
34DEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK);
35DEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK);
36DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
37DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
38DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
39DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK);
Steven King2d24b532014-06-30 09:53:19 -0700[diff] [blame]40DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
Greg Ungerer98122d72012-07-13 16:07:15 +1000[diff] [blame]41
42struct clk *mcf_clks[] = {
43 &clk_pll,
44 &clk_sys,
45 &clk_mcfslt0,
46 &clk_mcfslt1,
47 &clk_mcfuart0,
48 &clk_mcfuart1,
49 &clk_mcfuart2,
50 &clk_mcfuart3,
Steven King2d24b532014-06-30 09:53:19 -0700[diff] [blame]51 &clk_mcfi2c0,
Greg Ungerer98122d72012-07-13 16:07:15 +1000[diff] [blame]52 NULL
53};
54
55/***************************************************************************/
56
Greg Ungerer5b2e6552010-11-02 12:05:29 +1000[diff] [blame]57static void __init m54xx_uarts_init(void)
Philippe De Muyterea49f8ff2010-09-20 13:11:11 +0200[diff] [blame]58{
Greg Ungererb9a0c3f2011-12-24 01:08:47 +1000[diff] [blame]59 /* enable io pins */
Greg Ungerer632306f2012-09-18 14:34:04 +1000[diff] [blame]60 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
Greg Ungererb9a0c3f2011-12-24 01:08:47 +1000[diff] [blame]61 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
Greg Ungerer632306f2012-09-18 14:34:04 +1000[diff] [blame]62 MCFGPIO_PAR_PSC1);
Greg Ungererb9a0c3f2011-12-24 01:08:47 +1000[diff] [blame]63 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
Greg Ungerer632306f2012-09-18 14:34:04 +1000[diff] [blame]64 MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
65 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
Philippe De Muyterea49f8ff2010-09-20 13:11:11 +0200[diff] [blame]66}
67
68/***************************************************************************/
69
Steven King2d24b532014-06-30 09:53:19 -0700[diff] [blame]70static void __init m54xx_i2c_init(void)
71{
72#if IS_ENABLED(CONFIG_I2C_IMX)
73 u32 r;
74
75 /* set the fec/i2c/irq pin assignment register for i2c */
76 r = readl(MCF_PAR_FECI2CIRQ);
77 r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL;
78 writel(r, MCF_PAR_FECI2CIRQ);
79#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
80}
81
82/***************************************************************************/
83
Greg Ungerer5b2e6552010-11-02 12:05:29 +1000[diff] [blame]84static void mcf54xx_reset(void)
Philippe De Muyterea49f8ff2010-09-20 13:11:11 +0200[diff] [blame]85{
86 /* disable interrupts and enable the watchdog */
87 asm("movew #0x2700, %sr\n");
Greg Ungerer944c3d82012-09-18 14:51:46 +1000[diff] [blame]88 __raw_writel(0, MCF_GPT_GMS0);
89 __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
Philippe De Muyterea49f8ff2010-09-20 13:11:11 +0200[diff] [blame]90 __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
Greg Ungerer944c3d82012-09-18 14:51:46 +1000[diff] [blame]91 MCF_GPT_GMS0);
Philippe De Muyterea49f8ff2010-09-20 13:11:11 +0200[diff] [blame]92}
93
94/***************************************************************************/
95
96void __init config_BSP(char *commandp, int size)
97{
Greg Ungerer88be3512011-10-14 15:06:22 +1000[diff] [blame]98#ifdef CONFIG_MMU
Greg Ungererf7116062016-08-26 14:24:27 +1000[diff] [blame]99 cf_bootmem_alloc();
Greg Ungerer88be3512011-10-14 15:06:22 +1000[diff] [blame]100 mmu_context_init();
101#endif
Greg Ungerer5b2e6552010-11-02 12:05:29 +1000[diff] [blame]102 mach_reset = mcf54xx_reset;
Greg Ungerer35aefb22012-01-23 15:34:58 +1000[diff] [blame]103 mach_sched_init = hw_timer_init;
Greg Ungerer5b2e6552010-11-02 12:05:29 +1000[diff] [blame]104 m54xx_uarts_init();
Steven King2d24b532014-06-30 09:53:19 -0700[diff] [blame]105 m54xx_i2c_init();
Philippe De Muyterea49f8ff2010-09-20 13:11:11 +0200[diff] [blame]106}
107
108/***************************************************************************/