Ulrich Hecht | 596bdcf | 2014-12-17 17:18:49 +0100 | [diff] [blame] | 1 | * Renesas R8A73A4 Clock Pulse Generator (CPG) |
| 2 | |
| 3 | The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs |
| 4 | and several fixed ratio dividers. |
| 5 | |
| 6 | Required Properties: |
| 7 | |
| 8 | - compatible: Must be "renesas,r8a73a4-cpg-clocks" |
| 9 | |
| 10 | - reg: Base address and length of the memory resource used by the CPG |
| 11 | |
| 12 | - clocks: Reference to the parent clocks ("extal1" and "extal2") |
| 13 | |
| 14 | - #clock-cells: Must be 1 |
| 15 | |
| 16 | - clock-output-names: The names of the clocks. Supported clocks are "main", |
| 17 | "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b", |
| 18 | "m1", "m2", "zx", "zs", and "hp". |
| 19 | |
| 20 | |
| 21 | Example |
| 22 | ------- |
| 23 | |
| 24 | cpg_clocks: cpg_clocks@e6150000 { |
| 25 | compatible = "renesas,r8a73a4-cpg-clocks"; |
| 26 | reg = <0 0xe6150000 0 0x10000>; |
| 27 | clocks = <&extal1_clk>, <&extal2_clk>; |
| 28 | #clock-cells = <1>; |
| 29 | clock-output-names = "main", "pll0", "pll1", "pll2", |
| 30 | "pll2s", "pll2h", "z", "z2", |
| 31 | "i", "m3", "b", "m1", "m2", |
| 32 | "zx", "zs", "hp"; |
| 33 | }; |